2 * Performance events x86 architecture code
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
12 * For licencing details see kernel-base/COPYING
15 #include <linux/perf_event.h>
16 #include <linux/capability.h>
17 #include <linux/notifier.h>
18 #include <linux/hardirq.h>
19 #include <linux/kprobes.h>
20 #include <linux/export.h>
21 #include <linux/init.h>
22 #include <linux/kdebug.h>
23 #include <linux/sched/mm.h>
24 #include <linux/sched/clock.h>
25 #include <linux/uaccess.h>
26 #include <linux/slab.h>
27 #include <linux/cpu.h>
28 #include <linux/bitops.h>
29 #include <linux/device.h>
30 #include <linux/nospec.h>
31 #include <linux/static_call.h>
34 #include <asm/stacktrace.h>
37 #include <asm/alternative.h>
38 #include <asm/mmu_context.h>
39 #include <asm/tlbflush.h>
40 #include <asm/timer.h>
43 #include <asm/unwind.h>
45 #include "perf_event.h"
47 struct x86_pmu x86_pmu __read_mostly;
48 static struct pmu pmu;
50 DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
55 DEFINE_STATIC_KEY_FALSE(rdpmc_never_available_key);
56 DEFINE_STATIC_KEY_FALSE(rdpmc_always_available_key);
57 DEFINE_STATIC_KEY_FALSE(perf_is_hybrid);
60 * This here uses DEFINE_STATIC_CALL_NULL() to get a static_call defined
61 * from just a typename, as opposed to an actual function.
63 DEFINE_STATIC_CALL_NULL(x86_pmu_handle_irq, *x86_pmu.handle_irq);
64 DEFINE_STATIC_CALL_NULL(x86_pmu_disable_all, *x86_pmu.disable_all);
65 DEFINE_STATIC_CALL_NULL(x86_pmu_enable_all, *x86_pmu.enable_all);
66 DEFINE_STATIC_CALL_NULL(x86_pmu_enable, *x86_pmu.enable);
67 DEFINE_STATIC_CALL_NULL(x86_pmu_disable, *x86_pmu.disable);
69 DEFINE_STATIC_CALL_NULL(x86_pmu_assign, *x86_pmu.assign);
71 DEFINE_STATIC_CALL_NULL(x86_pmu_add, *x86_pmu.add);
72 DEFINE_STATIC_CALL_NULL(x86_pmu_del, *x86_pmu.del);
73 DEFINE_STATIC_CALL_NULL(x86_pmu_read, *x86_pmu.read);
75 DEFINE_STATIC_CALL_NULL(x86_pmu_schedule_events, *x86_pmu.schedule_events);
76 DEFINE_STATIC_CALL_NULL(x86_pmu_get_event_constraints, *x86_pmu.get_event_constraints);
77 DEFINE_STATIC_CALL_NULL(x86_pmu_put_event_constraints, *x86_pmu.put_event_constraints);
79 DEFINE_STATIC_CALL_NULL(x86_pmu_start_scheduling, *x86_pmu.start_scheduling);
80 DEFINE_STATIC_CALL_NULL(x86_pmu_commit_scheduling, *x86_pmu.commit_scheduling);
81 DEFINE_STATIC_CALL_NULL(x86_pmu_stop_scheduling, *x86_pmu.stop_scheduling);
83 DEFINE_STATIC_CALL_NULL(x86_pmu_sched_task, *x86_pmu.sched_task);
84 DEFINE_STATIC_CALL_NULL(x86_pmu_swap_task_ctx, *x86_pmu.swap_task_ctx);
86 DEFINE_STATIC_CALL_NULL(x86_pmu_drain_pebs, *x86_pmu.drain_pebs);
87 DEFINE_STATIC_CALL_NULL(x86_pmu_pebs_aliases, *x86_pmu.pebs_aliases);
90 * This one is magic, it will get called even when PMU init fails (because
91 * there is no PMU), in which case it should simply return NULL.
93 DEFINE_STATIC_CALL_RET0(x86_pmu_guest_get_msrs, *x86_pmu.guest_get_msrs);
95 u64 __read_mostly hw_cache_event_ids
96 [PERF_COUNT_HW_CACHE_MAX]
97 [PERF_COUNT_HW_CACHE_OP_MAX]
98 [PERF_COUNT_HW_CACHE_RESULT_MAX];
99 u64 __read_mostly hw_cache_extra_regs
100 [PERF_COUNT_HW_CACHE_MAX]
101 [PERF_COUNT_HW_CACHE_OP_MAX]
102 [PERF_COUNT_HW_CACHE_RESULT_MAX];
105 * Propagate event elapsed time into the generic event.
106 * Can only be executed on the CPU where the event is active.
107 * Returns the delta events processed.
109 u64 x86_perf_event_update(struct perf_event *event)
111 struct hw_perf_event *hwc = &event->hw;
112 int shift = 64 - x86_pmu.cntval_bits;
113 u64 prev_raw_count, new_raw_count;
116 if (unlikely(!hwc->event_base))
119 if (unlikely(is_topdown_count(event)) && x86_pmu.update_topdown_event)
120 return x86_pmu.update_topdown_event(event);
123 * Careful: an NMI might modify the previous event value.
125 * Our tactic to handle this is to first atomically read and
126 * exchange a new raw count - then add that new-prev delta
127 * count to the generic event atomically:
130 prev_raw_count = local64_read(&hwc->prev_count);
131 rdpmcl(hwc->event_base_rdpmc, new_raw_count);
133 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
134 new_raw_count) != prev_raw_count)
138 * Now we have the new raw value and have updated the prev
139 * timestamp already. We can now calculate the elapsed delta
140 * (event-)time and add that to the generic event.
142 * Careful, not all hw sign-extends above the physical width
145 delta = (new_raw_count << shift) - (prev_raw_count << shift);
148 local64_add(delta, &event->count);
149 local64_sub(delta, &hwc->period_left);
151 return new_raw_count;
155 * Find and validate any extra registers to set up.
157 static int x86_pmu_extra_regs(u64 config, struct perf_event *event)
159 struct extra_reg *extra_regs = hybrid(event->pmu, extra_regs);
160 struct hw_perf_event_extra *reg;
161 struct extra_reg *er;
163 reg = &event->hw.extra_reg;
168 for (er = extra_regs; er->msr; er++) {
169 if (er->event != (config & er->config_mask))
171 if (event->attr.config1 & ~er->valid_mask)
173 /* Check if the extra msrs can be safely accessed*/
174 if (!er->extra_msr_access)
178 reg->config = event->attr.config1;
185 static atomic_t active_events;
186 static atomic_t pmc_refcount;
187 static DEFINE_MUTEX(pmc_reserve_mutex);
189 #ifdef CONFIG_X86_LOCAL_APIC
191 static inline int get_possible_num_counters(void)
193 int i, num_counters = x86_pmu.num_counters;
198 for (i = 0; i < x86_pmu.num_hybrid_pmus; i++)
199 num_counters = max_t(int, num_counters, x86_pmu.hybrid_pmu[i].num_counters);
204 static bool reserve_pmc_hardware(void)
206 int i, num_counters = get_possible_num_counters();
208 for (i = 0; i < num_counters; i++) {
209 if (!reserve_perfctr_nmi(x86_pmu_event_addr(i)))
213 for (i = 0; i < num_counters; i++) {
214 if (!reserve_evntsel_nmi(x86_pmu_config_addr(i)))
221 for (i--; i >= 0; i--)
222 release_evntsel_nmi(x86_pmu_config_addr(i));
227 for (i--; i >= 0; i--)
228 release_perfctr_nmi(x86_pmu_event_addr(i));
233 static void release_pmc_hardware(void)
235 int i, num_counters = get_possible_num_counters();
237 for (i = 0; i < num_counters; i++) {
238 release_perfctr_nmi(x86_pmu_event_addr(i));
239 release_evntsel_nmi(x86_pmu_config_addr(i));
245 static bool reserve_pmc_hardware(void) { return true; }
246 static void release_pmc_hardware(void) {}
250 bool check_hw_exists(struct pmu *pmu, int num_counters, int num_counters_fixed)
252 u64 val, val_fail = -1, val_new= ~0;
253 int i, reg, reg_fail = -1, ret = 0;
258 * Check to see if the BIOS enabled any of the counters, if so
261 for (i = 0; i < num_counters; i++) {
262 reg = x86_pmu_config_addr(i);
263 ret = rdmsrl_safe(reg, &val);
266 if (val & ARCH_PERFMON_EVENTSEL_ENABLE) {
275 if (num_counters_fixed) {
276 reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
277 ret = rdmsrl_safe(reg, &val);
280 for (i = 0; i < num_counters_fixed; i++) {
281 if (fixed_counter_disabled(i, pmu))
283 if (val & (0x03ULL << i*4)) {
292 * If all the counters are enabled, the below test will always
293 * fail. The tools will also become useless in this scenario.
294 * Just fail and disable the hardware counters.
297 if (reg_safe == -1) {
303 * Read the current value, change it and read it back to see if it
304 * matches, this is needed to detect certain hardware emulators
305 * (qemu/kvm) that don't trap on the MSR access and always return 0s.
307 reg = x86_pmu_event_addr(reg_safe);
308 if (rdmsrl_safe(reg, &val))
311 ret = wrmsrl_safe(reg, val);
312 ret |= rdmsrl_safe(reg, &val_new);
313 if (ret || val != val_new)
317 * We still allow the PMU driver to operate:
320 pr_cont("Broken BIOS detected, complain to your hardware vendor.\n");
321 pr_err(FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n",
328 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
329 pr_cont("PMU not available due to virtualization, using software events only.\n");
331 pr_cont("Broken PMU hardware detected, using software events only.\n");
332 pr_err("Failed to access perfctr msr (MSR %x is %Lx)\n",
339 static void hw_perf_event_destroy(struct perf_event *event)
341 x86_release_hardware();
342 atomic_dec(&active_events);
345 void hw_perf_lbr_event_destroy(struct perf_event *event)
347 hw_perf_event_destroy(event);
349 /* undo the lbr/bts event accounting */
350 x86_del_exclusive(x86_lbr_exclusive_lbr);
353 static inline int x86_pmu_initialized(void)
355 return x86_pmu.handle_irq != NULL;
359 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event)
361 struct perf_event_attr *attr = &event->attr;
362 unsigned int cache_type, cache_op, cache_result;
365 config = attr->config;
367 cache_type = (config >> 0) & 0xff;
368 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
370 cache_type = array_index_nospec(cache_type, PERF_COUNT_HW_CACHE_MAX);
372 cache_op = (config >> 8) & 0xff;
373 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
375 cache_op = array_index_nospec(cache_op, PERF_COUNT_HW_CACHE_OP_MAX);
377 cache_result = (config >> 16) & 0xff;
378 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
380 cache_result = array_index_nospec(cache_result, PERF_COUNT_HW_CACHE_RESULT_MAX);
382 val = hybrid_var(event->pmu, hw_cache_event_ids)[cache_type][cache_op][cache_result];
390 attr->config1 = hybrid_var(event->pmu, hw_cache_extra_regs)[cache_type][cache_op][cache_result];
391 return x86_pmu_extra_regs(val, event);
394 int x86_reserve_hardware(void)
398 if (!atomic_inc_not_zero(&pmc_refcount)) {
399 mutex_lock(&pmc_reserve_mutex);
400 if (atomic_read(&pmc_refcount) == 0) {
401 if (!reserve_pmc_hardware()) {
404 reserve_ds_buffers();
405 reserve_lbr_buffers();
409 atomic_inc(&pmc_refcount);
410 mutex_unlock(&pmc_reserve_mutex);
416 void x86_release_hardware(void)
418 if (atomic_dec_and_mutex_lock(&pmc_refcount, &pmc_reserve_mutex)) {
419 release_pmc_hardware();
420 release_ds_buffers();
421 release_lbr_buffers();
422 mutex_unlock(&pmc_reserve_mutex);
427 * Check if we can create event of a certain type (that no conflicting events
430 int x86_add_exclusive(unsigned int what)
435 * When lbr_pt_coexist we allow PT to coexist with either LBR or BTS.
436 * LBR and BTS are still mutually exclusive.
438 if (x86_pmu.lbr_pt_coexist && what == x86_lbr_exclusive_pt)
441 if (!atomic_inc_not_zero(&x86_pmu.lbr_exclusive[what])) {
442 mutex_lock(&pmc_reserve_mutex);
443 for (i = 0; i < ARRAY_SIZE(x86_pmu.lbr_exclusive); i++) {
444 if (i != what && atomic_read(&x86_pmu.lbr_exclusive[i]))
447 atomic_inc(&x86_pmu.lbr_exclusive[what]);
448 mutex_unlock(&pmc_reserve_mutex);
452 atomic_inc(&active_events);
456 mutex_unlock(&pmc_reserve_mutex);
460 void x86_del_exclusive(unsigned int what)
462 atomic_dec(&active_events);
465 * See the comment in x86_add_exclusive().
467 if (x86_pmu.lbr_pt_coexist && what == x86_lbr_exclusive_pt)
470 atomic_dec(&x86_pmu.lbr_exclusive[what]);
473 int x86_setup_perfctr(struct perf_event *event)
475 struct perf_event_attr *attr = &event->attr;
476 struct hw_perf_event *hwc = &event->hw;
479 if (!is_sampling_event(event)) {
480 hwc->sample_period = x86_pmu.max_period;
481 hwc->last_period = hwc->sample_period;
482 local64_set(&hwc->period_left, hwc->sample_period);
485 if (attr->type == event->pmu->type)
486 return x86_pmu_extra_regs(event->attr.config, event);
488 if (attr->type == PERF_TYPE_HW_CACHE)
489 return set_ext_hw_attr(hwc, event);
491 if (attr->config >= x86_pmu.max_events)
494 attr->config = array_index_nospec((unsigned long)attr->config, x86_pmu.max_events);
499 config = x86_pmu.event_map(attr->config);
507 hwc->config |= config;
513 * check that branch_sample_type is compatible with
514 * settings needed for precise_ip > 1 which implies
515 * using the LBR to capture ALL taken branches at the
516 * priv levels of the measurement
518 static inline int precise_br_compat(struct perf_event *event)
520 u64 m = event->attr.branch_sample_type;
523 /* must capture all branches */
524 if (!(m & PERF_SAMPLE_BRANCH_ANY))
527 m &= PERF_SAMPLE_BRANCH_KERNEL | PERF_SAMPLE_BRANCH_USER;
529 if (!event->attr.exclude_user)
530 b |= PERF_SAMPLE_BRANCH_USER;
532 if (!event->attr.exclude_kernel)
533 b |= PERF_SAMPLE_BRANCH_KERNEL;
536 * ignore PERF_SAMPLE_BRANCH_HV, not supported on x86
542 int x86_pmu_max_precise(void)
546 /* Support for constant skid */
547 if (x86_pmu.pebs_active && !x86_pmu.pebs_broken) {
550 /* Support for IP fixup */
551 if (x86_pmu.lbr_nr || x86_pmu.intel_cap.pebs_format >= 2)
554 if (x86_pmu.pebs_prec_dist)
560 int x86_pmu_hw_config(struct perf_event *event)
562 if (event->attr.precise_ip) {
563 int precise = x86_pmu_max_precise();
565 if (event->attr.precise_ip > precise)
568 /* There's no sense in having PEBS for non sampling events: */
569 if (!is_sampling_event(event))
573 * check that PEBS LBR correction does not conflict with
574 * whatever the user is asking with attr->branch_sample_type
576 if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format < 2) {
577 u64 *br_type = &event->attr.branch_sample_type;
579 if (has_branch_stack(event)) {
580 if (!precise_br_compat(event))
583 /* branch_sample_type is compatible */
587 * user did not specify branch_sample_type
589 * For PEBS fixups, we capture all
590 * the branches at the priv level of the
593 *br_type = PERF_SAMPLE_BRANCH_ANY;
595 if (!event->attr.exclude_user)
596 *br_type |= PERF_SAMPLE_BRANCH_USER;
598 if (!event->attr.exclude_kernel)
599 *br_type |= PERF_SAMPLE_BRANCH_KERNEL;
603 if (event->attr.branch_sample_type & PERF_SAMPLE_BRANCH_CALL_STACK)
604 event->attach_state |= PERF_ATTACH_TASK_DATA;
608 * (keep 'enabled' bit clear for now)
610 event->hw.config = ARCH_PERFMON_EVENTSEL_INT;
613 * Count user and OS events unless requested not to
615 if (!event->attr.exclude_user)
616 event->hw.config |= ARCH_PERFMON_EVENTSEL_USR;
617 if (!event->attr.exclude_kernel)
618 event->hw.config |= ARCH_PERFMON_EVENTSEL_OS;
620 if (event->attr.type == event->pmu->type)
621 event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK;
623 if (event->attr.sample_period && x86_pmu.limit_period) {
624 if (x86_pmu.limit_period(event, event->attr.sample_period) >
625 event->attr.sample_period)
629 /* sample_regs_user never support XMM registers */
630 if (unlikely(event->attr.sample_regs_user & PERF_REG_EXTENDED_MASK))
633 * Besides the general purpose registers, XMM registers may
634 * be collected in PEBS on some platforms, e.g. Icelake
636 if (unlikely(event->attr.sample_regs_intr & PERF_REG_EXTENDED_MASK)) {
637 if (!(event->pmu->capabilities & PERF_PMU_CAP_EXTENDED_REGS))
640 if (!event->attr.precise_ip)
644 return x86_setup_perfctr(event);
648 * Setup the hardware configuration for a given attr_type
650 static int __x86_pmu_event_init(struct perf_event *event)
654 if (!x86_pmu_initialized())
657 err = x86_reserve_hardware();
661 atomic_inc(&active_events);
662 event->destroy = hw_perf_event_destroy;
665 event->hw.last_cpu = -1;
666 event->hw.last_tag = ~0ULL;
669 event->hw.extra_reg.idx = EXTRA_REG_NONE;
670 event->hw.branch_reg.idx = EXTRA_REG_NONE;
672 return x86_pmu.hw_config(event);
675 void x86_pmu_disable_all(void)
677 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
680 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
681 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
684 if (!test_bit(idx, cpuc->active_mask))
686 rdmsrl(x86_pmu_config_addr(idx), val);
687 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
689 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
690 wrmsrl(x86_pmu_config_addr(idx), val);
691 if (is_counter_pair(hwc))
692 wrmsrl(x86_pmu_config_addr(idx + 1), 0);
696 struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr)
698 return static_call(x86_pmu_guest_get_msrs)(nr);
700 EXPORT_SYMBOL_GPL(perf_guest_get_msrs);
703 * There may be PMI landing after enabled=0. The PMI hitting could be before or
706 * If PMI hits before disable_all, the PMU will be disabled in the NMI handler.
707 * It will not be re-enabled in the NMI handler again, because enabled=0. After
708 * handling the NMI, disable_all will be called, which will not change the
709 * state either. If PMI hits after disable_all, the PMU is already disabled
710 * before entering NMI handler. The NMI handler will not change the state
713 * So either situation is harmless.
715 static void x86_pmu_disable(struct pmu *pmu)
717 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
719 if (!x86_pmu_initialized())
729 static_call(x86_pmu_disable_all)();
732 void x86_pmu_enable_all(int added)
734 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
737 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
738 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
740 if (!test_bit(idx, cpuc->active_mask))
743 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
747 static inline int is_x86_event(struct perf_event *event)
752 return event->pmu == &pmu;
754 for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) {
755 if (event->pmu == &x86_pmu.hybrid_pmu[i].pmu)
762 struct pmu *x86_get_pmu(unsigned int cpu)
764 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
767 * All CPUs of the hybrid type have been offline.
768 * The x86_get_pmu() should not be invoked.
770 if (WARN_ON_ONCE(!cpuc->pmu))
776 * Event scheduler state:
778 * Assign events iterating over all events and counters, beginning
779 * with events with least weights first. Keep the current iterator
780 * state in struct sched_state.
784 int event; /* event index */
785 int counter; /* counter index */
786 int unassigned; /* number of events to be assigned left */
787 int nr_gp; /* number of GP counters used */
791 /* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */
792 #define SCHED_STATES_MAX 2
799 struct event_constraint **constraints;
800 struct sched_state state;
801 struct sched_state saved[SCHED_STATES_MAX];
805 * Initialize iterator that runs through all events and counters.
807 static void perf_sched_init(struct perf_sched *sched, struct event_constraint **constraints,
808 int num, int wmin, int wmax, int gpmax)
812 memset(sched, 0, sizeof(*sched));
813 sched->max_events = num;
814 sched->max_weight = wmax;
815 sched->max_gp = gpmax;
816 sched->constraints = constraints;
818 for (idx = 0; idx < num; idx++) {
819 if (constraints[idx]->weight == wmin)
823 sched->state.event = idx; /* start with min weight */
824 sched->state.weight = wmin;
825 sched->state.unassigned = num;
828 static void perf_sched_save_state(struct perf_sched *sched)
830 if (WARN_ON_ONCE(sched->saved_states >= SCHED_STATES_MAX))
833 sched->saved[sched->saved_states] = sched->state;
834 sched->saved_states++;
837 static bool perf_sched_restore_state(struct perf_sched *sched)
839 if (!sched->saved_states)
842 sched->saved_states--;
843 sched->state = sched->saved[sched->saved_states];
845 /* this assignment didn't work out */
846 /* XXX broken vs EVENT_PAIR */
847 sched->state.used &= ~BIT_ULL(sched->state.counter);
849 /* try the next one */
850 sched->state.counter++;
856 * Select a counter for the current event to schedule. Return true on
859 static bool __perf_sched_find_counter(struct perf_sched *sched)
861 struct event_constraint *c;
864 if (!sched->state.unassigned)
867 if (sched->state.event >= sched->max_events)
870 c = sched->constraints[sched->state.event];
871 /* Prefer fixed purpose counters */
872 if (c->idxmsk64 & (~0ULL << INTEL_PMC_IDX_FIXED)) {
873 idx = INTEL_PMC_IDX_FIXED;
874 for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_MAX) {
875 u64 mask = BIT_ULL(idx);
877 if (sched->state.used & mask)
880 sched->state.used |= mask;
885 /* Grab the first unused counter starting with idx */
886 idx = sched->state.counter;
887 for_each_set_bit_from(idx, c->idxmsk, INTEL_PMC_IDX_FIXED) {
888 u64 mask = BIT_ULL(idx);
890 if (c->flags & PERF_X86_EVENT_PAIR)
893 if (sched->state.used & mask)
896 if (sched->state.nr_gp++ >= sched->max_gp)
899 sched->state.used |= mask;
906 sched->state.counter = idx;
909 perf_sched_save_state(sched);
914 static bool perf_sched_find_counter(struct perf_sched *sched)
916 while (!__perf_sched_find_counter(sched)) {
917 if (!perf_sched_restore_state(sched))
925 * Go through all unassigned events and find the next one to schedule.
926 * Take events with the least weight first. Return true on success.
928 static bool perf_sched_next_event(struct perf_sched *sched)
930 struct event_constraint *c;
932 if (!sched->state.unassigned || !--sched->state.unassigned)
937 sched->state.event++;
938 if (sched->state.event >= sched->max_events) {
940 sched->state.event = 0;
941 sched->state.weight++;
942 if (sched->state.weight > sched->max_weight)
945 c = sched->constraints[sched->state.event];
946 } while (c->weight != sched->state.weight);
948 sched->state.counter = 0; /* start with first counter */
954 * Assign a counter for each event.
956 int perf_assign_events(struct event_constraint **constraints, int n,
957 int wmin, int wmax, int gpmax, int *assign)
959 struct perf_sched sched;
961 perf_sched_init(&sched, constraints, n, wmin, wmax, gpmax);
964 if (!perf_sched_find_counter(&sched))
967 assign[sched.state.event] = sched.state.counter;
968 } while (perf_sched_next_event(&sched));
970 return sched.state.unassigned;
972 EXPORT_SYMBOL_GPL(perf_assign_events);
974 int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
976 int num_counters = hybrid(cpuc->pmu, num_counters);
977 struct event_constraint *c;
978 struct perf_event *e;
979 int n0, i, wmin, wmax, unsched = 0;
980 struct hw_perf_event *hwc;
984 * Compute the number of events already present; see x86_pmu_add(),
985 * validate_group() and x86_pmu_commit_txn(). For the former two
986 * cpuc->n_events hasn't been updated yet, while for the latter
987 * cpuc->n_txn contains the number of events added in the current
991 if (cpuc->txn_flags & PERF_PMU_TXN_ADD)
994 static_call_cond(x86_pmu_start_scheduling)(cpuc);
996 for (i = 0, wmin = X86_PMC_IDX_MAX, wmax = 0; i < n; i++) {
997 c = cpuc->event_constraint[i];
1000 * Previously scheduled events should have a cached constraint,
1001 * while new events should not have one.
1003 WARN_ON_ONCE((c && i >= n0) || (!c && i < n0));
1006 * Request constraints for new events; or for those events that
1007 * have a dynamic constraint -- for those the constraint can
1008 * change due to external factors (sibling state, allow_tfa).
1010 if (!c || (c->flags & PERF_X86_EVENT_DYNAMIC)) {
1011 c = static_call(x86_pmu_get_event_constraints)(cpuc, i, cpuc->event_list[i]);
1012 cpuc->event_constraint[i] = c;
1015 wmin = min(wmin, c->weight);
1016 wmax = max(wmax, c->weight);
1020 * fastpath, try to reuse previous register
1022 for (i = 0; i < n; i++) {
1025 hwc = &cpuc->event_list[i]->hw;
1026 c = cpuc->event_constraint[i];
1028 /* never assigned */
1032 /* constraint still honored */
1033 if (!test_bit(hwc->idx, c->idxmsk))
1036 mask = BIT_ULL(hwc->idx);
1037 if (is_counter_pair(hwc))
1040 /* not already used */
1041 if (used_mask & mask)
1047 assign[i] = hwc->idx;
1052 int gpmax = num_counters;
1055 * Do not allow scheduling of more than half the available
1058 * This helps avoid counter starvation of sibling thread by
1059 * ensuring at most half the counters cannot be in exclusive
1060 * mode. There is no designated counters for the limits. Any
1061 * N/2 counters can be used. This helps with events with
1062 * specific counter constraints.
1064 if (is_ht_workaround_enabled() && !cpuc->is_fake &&
1065 READ_ONCE(cpuc->excl_cntrs->exclusive_present))
1069 * Reduce the amount of available counters to allow fitting
1070 * the extra Merge events needed by large increment events.
1072 if (x86_pmu.flags & PMU_FL_PAIR) {
1073 gpmax = num_counters - cpuc->n_pair;
1074 WARN_ON(gpmax <= 0);
1077 unsched = perf_assign_events(cpuc->event_constraint, n, wmin,
1078 wmax, gpmax, assign);
1082 * In case of success (unsched = 0), mark events as committed,
1083 * so we do not put_constraint() in case new events are added
1084 * and fail to be scheduled
1086 * We invoke the lower level commit callback to lock the resource
1088 * We do not need to do all of this in case we are called to
1089 * validate an event group (assign == NULL)
1091 if (!unsched && assign) {
1092 for (i = 0; i < n; i++)
1093 static_call_cond(x86_pmu_commit_scheduling)(cpuc, i, assign[i]);
1095 for (i = n0; i < n; i++) {
1096 e = cpuc->event_list[i];
1099 * release events that failed scheduling
1101 static_call_cond(x86_pmu_put_event_constraints)(cpuc, e);
1103 cpuc->event_constraint[i] = NULL;
1107 static_call_cond(x86_pmu_stop_scheduling)(cpuc);
1109 return unsched ? -EINVAL : 0;
1112 static int add_nr_metric_event(struct cpu_hw_events *cpuc,
1113 struct perf_event *event)
1115 if (is_metric_event(event)) {
1116 if (cpuc->n_metric == INTEL_TD_METRIC_NUM)
1119 cpuc->n_txn_metric++;
1125 static void del_nr_metric_event(struct cpu_hw_events *cpuc,
1126 struct perf_event *event)
1128 if (is_metric_event(event))
1132 static int collect_event(struct cpu_hw_events *cpuc, struct perf_event *event,
1133 int max_count, int n)
1135 union perf_capabilities intel_cap = hybrid(cpuc->pmu, intel_cap);
1137 if (intel_cap.perf_metrics && add_nr_metric_event(cpuc, event))
1140 if (n >= max_count + cpuc->n_metric)
1143 cpuc->event_list[n] = event;
1144 if (is_counter_pair(&event->hw)) {
1153 * dogrp: true if must collect siblings events (group)
1154 * returns total number of events and error code
1156 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
1158 int num_counters = hybrid(cpuc->pmu, num_counters);
1159 int num_counters_fixed = hybrid(cpuc->pmu, num_counters_fixed);
1160 struct perf_event *event;
1163 max_count = num_counters + num_counters_fixed;
1165 /* current number of events already accepted */
1167 if (!cpuc->n_events)
1168 cpuc->pebs_output = 0;
1170 if (!cpuc->is_fake && leader->attr.precise_ip) {
1172 * For PEBS->PT, if !aux_event, the group leader (PT) went
1173 * away, the group was broken down and this singleton event
1174 * can't schedule any more.
1176 if (is_pebs_pt(leader) && !leader->aux_event)
1180 * pebs_output: 0: no PEBS so far, 1: PT, 2: DS
1182 if (cpuc->pebs_output &&
1183 cpuc->pebs_output != is_pebs_pt(leader) + 1)
1186 cpuc->pebs_output = is_pebs_pt(leader) + 1;
1189 if (is_x86_event(leader)) {
1190 if (collect_event(cpuc, leader, max_count, n))
1198 for_each_sibling_event(event, leader) {
1199 if (!is_x86_event(event) || event->state <= PERF_EVENT_STATE_OFF)
1202 if (collect_event(cpuc, event, max_count, n))
1210 static inline void x86_assign_hw_event(struct perf_event *event,
1211 struct cpu_hw_events *cpuc, int i)
1213 struct hw_perf_event *hwc = &event->hw;
1216 idx = hwc->idx = cpuc->assign[i];
1217 hwc->last_cpu = smp_processor_id();
1218 hwc->last_tag = ++cpuc->tags[i];
1220 static_call_cond(x86_pmu_assign)(event, idx);
1223 case INTEL_PMC_IDX_FIXED_BTS:
1224 case INTEL_PMC_IDX_FIXED_VLBR:
1225 hwc->config_base = 0;
1226 hwc->event_base = 0;
1229 case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END:
1230 /* All the metric events are mapped onto the fixed counter 3. */
1231 idx = INTEL_PMC_IDX_FIXED_SLOTS;
1233 case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS-1:
1234 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
1235 hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 +
1236 (idx - INTEL_PMC_IDX_FIXED);
1237 hwc->event_base_rdpmc = (idx - INTEL_PMC_IDX_FIXED) |
1238 INTEL_PMC_FIXED_RDPMC_BASE;
1242 hwc->config_base = x86_pmu_config_addr(hwc->idx);
1243 hwc->event_base = x86_pmu_event_addr(hwc->idx);
1244 hwc->event_base_rdpmc = x86_pmu_rdpmc_index(hwc->idx);
1250 * x86_perf_rdpmc_index - Return PMC counter used for event
1251 * @event: the perf_event to which the PMC counter was assigned
1253 * The counter assigned to this performance event may change if interrupts
1254 * are enabled. This counter should thus never be used while interrupts are
1255 * enabled. Before this function is used to obtain the assigned counter the
1256 * event should be checked for validity using, for example,
1257 * perf_event_read_local(), within the same interrupt disabled section in
1258 * which this counter is planned to be used.
1260 * Return: The index of the performance monitoring counter assigned to
1263 int x86_perf_rdpmc_index(struct perf_event *event)
1265 lockdep_assert_irqs_disabled();
1267 return event->hw.event_base_rdpmc;
1270 static inline int match_prev_assignment(struct hw_perf_event *hwc,
1271 struct cpu_hw_events *cpuc,
1274 return hwc->idx == cpuc->assign[i] &&
1275 hwc->last_cpu == smp_processor_id() &&
1276 hwc->last_tag == cpuc->tags[i];
1279 static void x86_pmu_start(struct perf_event *event, int flags);
1281 static void x86_pmu_enable(struct pmu *pmu)
1283 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1284 struct perf_event *event;
1285 struct hw_perf_event *hwc;
1286 int i, added = cpuc->n_added;
1288 if (!x86_pmu_initialized())
1294 if (cpuc->n_added) {
1295 int n_running = cpuc->n_events - cpuc->n_added;
1297 * apply assignment obtained either from
1298 * hw_perf_group_sched_in() or x86_pmu_enable()
1300 * step1: save events moving to new counters
1302 for (i = 0; i < n_running; i++) {
1303 event = cpuc->event_list[i];
1307 * we can avoid reprogramming counter if:
1308 * - assigned same counter as last time
1309 * - running on same CPU as last time
1310 * - no other event has used the counter since
1312 if (hwc->idx == -1 ||
1313 match_prev_assignment(hwc, cpuc, i))
1317 * Ensure we don't accidentally enable a stopped
1318 * counter simply because we rescheduled.
1320 if (hwc->state & PERF_HES_STOPPED)
1321 hwc->state |= PERF_HES_ARCH;
1323 x86_pmu_stop(event, PERF_EF_UPDATE);
1327 * step2: reprogram moved events into new counters
1329 for (i = 0; i < cpuc->n_events; i++) {
1330 event = cpuc->event_list[i];
1333 if (!match_prev_assignment(hwc, cpuc, i))
1334 x86_assign_hw_event(event, cpuc, i);
1335 else if (i < n_running)
1338 if (hwc->state & PERF_HES_ARCH)
1342 * if cpuc->enabled = 0, then no wrmsr as
1343 * per x86_pmu_enable_event()
1345 x86_pmu_start(event, PERF_EF_RELOAD);
1348 perf_events_lapic_init();
1354 static_call(x86_pmu_enable_all)(added);
1357 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
1360 * Set the next IRQ period, based on the hwc->period_left value.
1361 * To be called with the event disabled in hw:
1363 int x86_perf_event_set_period(struct perf_event *event)
1365 struct hw_perf_event *hwc = &event->hw;
1366 s64 left = local64_read(&hwc->period_left);
1367 s64 period = hwc->sample_period;
1368 int ret = 0, idx = hwc->idx;
1370 if (unlikely(!hwc->event_base))
1373 if (unlikely(is_topdown_count(event)) &&
1374 x86_pmu.set_topdown_event_period)
1375 return x86_pmu.set_topdown_event_period(event);
1378 * If we are way outside a reasonable range then just skip forward:
1380 if (unlikely(left <= -period)) {
1382 local64_set(&hwc->period_left, left);
1383 hwc->last_period = period;
1387 if (unlikely(left <= 0)) {
1389 local64_set(&hwc->period_left, left);
1390 hwc->last_period = period;
1394 * Quirk: certain CPUs dont like it if just 1 hw_event is left:
1396 if (unlikely(left < 2))
1399 if (left > x86_pmu.max_period)
1400 left = x86_pmu.max_period;
1402 if (x86_pmu.limit_period)
1403 left = x86_pmu.limit_period(event, left);
1405 per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
1408 * The hw event starts counting from this event offset,
1409 * mark it to be able to extra future deltas:
1411 local64_set(&hwc->prev_count, (u64)-left);
1413 wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask);
1416 * Sign extend the Merge event counter's upper 16 bits since
1417 * we currently declare a 48-bit counter width
1419 if (is_counter_pair(hwc))
1420 wrmsrl(x86_pmu_event_addr(idx + 1), 0xffff);
1423 * Due to erratum on certan cpu we need
1424 * a second write to be sure the register
1425 * is updated properly
1427 if (x86_pmu.perfctr_second_write) {
1428 wrmsrl(hwc->event_base,
1429 (u64)(-left) & x86_pmu.cntval_mask);
1432 perf_event_update_userpage(event);
1437 void x86_pmu_enable_event(struct perf_event *event)
1439 if (__this_cpu_read(cpu_hw_events.enabled))
1440 __x86_pmu_enable_event(&event->hw,
1441 ARCH_PERFMON_EVENTSEL_ENABLE);
1445 * Add a single event to the PMU.
1447 * The event is added to the group of enabled events
1448 * but only if it can be scheduled with existing events.
1450 static int x86_pmu_add(struct perf_event *event, int flags)
1452 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1453 struct hw_perf_event *hwc;
1454 int assign[X86_PMC_IDX_MAX];
1459 n0 = cpuc->n_events;
1460 ret = n = collect_events(cpuc, event, false);
1464 hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
1465 if (!(flags & PERF_EF_START))
1466 hwc->state |= PERF_HES_ARCH;
1469 * If group events scheduling transaction was started,
1470 * skip the schedulability test here, it will be performed
1471 * at commit time (->commit_txn) as a whole.
1473 * If commit fails, we'll call ->del() on all events
1474 * for which ->add() was called.
1476 if (cpuc->txn_flags & PERF_PMU_TXN_ADD)
1479 ret = static_call(x86_pmu_schedule_events)(cpuc, n, assign);
1483 * copy new assignment, now we know it is possible
1484 * will be used by hw_perf_enable()
1486 memcpy(cpuc->assign, assign, n*sizeof(int));
1490 * Commit the collect_events() state. See x86_pmu_del() and
1494 cpuc->n_added += n - n0;
1495 cpuc->n_txn += n - n0;
1498 * This is before x86_pmu_enable() will call x86_pmu_start(),
1499 * so we enable LBRs before an event needs them etc..
1501 static_call_cond(x86_pmu_add)(event);
1508 static void x86_pmu_start(struct perf_event *event, int flags)
1510 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1511 int idx = event->hw.idx;
1513 if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
1516 if (WARN_ON_ONCE(idx == -1))
1519 if (flags & PERF_EF_RELOAD) {
1520 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
1521 x86_perf_event_set_period(event);
1524 event->hw.state = 0;
1526 cpuc->events[idx] = event;
1527 __set_bit(idx, cpuc->active_mask);
1528 static_call(x86_pmu_enable)(event);
1529 perf_event_update_userpage(event);
1532 void perf_event_print_debug(void)
1534 u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
1536 int cpu = smp_processor_id();
1537 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1538 int num_counters = hybrid(cpuc->pmu, num_counters);
1539 int num_counters_fixed = hybrid(cpuc->pmu, num_counters_fixed);
1540 struct event_constraint *pebs_constraints = hybrid(cpuc->pmu, pebs_constraints);
1541 unsigned long flags;
1547 local_irq_save(flags);
1549 if (x86_pmu.version >= 2) {
1550 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1551 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1552 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1553 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1556 pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl);
1557 pr_info("CPU#%d: status: %016llx\n", cpu, status);
1558 pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow);
1559 pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed);
1560 if (pebs_constraints) {
1561 rdmsrl(MSR_IA32_PEBS_ENABLE, pebs);
1562 pr_info("CPU#%d: pebs: %016llx\n", cpu, pebs);
1564 if (x86_pmu.lbr_nr) {
1565 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
1566 pr_info("CPU#%d: debugctl: %016llx\n", cpu, debugctl);
1569 pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask);
1571 for (idx = 0; idx < num_counters; idx++) {
1572 rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl);
1573 rdmsrl(x86_pmu_event_addr(idx), pmc_count);
1575 prev_left = per_cpu(pmc_prev_left[idx], cpu);
1577 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
1578 cpu, idx, pmc_ctrl);
1579 pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
1580 cpu, idx, pmc_count);
1581 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
1582 cpu, idx, prev_left);
1584 for (idx = 0; idx < num_counters_fixed; idx++) {
1585 if (fixed_counter_disabled(idx, cpuc->pmu))
1587 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1589 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1590 cpu, idx, pmc_count);
1592 local_irq_restore(flags);
1595 void x86_pmu_stop(struct perf_event *event, int flags)
1597 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1598 struct hw_perf_event *hwc = &event->hw;
1600 if (test_bit(hwc->idx, cpuc->active_mask)) {
1601 static_call(x86_pmu_disable)(event);
1602 __clear_bit(hwc->idx, cpuc->active_mask);
1603 cpuc->events[hwc->idx] = NULL;
1604 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
1605 hwc->state |= PERF_HES_STOPPED;
1608 if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
1610 * Drain the remaining delta count out of a event
1611 * that we are disabling:
1613 x86_perf_event_update(event);
1614 hwc->state |= PERF_HES_UPTODATE;
1618 static void x86_pmu_del(struct perf_event *event, int flags)
1620 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1621 union perf_capabilities intel_cap = hybrid(cpuc->pmu, intel_cap);
1625 * If we're called during a txn, we only need to undo x86_pmu.add.
1626 * The events never got scheduled and ->cancel_txn will truncate
1629 * XXX assumes any ->del() called during a TXN will only be on
1630 * an event added during that same TXN.
1632 if (cpuc->txn_flags & PERF_PMU_TXN_ADD)
1635 __set_bit(event->hw.idx, cpuc->dirty);
1638 * Not a TXN, therefore cleanup properly.
1640 x86_pmu_stop(event, PERF_EF_UPDATE);
1642 for (i = 0; i < cpuc->n_events; i++) {
1643 if (event == cpuc->event_list[i])
1647 if (WARN_ON_ONCE(i == cpuc->n_events)) /* called ->del() without ->add() ? */
1650 /* If we have a newly added event; make sure to decrease n_added. */
1651 if (i >= cpuc->n_events - cpuc->n_added)
1654 static_call_cond(x86_pmu_put_event_constraints)(cpuc, event);
1656 /* Delete the array entry. */
1657 while (++i < cpuc->n_events) {
1658 cpuc->event_list[i-1] = cpuc->event_list[i];
1659 cpuc->event_constraint[i-1] = cpuc->event_constraint[i];
1661 cpuc->event_constraint[i-1] = NULL;
1663 if (intel_cap.perf_metrics)
1664 del_nr_metric_event(cpuc, event);
1666 perf_event_update_userpage(event);
1671 * This is after x86_pmu_stop(); so we disable LBRs after any
1672 * event can need them etc..
1674 static_call_cond(x86_pmu_del)(event);
1677 int x86_pmu_handle_irq(struct pt_regs *regs)
1679 struct perf_sample_data data;
1680 struct cpu_hw_events *cpuc;
1681 struct perf_event *event;
1682 int idx, handled = 0;
1685 cpuc = this_cpu_ptr(&cpu_hw_events);
1688 * Some chipsets need to unmask the LVTPC in a particular spot
1689 * inside the nmi handler. As a result, the unmasking was pushed
1690 * into all the nmi handlers.
1692 * This generic handler doesn't seem to have any issues where the
1693 * unmasking occurs so it was left at the top.
1695 apic_write(APIC_LVTPC, APIC_DM_NMI);
1697 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1698 if (!test_bit(idx, cpuc->active_mask))
1701 event = cpuc->events[idx];
1703 val = x86_perf_event_update(event);
1704 if (val & (1ULL << (x86_pmu.cntval_bits - 1)))
1712 if (!x86_perf_event_set_period(event))
1715 perf_sample_data_init(&data, 0, event->hw.last_period);
1717 if (has_branch_stack(event))
1718 data.br_stack = &cpuc->lbr_stack;
1720 if (perf_event_overflow(event, &data, regs))
1721 x86_pmu_stop(event, 0);
1725 inc_irq_stat(apic_perf_irqs);
1730 void perf_events_lapic_init(void)
1732 if (!x86_pmu.apic || !x86_pmu_initialized())
1736 * Always use NMI for PMU
1738 apic_write(APIC_LVTPC, APIC_DM_NMI);
1742 perf_event_nmi_handler(unsigned int cmd, struct pt_regs *regs)
1749 * All PMUs/events that share this PMI handler should make sure to
1750 * increment active_events for their events.
1752 if (!atomic_read(&active_events))
1755 start_clock = sched_clock();
1756 ret = static_call(x86_pmu_handle_irq)(regs);
1757 finish_clock = sched_clock();
1759 perf_sample_event_took(finish_clock - start_clock);
1763 NOKPROBE_SYMBOL(perf_event_nmi_handler);
1765 struct event_constraint emptyconstraint;
1766 struct event_constraint unconstrained;
1768 static int x86_pmu_prepare_cpu(unsigned int cpu)
1770 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1773 for (i = 0 ; i < X86_PERF_KFREE_MAX; i++)
1774 cpuc->kfree_on_online[i] = NULL;
1775 if (x86_pmu.cpu_prepare)
1776 return x86_pmu.cpu_prepare(cpu);
1780 static int x86_pmu_dead_cpu(unsigned int cpu)
1782 if (x86_pmu.cpu_dead)
1783 x86_pmu.cpu_dead(cpu);
1787 static int x86_pmu_online_cpu(unsigned int cpu)
1789 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1792 for (i = 0 ; i < X86_PERF_KFREE_MAX; i++) {
1793 kfree(cpuc->kfree_on_online[i]);
1794 cpuc->kfree_on_online[i] = NULL;
1799 static int x86_pmu_starting_cpu(unsigned int cpu)
1801 if (x86_pmu.cpu_starting)
1802 x86_pmu.cpu_starting(cpu);
1806 static int x86_pmu_dying_cpu(unsigned int cpu)
1808 if (x86_pmu.cpu_dying)
1809 x86_pmu.cpu_dying(cpu);
1813 static void __init pmu_check_apic(void)
1815 if (boot_cpu_has(X86_FEATURE_APIC))
1819 pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1820 pr_info("no hardware sampling interrupt available.\n");
1823 * If we have a PMU initialized but no APIC
1824 * interrupts, we cannot sample hardware
1825 * events (user-space has to fall back and
1826 * sample via a hrtimer based software event):
1828 pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
1832 static struct attribute_group x86_pmu_format_group __ro_after_init = {
1837 ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr, char *page)
1839 struct perf_pmu_events_attr *pmu_attr =
1840 container_of(attr, struct perf_pmu_events_attr, attr);
1843 if (pmu_attr->id < x86_pmu.max_events)
1844 config = x86_pmu.event_map(pmu_attr->id);
1846 /* string trumps id */
1847 if (pmu_attr->event_str)
1848 return sprintf(page, "%s\n", pmu_attr->event_str);
1850 return x86_pmu.events_sysfs_show(page, config);
1852 EXPORT_SYMBOL_GPL(events_sysfs_show);
1854 ssize_t events_ht_sysfs_show(struct device *dev, struct device_attribute *attr,
1857 struct perf_pmu_events_ht_attr *pmu_attr =
1858 container_of(attr, struct perf_pmu_events_ht_attr, attr);
1861 * Report conditional events depending on Hyper-Threading.
1863 * This is overly conservative as usually the HT special
1864 * handling is not needed if the other CPU thread is idle.
1866 * Note this does not (and cannot) handle the case when thread
1867 * siblings are invisible, for example with virtualization
1868 * if they are owned by some other guest. The user tool
1869 * has to re-read when a thread sibling gets onlined later.
1871 return sprintf(page, "%s",
1872 topology_max_smt_threads() > 1 ?
1873 pmu_attr->event_str_ht :
1874 pmu_attr->event_str_noht);
1877 ssize_t events_hybrid_sysfs_show(struct device *dev,
1878 struct device_attribute *attr,
1881 struct perf_pmu_events_hybrid_attr *pmu_attr =
1882 container_of(attr, struct perf_pmu_events_hybrid_attr, attr);
1883 struct x86_hybrid_pmu *pmu;
1884 const char *str, *next_str;
1887 if (hweight64(pmu_attr->pmu_type) == 1)
1888 return sprintf(page, "%s", pmu_attr->event_str);
1891 * Hybrid PMUs may support the same event name, but with different
1892 * event encoding, e.g., the mem-loads event on an Atom PMU has
1893 * different event encoding from a Core PMU.
1895 * The event_str includes all event encodings. Each event encoding
1896 * is divided by ";". The order of the event encodings must follow
1897 * the order of the hybrid PMU index.
1899 pmu = container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu);
1901 str = pmu_attr->event_str;
1902 for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) {
1903 if (!(x86_pmu.hybrid_pmu[i].cpu_type & pmu_attr->pmu_type))
1905 if (x86_pmu.hybrid_pmu[i].cpu_type & pmu->cpu_type) {
1906 next_str = strchr(str, ';');
1908 return snprintf(page, next_str - str + 1, "%s", str);
1910 return sprintf(page, "%s", str);
1912 str = strchr(str, ';');
1918 EXPORT_SYMBOL_GPL(events_hybrid_sysfs_show);
1920 EVENT_ATTR(cpu-cycles, CPU_CYCLES );
1921 EVENT_ATTR(instructions, INSTRUCTIONS );
1922 EVENT_ATTR(cache-references, CACHE_REFERENCES );
1923 EVENT_ATTR(cache-misses, CACHE_MISSES );
1924 EVENT_ATTR(branch-instructions, BRANCH_INSTRUCTIONS );
1925 EVENT_ATTR(branch-misses, BRANCH_MISSES );
1926 EVENT_ATTR(bus-cycles, BUS_CYCLES );
1927 EVENT_ATTR(stalled-cycles-frontend, STALLED_CYCLES_FRONTEND );
1928 EVENT_ATTR(stalled-cycles-backend, STALLED_CYCLES_BACKEND );
1929 EVENT_ATTR(ref-cycles, REF_CPU_CYCLES );
1931 static struct attribute *empty_attrs;
1933 static struct attribute *events_attr[] = {
1934 EVENT_PTR(CPU_CYCLES),
1935 EVENT_PTR(INSTRUCTIONS),
1936 EVENT_PTR(CACHE_REFERENCES),
1937 EVENT_PTR(CACHE_MISSES),
1938 EVENT_PTR(BRANCH_INSTRUCTIONS),
1939 EVENT_PTR(BRANCH_MISSES),
1940 EVENT_PTR(BUS_CYCLES),
1941 EVENT_PTR(STALLED_CYCLES_FRONTEND),
1942 EVENT_PTR(STALLED_CYCLES_BACKEND),
1943 EVENT_PTR(REF_CPU_CYCLES),
1948 * Remove all undefined events (x86_pmu.event_map(id) == 0)
1949 * out of events_attr attributes.
1952 is_visible(struct kobject *kobj, struct attribute *attr, int idx)
1954 struct perf_pmu_events_attr *pmu_attr;
1956 if (idx >= x86_pmu.max_events)
1959 pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr.attr);
1961 return pmu_attr->event_str || x86_pmu.event_map(idx) ? attr->mode : 0;
1964 static struct attribute_group x86_pmu_events_group __ro_after_init = {
1966 .attrs = events_attr,
1967 .is_visible = is_visible,
1970 ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event)
1972 u64 umask = (config & ARCH_PERFMON_EVENTSEL_UMASK) >> 8;
1973 u64 cmask = (config & ARCH_PERFMON_EVENTSEL_CMASK) >> 24;
1974 bool edge = (config & ARCH_PERFMON_EVENTSEL_EDGE);
1975 bool pc = (config & ARCH_PERFMON_EVENTSEL_PIN_CONTROL);
1976 bool any = (config & ARCH_PERFMON_EVENTSEL_ANY);
1977 bool inv = (config & ARCH_PERFMON_EVENTSEL_INV);
1981 * We have whole page size to spend and just little data
1982 * to write, so we can safely use sprintf.
1984 ret = sprintf(page, "event=0x%02llx", event);
1987 ret += sprintf(page + ret, ",umask=0x%02llx", umask);
1990 ret += sprintf(page + ret, ",edge");
1993 ret += sprintf(page + ret, ",pc");
1996 ret += sprintf(page + ret, ",any");
1999 ret += sprintf(page + ret, ",inv");
2002 ret += sprintf(page + ret, ",cmask=0x%02llx", cmask);
2004 ret += sprintf(page + ret, "\n");
2009 static struct attribute_group x86_pmu_attr_group;
2010 static struct attribute_group x86_pmu_caps_group;
2012 static void x86_pmu_static_call_update(void)
2014 static_call_update(x86_pmu_handle_irq, x86_pmu.handle_irq);
2015 static_call_update(x86_pmu_disable_all, x86_pmu.disable_all);
2016 static_call_update(x86_pmu_enable_all, x86_pmu.enable_all);
2017 static_call_update(x86_pmu_enable, x86_pmu.enable);
2018 static_call_update(x86_pmu_disable, x86_pmu.disable);
2020 static_call_update(x86_pmu_assign, x86_pmu.assign);
2022 static_call_update(x86_pmu_add, x86_pmu.add);
2023 static_call_update(x86_pmu_del, x86_pmu.del);
2024 static_call_update(x86_pmu_read, x86_pmu.read);
2026 static_call_update(x86_pmu_schedule_events, x86_pmu.schedule_events);
2027 static_call_update(x86_pmu_get_event_constraints, x86_pmu.get_event_constraints);
2028 static_call_update(x86_pmu_put_event_constraints, x86_pmu.put_event_constraints);
2030 static_call_update(x86_pmu_start_scheduling, x86_pmu.start_scheduling);
2031 static_call_update(x86_pmu_commit_scheduling, x86_pmu.commit_scheduling);
2032 static_call_update(x86_pmu_stop_scheduling, x86_pmu.stop_scheduling);
2034 static_call_update(x86_pmu_sched_task, x86_pmu.sched_task);
2035 static_call_update(x86_pmu_swap_task_ctx, x86_pmu.swap_task_ctx);
2037 static_call_update(x86_pmu_drain_pebs, x86_pmu.drain_pebs);
2038 static_call_update(x86_pmu_pebs_aliases, x86_pmu.pebs_aliases);
2040 static_call_update(x86_pmu_guest_get_msrs, x86_pmu.guest_get_msrs);
2043 static void _x86_pmu_read(struct perf_event *event)
2045 x86_perf_event_update(event);
2048 void x86_pmu_show_pmu_cap(int num_counters, int num_counters_fixed,
2051 pr_info("... version: %d\n", x86_pmu.version);
2052 pr_info("... bit width: %d\n", x86_pmu.cntval_bits);
2053 pr_info("... generic registers: %d\n", num_counters);
2054 pr_info("... value mask: %016Lx\n", x86_pmu.cntval_mask);
2055 pr_info("... max period: %016Lx\n", x86_pmu.max_period);
2056 pr_info("... fixed-purpose events: %lu\n",
2057 hweight64((((1ULL << num_counters_fixed) - 1)
2058 << INTEL_PMC_IDX_FIXED) & intel_ctrl));
2059 pr_info("... event mask: %016Lx\n", intel_ctrl);
2063 * The generic code is not hybrid friendly. The hybrid_pmu->pmu
2064 * of the first registered PMU is unconditionally assigned to
2065 * each possible cpuctx->ctx.pmu.
2066 * Update the correct hybrid PMU to the cpuctx->ctx.pmu.
2068 void x86_pmu_update_cpu_context(struct pmu *pmu, int cpu)
2070 struct perf_cpu_context *cpuctx;
2072 if (!pmu->pmu_cpu_context)
2075 cpuctx = per_cpu_ptr(pmu->pmu_cpu_context, cpu);
2076 cpuctx->ctx.pmu = pmu;
2079 static int __init init_hw_perf_events(void)
2081 struct x86_pmu_quirk *quirk;
2084 pr_info("Performance Events: ");
2086 switch (boot_cpu_data.x86_vendor) {
2087 case X86_VENDOR_INTEL:
2088 err = intel_pmu_init();
2090 case X86_VENDOR_AMD:
2091 err = amd_pmu_init();
2093 case X86_VENDOR_HYGON:
2094 err = amd_pmu_init();
2095 x86_pmu.name = "HYGON";
2097 case X86_VENDOR_ZHAOXIN:
2098 case X86_VENDOR_CENTAUR:
2099 err = zhaoxin_pmu_init();
2105 pr_cont("no PMU driver, software events only.\n");
2111 /* sanity check that the hardware exists or is emulated */
2112 if (!check_hw_exists(&pmu, x86_pmu.num_counters, x86_pmu.num_counters_fixed))
2115 pr_cont("%s PMU driver.\n", x86_pmu.name);
2117 x86_pmu.attr_rdpmc = 1; /* enable userspace RDPMC usage by default */
2119 for (quirk = x86_pmu.quirks; quirk; quirk = quirk->next)
2122 if (!x86_pmu.intel_ctrl)
2123 x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
2125 perf_events_lapic_init();
2126 register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI");
2128 unconstrained = (struct event_constraint)
2129 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
2130 0, x86_pmu.num_counters, 0, 0);
2132 x86_pmu_format_group.attrs = x86_pmu.format_attrs;
2134 if (!x86_pmu.events_sysfs_show)
2135 x86_pmu_events_group.attrs = &empty_attrs;
2137 pmu.attr_update = x86_pmu.attr_update;
2140 x86_pmu_show_pmu_cap(x86_pmu.num_counters,
2141 x86_pmu.num_counters_fixed,
2142 x86_pmu.intel_ctrl);
2146 x86_pmu.read = _x86_pmu_read;
2148 if (!x86_pmu.guest_get_msrs)
2149 x86_pmu.guest_get_msrs = (void *)&__static_call_return0;
2151 x86_pmu_static_call_update();
2154 * Install callbacks. Core will call them for each online
2157 err = cpuhp_setup_state(CPUHP_PERF_X86_PREPARE, "perf/x86:prepare",
2158 x86_pmu_prepare_cpu, x86_pmu_dead_cpu);
2162 err = cpuhp_setup_state(CPUHP_AP_PERF_X86_STARTING,
2163 "perf/x86:starting", x86_pmu_starting_cpu,
2168 err = cpuhp_setup_state(CPUHP_AP_PERF_X86_ONLINE, "perf/x86:online",
2169 x86_pmu_online_cpu, NULL);
2174 err = perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
2178 u8 cpu_type = get_this_hybrid_cpu_type();
2179 struct x86_hybrid_pmu *hybrid_pmu;
2182 if (!cpu_type && x86_pmu.get_hybrid_cpu_type)
2183 cpu_type = x86_pmu.get_hybrid_cpu_type();
2185 for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) {
2186 hybrid_pmu = &x86_pmu.hybrid_pmu[i];
2188 hybrid_pmu->pmu = pmu;
2189 hybrid_pmu->pmu.type = -1;
2190 hybrid_pmu->pmu.attr_update = x86_pmu.attr_update;
2191 hybrid_pmu->pmu.capabilities |= PERF_PMU_CAP_HETEROGENEOUS_CPUS;
2192 hybrid_pmu->pmu.capabilities |= PERF_PMU_CAP_EXTENDED_HW_TYPE;
2194 err = perf_pmu_register(&hybrid_pmu->pmu, hybrid_pmu->name,
2195 (hybrid_pmu->cpu_type == hybrid_big) ? PERF_TYPE_RAW : -1);
2199 if (cpu_type == hybrid_pmu->cpu_type)
2200 x86_pmu_update_cpu_context(&hybrid_pmu->pmu, raw_smp_processor_id());
2203 if (i < x86_pmu.num_hybrid_pmus) {
2204 for (j = 0; j < i; j++)
2205 perf_pmu_unregister(&x86_pmu.hybrid_pmu[j].pmu);
2206 pr_warn("Failed to register hybrid PMUs\n");
2207 kfree(x86_pmu.hybrid_pmu);
2208 x86_pmu.hybrid_pmu = NULL;
2209 x86_pmu.num_hybrid_pmus = 0;
2217 cpuhp_remove_state(CPUHP_AP_PERF_X86_ONLINE);
2219 cpuhp_remove_state(CPUHP_AP_PERF_X86_STARTING);
2221 cpuhp_remove_state(CPUHP_PERF_X86_PREPARE);
2224 early_initcall(init_hw_perf_events);
2226 static void x86_pmu_read(struct perf_event *event)
2228 static_call(x86_pmu_read)(event);
2232 * Start group events scheduling transaction
2233 * Set the flag to make pmu::enable() not perform the
2234 * schedulability test, it will be performed at commit time
2236 * We only support PERF_PMU_TXN_ADD transactions. Save the
2237 * transaction flags but otherwise ignore non-PERF_PMU_TXN_ADD
2240 static void x86_pmu_start_txn(struct pmu *pmu, unsigned int txn_flags)
2242 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2244 WARN_ON_ONCE(cpuc->txn_flags); /* txn already in flight */
2246 cpuc->txn_flags = txn_flags;
2247 if (txn_flags & ~PERF_PMU_TXN_ADD)
2250 perf_pmu_disable(pmu);
2251 __this_cpu_write(cpu_hw_events.n_txn, 0);
2252 __this_cpu_write(cpu_hw_events.n_txn_pair, 0);
2253 __this_cpu_write(cpu_hw_events.n_txn_metric, 0);
2257 * Stop group events scheduling transaction
2258 * Clear the flag and pmu::enable() will perform the
2259 * schedulability test.
2261 static void x86_pmu_cancel_txn(struct pmu *pmu)
2263 unsigned int txn_flags;
2264 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2266 WARN_ON_ONCE(!cpuc->txn_flags); /* no txn in flight */
2268 txn_flags = cpuc->txn_flags;
2269 cpuc->txn_flags = 0;
2270 if (txn_flags & ~PERF_PMU_TXN_ADD)
2274 * Truncate collected array by the number of events added in this
2275 * transaction. See x86_pmu_add() and x86_pmu_*_txn().
2277 __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn));
2278 __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn));
2279 __this_cpu_sub(cpu_hw_events.n_pair, __this_cpu_read(cpu_hw_events.n_txn_pair));
2280 __this_cpu_sub(cpu_hw_events.n_metric, __this_cpu_read(cpu_hw_events.n_txn_metric));
2281 perf_pmu_enable(pmu);
2285 * Commit group events scheduling transaction
2286 * Perform the group schedulability test as a whole
2287 * Return 0 if success
2289 * Does not cancel the transaction on failure; expects the caller to do this.
2291 static int x86_pmu_commit_txn(struct pmu *pmu)
2293 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2294 int assign[X86_PMC_IDX_MAX];
2297 WARN_ON_ONCE(!cpuc->txn_flags); /* no txn in flight */
2299 if (cpuc->txn_flags & ~PERF_PMU_TXN_ADD) {
2300 cpuc->txn_flags = 0;
2306 if (!x86_pmu_initialized())
2309 ret = static_call(x86_pmu_schedule_events)(cpuc, n, assign);
2314 * copy new assignment, now we know it is possible
2315 * will be used by hw_perf_enable()
2317 memcpy(cpuc->assign, assign, n*sizeof(int));
2319 cpuc->txn_flags = 0;
2320 perf_pmu_enable(pmu);
2324 * a fake_cpuc is used to validate event groups. Due to
2325 * the extra reg logic, we need to also allocate a fake
2326 * per_core and per_cpu structure. Otherwise, group events
2327 * using extra reg may conflict without the kernel being
2328 * able to catch this when the last event gets added to
2331 static void free_fake_cpuc(struct cpu_hw_events *cpuc)
2333 intel_cpuc_finish(cpuc);
2337 static struct cpu_hw_events *allocate_fake_cpuc(struct pmu *event_pmu)
2339 struct cpu_hw_events *cpuc;
2342 cpuc = kzalloc(sizeof(*cpuc), GFP_KERNEL);
2344 return ERR_PTR(-ENOMEM);
2348 struct x86_hybrid_pmu *h_pmu;
2350 h_pmu = hybrid_pmu(event_pmu);
2351 if (cpumask_empty(&h_pmu->supported_cpus))
2353 cpu = cpumask_first(&h_pmu->supported_cpus);
2355 cpu = raw_smp_processor_id();
2356 cpuc->pmu = event_pmu;
2358 if (intel_cpuc_prepare(cpuc, cpu))
2363 free_fake_cpuc(cpuc);
2364 return ERR_PTR(-ENOMEM);
2368 * validate that we can schedule this event
2370 static int validate_event(struct perf_event *event)
2372 struct cpu_hw_events *fake_cpuc;
2373 struct event_constraint *c;
2376 fake_cpuc = allocate_fake_cpuc(event->pmu);
2377 if (IS_ERR(fake_cpuc))
2378 return PTR_ERR(fake_cpuc);
2380 c = x86_pmu.get_event_constraints(fake_cpuc, 0, event);
2382 if (!c || !c->weight)
2385 if (x86_pmu.put_event_constraints)
2386 x86_pmu.put_event_constraints(fake_cpuc, event);
2388 free_fake_cpuc(fake_cpuc);
2394 * validate a single event group
2396 * validation include:
2397 * - check events are compatible which each other
2398 * - events do not compete for the same counter
2399 * - number of events <= number of counters
2401 * validation ensures the group can be loaded onto the
2402 * PMU if it was the only group available.
2404 static int validate_group(struct perf_event *event)
2406 struct perf_event *leader = event->group_leader;
2407 struct cpu_hw_events *fake_cpuc;
2408 int ret = -EINVAL, n;
2411 * Reject events from different hybrid PMUs.
2414 struct perf_event *sibling;
2415 struct pmu *pmu = NULL;
2417 if (is_x86_event(leader))
2420 for_each_sibling_event(sibling, leader) {
2421 if (!is_x86_event(sibling))
2425 else if (pmu != sibling->pmu)
2430 fake_cpuc = allocate_fake_cpuc(event->pmu);
2431 if (IS_ERR(fake_cpuc))
2432 return PTR_ERR(fake_cpuc);
2434 * the event is not yet connected with its
2435 * siblings therefore we must first collect
2436 * existing siblings, then add the new event
2437 * before we can simulate the scheduling
2439 n = collect_events(fake_cpuc, leader, true);
2443 fake_cpuc->n_events = n;
2444 n = collect_events(fake_cpuc, event, false);
2448 fake_cpuc->n_events = 0;
2449 ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
2452 free_fake_cpuc(fake_cpuc);
2456 static int x86_pmu_event_init(struct perf_event *event)
2458 struct x86_hybrid_pmu *pmu = NULL;
2461 if ((event->attr.type != event->pmu->type) &&
2462 (event->attr.type != PERF_TYPE_HARDWARE) &&
2463 (event->attr.type != PERF_TYPE_HW_CACHE))
2466 if (is_hybrid() && (event->cpu != -1)) {
2467 pmu = hybrid_pmu(event->pmu);
2468 if (!cpumask_test_cpu(event->cpu, &pmu->supported_cpus))
2472 err = __x86_pmu_event_init(event);
2474 if (event->group_leader != event)
2475 err = validate_group(event);
2477 err = validate_event(event);
2481 event->destroy(event);
2482 event->destroy = NULL;
2485 if (READ_ONCE(x86_pmu.attr_rdpmc) &&
2486 !(event->hw.flags & PERF_X86_EVENT_LARGE_PEBS))
2487 event->hw.flags |= PERF_EVENT_FLAG_USER_READ_CNT;
2492 void perf_clear_dirty_counters(void)
2494 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2497 /* Don't need to clear the assigned counter. */
2498 for (i = 0; i < cpuc->n_events; i++)
2499 __clear_bit(cpuc->assign[i], cpuc->dirty);
2501 if (bitmap_empty(cpuc->dirty, X86_PMC_IDX_MAX))
2504 for_each_set_bit(i, cpuc->dirty, X86_PMC_IDX_MAX) {
2505 if (i >= INTEL_PMC_IDX_FIXED) {
2506 /* Metrics and fake events don't have corresponding HW counters. */
2507 if ((i - INTEL_PMC_IDX_FIXED) >= hybrid(cpuc->pmu, num_counters_fixed))
2510 wrmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + (i - INTEL_PMC_IDX_FIXED), 0);
2512 wrmsrl(x86_pmu_event_addr(i), 0);
2516 bitmap_zero(cpuc->dirty, X86_PMC_IDX_MAX);
2519 static void x86_pmu_event_mapped(struct perf_event *event, struct mm_struct *mm)
2521 if (!(event->hw.flags & PERF_EVENT_FLAG_USER_READ_CNT))
2525 * This function relies on not being called concurrently in two
2526 * tasks in the same mm. Otherwise one task could observe
2527 * perf_rdpmc_allowed > 1 and return all the way back to
2528 * userspace with CR4.PCE clear while another task is still
2529 * doing on_each_cpu_mask() to propagate CR4.PCE.
2531 * For now, this can't happen because all callers hold mmap_lock
2532 * for write. If this changes, we'll need a different solution.
2534 mmap_assert_write_locked(mm);
2536 if (atomic_inc_return(&mm->context.perf_rdpmc_allowed) == 1)
2537 on_each_cpu_mask(mm_cpumask(mm), cr4_update_pce, NULL, 1);
2540 static void x86_pmu_event_unmapped(struct perf_event *event, struct mm_struct *mm)
2542 if (!(event->hw.flags & PERF_EVENT_FLAG_USER_READ_CNT))
2545 if (atomic_dec_and_test(&mm->context.perf_rdpmc_allowed))
2546 on_each_cpu_mask(mm_cpumask(mm), cr4_update_pce, NULL, 1);
2549 static int x86_pmu_event_idx(struct perf_event *event)
2551 struct hw_perf_event *hwc = &event->hw;
2553 if (!(hwc->flags & PERF_EVENT_FLAG_USER_READ_CNT))
2556 if (is_metric_idx(hwc->idx))
2557 return INTEL_PMC_FIXED_RDPMC_METRICS + 1;
2559 return hwc->event_base_rdpmc + 1;
2562 static ssize_t get_attr_rdpmc(struct device *cdev,
2563 struct device_attribute *attr,
2566 return snprintf(buf, 40, "%d\n", x86_pmu.attr_rdpmc);
2569 static ssize_t set_attr_rdpmc(struct device *cdev,
2570 struct device_attribute *attr,
2571 const char *buf, size_t count)
2576 ret = kstrtoul(buf, 0, &val);
2583 if (x86_pmu.attr_rdpmc_broken)
2586 if (val != x86_pmu.attr_rdpmc) {
2588 * Changing into or out of never available or always available,
2589 * aka perf-event-bypassing mode. This path is extremely slow,
2590 * but only root can trigger it, so it's okay.
2593 static_branch_inc(&rdpmc_never_available_key);
2594 else if (x86_pmu.attr_rdpmc == 0)
2595 static_branch_dec(&rdpmc_never_available_key);
2598 static_branch_inc(&rdpmc_always_available_key);
2599 else if (x86_pmu.attr_rdpmc == 2)
2600 static_branch_dec(&rdpmc_always_available_key);
2602 on_each_cpu(cr4_update_pce, NULL, 1);
2603 x86_pmu.attr_rdpmc = val;
2609 static DEVICE_ATTR(rdpmc, S_IRUSR | S_IWUSR, get_attr_rdpmc, set_attr_rdpmc);
2611 static struct attribute *x86_pmu_attrs[] = {
2612 &dev_attr_rdpmc.attr,
2616 static struct attribute_group x86_pmu_attr_group __ro_after_init = {
2617 .attrs = x86_pmu_attrs,
2620 static ssize_t max_precise_show(struct device *cdev,
2621 struct device_attribute *attr,
2624 return snprintf(buf, PAGE_SIZE, "%d\n", x86_pmu_max_precise());
2627 static DEVICE_ATTR_RO(max_precise);
2629 static struct attribute *x86_pmu_caps_attrs[] = {
2630 &dev_attr_max_precise.attr,
2634 static struct attribute_group x86_pmu_caps_group __ro_after_init = {
2636 .attrs = x86_pmu_caps_attrs,
2639 static const struct attribute_group *x86_pmu_attr_groups[] = {
2640 &x86_pmu_attr_group,
2641 &x86_pmu_format_group,
2642 &x86_pmu_events_group,
2643 &x86_pmu_caps_group,
2647 static void x86_pmu_sched_task(struct perf_event_context *ctx, bool sched_in)
2649 static_call_cond(x86_pmu_sched_task)(ctx, sched_in);
2652 static void x86_pmu_swap_task_ctx(struct perf_event_context *prev,
2653 struct perf_event_context *next)
2655 static_call_cond(x86_pmu_swap_task_ctx)(prev, next);
2658 void perf_check_microcode(void)
2660 if (x86_pmu.check_microcode)
2661 x86_pmu.check_microcode();
2664 static int x86_pmu_check_period(struct perf_event *event, u64 value)
2666 if (x86_pmu.check_period && x86_pmu.check_period(event, value))
2669 if (value && x86_pmu.limit_period) {
2670 if (x86_pmu.limit_period(event, value) > value)
2677 static int x86_pmu_aux_output_match(struct perf_event *event)
2679 if (!(pmu.capabilities & PERF_PMU_CAP_AUX_OUTPUT))
2682 if (x86_pmu.aux_output_match)
2683 return x86_pmu.aux_output_match(event);
2688 static int x86_pmu_filter_match(struct perf_event *event)
2690 if (x86_pmu.filter_match)
2691 return x86_pmu.filter_match(event);
2696 static struct pmu pmu = {
2697 .pmu_enable = x86_pmu_enable,
2698 .pmu_disable = x86_pmu_disable,
2700 .attr_groups = x86_pmu_attr_groups,
2702 .event_init = x86_pmu_event_init,
2704 .event_mapped = x86_pmu_event_mapped,
2705 .event_unmapped = x86_pmu_event_unmapped,
2709 .start = x86_pmu_start,
2710 .stop = x86_pmu_stop,
2711 .read = x86_pmu_read,
2713 .start_txn = x86_pmu_start_txn,
2714 .cancel_txn = x86_pmu_cancel_txn,
2715 .commit_txn = x86_pmu_commit_txn,
2717 .event_idx = x86_pmu_event_idx,
2718 .sched_task = x86_pmu_sched_task,
2719 .swap_task_ctx = x86_pmu_swap_task_ctx,
2720 .check_period = x86_pmu_check_period,
2722 .aux_output_match = x86_pmu_aux_output_match,
2724 .filter_match = x86_pmu_filter_match,
2727 void arch_perf_update_userpage(struct perf_event *event,
2728 struct perf_event_mmap_page *userpg, u64 now)
2730 struct cyc2ns_data data;
2733 userpg->cap_user_time = 0;
2734 userpg->cap_user_time_zero = 0;
2735 userpg->cap_user_rdpmc =
2736 !!(event->hw.flags & PERF_EVENT_FLAG_USER_READ_CNT);
2737 userpg->pmc_width = x86_pmu.cntval_bits;
2739 if (!using_native_sched_clock() || !sched_clock_stable())
2742 cyc2ns_read_begin(&data);
2744 offset = data.cyc2ns_offset + __sched_clock_offset;
2747 * Internal timekeeping for enabled/running/stopped times
2748 * is always in the local_clock domain.
2750 userpg->cap_user_time = 1;
2751 userpg->time_mult = data.cyc2ns_mul;
2752 userpg->time_shift = data.cyc2ns_shift;
2753 userpg->time_offset = offset - now;
2756 * cap_user_time_zero doesn't make sense when we're using a different
2757 * time base for the records.
2759 if (!event->attr.use_clockid) {
2760 userpg->cap_user_time_zero = 1;
2761 userpg->time_zero = offset;
2768 * Determine whether the regs were taken from an irq/exception handler rather
2769 * than from perf_arch_fetch_caller_regs().
2771 static bool perf_hw_regs(struct pt_regs *regs)
2773 return regs->flags & X86_EFLAGS_FIXED;
2777 perf_callchain_kernel(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs)
2779 struct unwind_state state;
2782 if (perf_guest_state()) {
2783 /* TODO: We don't support guest os callchain now */
2787 if (perf_callchain_store(entry, regs->ip))
2790 if (perf_hw_regs(regs))
2791 unwind_start(&state, current, regs, NULL);
2793 unwind_start(&state, current, NULL, (void *)regs->sp);
2795 for (; !unwind_done(&state); unwind_next_frame(&state)) {
2796 addr = unwind_get_return_address(&state);
2797 if (!addr || perf_callchain_store(entry, addr))
2803 valid_user_frame(const void __user *fp, unsigned long size)
2805 return __access_ok(fp, size);
2808 static unsigned long get_segment_base(unsigned int segment)
2810 struct desc_struct *desc;
2811 unsigned int idx = segment >> 3;
2813 if ((segment & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2814 #ifdef CONFIG_MODIFY_LDT_SYSCALL
2815 struct ldt_struct *ldt;
2817 /* IRQs are off, so this synchronizes with smp_store_release */
2818 ldt = READ_ONCE(current->active_mm->context.ldt);
2819 if (!ldt || idx >= ldt->nr_entries)
2822 desc = &ldt->entries[idx];
2827 if (idx >= GDT_ENTRIES)
2830 desc = raw_cpu_ptr(gdt_page.gdt) + idx;
2833 return get_desc_base(desc);
2836 #ifdef CONFIG_IA32_EMULATION
2838 #include <linux/compat.h>
2841 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry_ctx *entry)
2843 /* 32-bit process in 64-bit kernel. */
2844 unsigned long ss_base, cs_base;
2845 struct stack_frame_ia32 frame;
2846 const struct stack_frame_ia32 __user *fp;
2848 if (user_64bit_mode(regs))
2851 cs_base = get_segment_base(regs->cs);
2852 ss_base = get_segment_base(regs->ss);
2854 fp = compat_ptr(ss_base + regs->bp);
2855 pagefault_disable();
2856 while (entry->nr < entry->max_stack) {
2857 if (!valid_user_frame(fp, sizeof(frame)))
2860 if (__get_user(frame.next_frame, &fp->next_frame))
2862 if (__get_user(frame.return_address, &fp->return_address))
2865 perf_callchain_store(entry, cs_base + frame.return_address);
2866 fp = compat_ptr(ss_base + frame.next_frame);
2873 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry_ctx *entry)
2880 perf_callchain_user(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs)
2882 struct stack_frame frame;
2883 const struct stack_frame __user *fp;
2885 if (perf_guest_state()) {
2886 /* TODO: We don't support guest os callchain now */
2891 * We don't know what to do with VM86 stacks.. ignore them for now.
2893 if (regs->flags & (X86_VM_MASK | PERF_EFLAGS_VM))
2896 fp = (void __user *)regs->bp;
2898 perf_callchain_store(entry, regs->ip);
2900 if (!nmi_uaccess_okay())
2903 if (perf_callchain_user32(regs, entry))
2906 pagefault_disable();
2907 while (entry->nr < entry->max_stack) {
2908 if (!valid_user_frame(fp, sizeof(frame)))
2911 if (__get_user(frame.next_frame, &fp->next_frame))
2913 if (__get_user(frame.return_address, &fp->return_address))
2916 perf_callchain_store(entry, frame.return_address);
2917 fp = (void __user *)frame.next_frame;
2923 * Deal with code segment offsets for the various execution modes:
2925 * VM86 - the good olde 16 bit days, where the linear address is
2926 * 20 bits and we use regs->ip + 0x10 * regs->cs.
2928 * IA32 - Where we need to look at GDT/LDT segment descriptor tables
2929 * to figure out what the 32bit base address is.
2931 * X32 - has TIF_X32 set, but is running in x86_64
2933 * X86_64 - CS,DS,SS,ES are all zero based.
2935 static unsigned long code_segment_base(struct pt_regs *regs)
2938 * For IA32 we look at the GDT/LDT segment base to convert the
2939 * effective IP to a linear address.
2942 #ifdef CONFIG_X86_32
2944 * If we are in VM86 mode, add the segment offset to convert to a
2947 if (regs->flags & X86_VM_MASK)
2948 return 0x10 * regs->cs;
2950 if (user_mode(regs) && regs->cs != __USER_CS)
2951 return get_segment_base(regs->cs);
2953 if (user_mode(regs) && !user_64bit_mode(regs) &&
2954 regs->cs != __USER32_CS)
2955 return get_segment_base(regs->cs);
2960 unsigned long perf_instruction_pointer(struct pt_regs *regs)
2962 if (perf_guest_state())
2963 return perf_guest_get_ip();
2965 return regs->ip + code_segment_base(regs);
2968 unsigned long perf_misc_flags(struct pt_regs *regs)
2970 unsigned int guest_state = perf_guest_state();
2974 if (guest_state & PERF_GUEST_USER)
2975 misc |= PERF_RECORD_MISC_GUEST_USER;
2977 misc |= PERF_RECORD_MISC_GUEST_KERNEL;
2979 if (user_mode(regs))
2980 misc |= PERF_RECORD_MISC_USER;
2982 misc |= PERF_RECORD_MISC_KERNEL;
2985 if (regs->flags & PERF_EFLAGS_EXACT)
2986 misc |= PERF_RECORD_MISC_EXACT_IP;
2991 void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
2993 cap->version = x86_pmu.version;
2995 * KVM doesn't support the hybrid PMU yet.
2996 * Return the common value in global x86_pmu,
2997 * which available for all cores.
2999 cap->num_counters_gp = x86_pmu.num_counters;
3000 cap->num_counters_fixed = x86_pmu.num_counters_fixed;
3001 cap->bit_width_gp = x86_pmu.cntval_bits;
3002 cap->bit_width_fixed = x86_pmu.cntval_bits;
3003 cap->events_mask = (unsigned int)x86_pmu.events_maskl;
3004 cap->events_mask_len = x86_pmu.events_mask_len;
3006 EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability);