2 * Performance events - AMD IBS
4 * Copyright (C) 2011 Advanced Micro Devices, Inc., Robert Richter
6 * For licencing details see kernel-base/COPYING
9 #include <linux/perf_event.h>
10 #include <linux/init.h>
11 #include <linux/export.h>
12 #include <linux/pci.h>
13 #include <linux/ptrace.h>
14 #include <linux/syscore_ops.h>
18 #include "../perf_event.h"
22 #if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_AMD)
24 #include <linux/kprobes.h>
25 #include <linux/hardirq.h>
29 #define IBS_FETCH_CONFIG_MASK (IBS_FETCH_RAND_EN | IBS_FETCH_MAX_CNT)
30 #define IBS_OP_CONFIG_MASK IBS_OP_MAX_CNT
36 * ENABLED; tracks the pmu::add(), pmu::del() state, when set the counter is taken
37 * and any further add()s must fail.
39 * STARTED/STOPPING/STOPPED; deal with pmu::start(), pmu::stop() state but are
40 * complicated by the fact that the IBS hardware can send late NMIs (ie. after
41 * we've cleared the EN bit).
43 * In order to consume these late NMIs we have the STOPPED state, any NMI that
44 * happens after we've cleared the EN state will clear this bit and report the
45 * NMI handled (this is fundamentally racy in the face or multiple NMI sources,
46 * someone else can consume our BIT and our NMI will go unhandled).
48 * And since we cannot set/clear this separate bit together with the EN bit,
49 * there are races; if we cleared STARTED early, an NMI could land in
50 * between clearing STARTED and clearing the EN bit (in fact multiple NMIs
51 * could happen if the period is small enough), and consume our STOPPED bit
52 * and trigger streams of unhandled NMIs.
54 * If, however, we clear STARTED late, an NMI can hit between clearing the
55 * EN bit and clearing STARTED, still see STARTED set and process the event.
56 * If this event will have the VALID bit clear, we bail properly, but this
57 * is not a given. With VALID set we can end up calling pmu::stop() again
58 * (the throttle logic) and trigger the WARNs in there.
60 * So what we do is set STOPPING before clearing EN to avoid the pmu::stop()
61 * nesting, and clear STARTED late, so that we have a well defined state over
62 * the clearing of the EN bit.
64 * XXX: we could probably be using !atomic bitops for all this.
77 struct perf_event *event;
78 unsigned long state[BITS_TO_LONGS(IBS_MAX_STATES)];
89 unsigned long offset_mask[1];
91 unsigned int fetch_count_reset_broken : 1;
92 unsigned int fetch_ignore_if_zero_rip : 1;
93 struct cpu_perf_ibs __percpu *pcpu;
95 struct attribute **format_attrs;
96 struct attribute_group format_group;
97 const struct attribute_group *attr_groups[2];
99 u64 (*get_count)(u64 config);
102 struct perf_ibs_data {
105 u32 data[0]; /* data buffer starts here */
108 u64 regs[MSR_AMD64_IBS_REG_COUNT_MAX];
112 perf_event_set_period(struct hw_perf_event *hwc, u64 min, u64 max, u64 *hw_period)
114 s64 left = local64_read(&hwc->period_left);
115 s64 period = hwc->sample_period;
119 * If we are way outside a reasonable range then just skip forward:
121 if (unlikely(left <= -period)) {
123 local64_set(&hwc->period_left, left);
124 hwc->last_period = period;
128 if (unlikely(left < (s64)min)) {
130 local64_set(&hwc->period_left, left);
131 hwc->last_period = period;
136 * If the hw period that triggers the sw overflow is too short
137 * we might hit the irq handler. This biases the results.
138 * Thus we shorten the next-to-last period and set the last
139 * period to the max period.
149 *hw_period = (u64)left;
155 perf_event_try_update(struct perf_event *event, u64 new_raw_count, int width)
157 struct hw_perf_event *hwc = &event->hw;
158 int shift = 64 - width;
163 * Careful: an NMI might modify the previous event value.
165 * Our tactic to handle this is to first atomically read and
166 * exchange a new raw count - then add that new-prev delta
167 * count to the generic event atomically:
169 prev_raw_count = local64_read(&hwc->prev_count);
170 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
171 new_raw_count) != prev_raw_count)
175 * Now we have the new raw value and have updated the prev
176 * timestamp already. We can now calculate the elapsed delta
177 * (event-)time and add that to the generic event.
179 * Careful, not all hw sign-extends above the physical width
182 delta = (new_raw_count << shift) - (prev_raw_count << shift);
185 local64_add(delta, &event->count);
186 local64_sub(delta, &hwc->period_left);
191 static struct perf_ibs perf_ibs_fetch;
192 static struct perf_ibs perf_ibs_op;
194 static struct perf_ibs *get_ibs_pmu(int type)
196 if (perf_ibs_fetch.pmu.type == type)
197 return &perf_ibs_fetch;
198 if (perf_ibs_op.pmu.type == type)
204 * Use IBS for precise event sampling:
206 * perf record -a -e cpu-cycles:p ... # use ibs op counting cycle count
207 * perf record -a -e r076:p ... # same as -e cpu-cycles:p
208 * perf record -a -e r0C1:p ... # use ibs op counting micro-ops
210 * IbsOpCntCtl (bit 19) of IBS Execution Control Register (IbsOpCtl,
211 * MSRC001_1033) is used to select either cycle or micro-ops counting
214 * The rip of IBS samples has skid 0. Thus, IBS supports precise
215 * levels 1 and 2 and the PERF_EFLAGS_EXACT is set. In rare cases the
216 * rip is invalid when IBS was not able to record the rip correctly.
217 * We clear PERF_EFLAGS_EXACT and take the rip from pt_regs then.
220 static int perf_ibs_precise_event(struct perf_event *event, u64 *config)
222 switch (event->attr.precise_ip) {
232 switch (event->attr.type) {
233 case PERF_TYPE_HARDWARE:
234 switch (event->attr.config) {
235 case PERF_COUNT_HW_CPU_CYCLES:
241 switch (event->attr.config) {
246 *config = IBS_OP_CNT_CTL;
257 static const struct perf_event_attr ibs_notsupp = {
266 static int perf_ibs_init(struct perf_event *event)
268 struct hw_perf_event *hwc = &event->hw;
269 struct perf_ibs *perf_ibs;
273 perf_ibs = get_ibs_pmu(event->attr.type);
275 config = event->attr.config;
277 perf_ibs = &perf_ibs_op;
278 ret = perf_ibs_precise_event(event, &config);
283 if (event->pmu != &perf_ibs->pmu)
286 if (perf_flags(&event->attr) & perf_flags(&ibs_notsupp))
289 if (config & ~perf_ibs->config_mask)
292 if (hwc->sample_period) {
293 if (config & perf_ibs->cnt_mask)
294 /* raw max_cnt may not be set */
296 if (!event->attr.sample_freq && hwc->sample_period & 0x0f)
298 * lower 4 bits can not be set in ibs max cnt,
299 * but allowing it in case we adjust the
300 * sample period to set a frequency.
303 hwc->sample_period &= ~0x0FULL;
304 if (!hwc->sample_period)
305 hwc->sample_period = 0x10;
307 max_cnt = config & perf_ibs->cnt_mask;
308 config &= ~perf_ibs->cnt_mask;
309 event->attr.sample_period = max_cnt << 4;
310 hwc->sample_period = event->attr.sample_period;
313 if (!hwc->sample_period)
317 * If we modify hwc->sample_period, we also need to update
318 * hwc->last_period and hwc->period_left.
320 hwc->last_period = hwc->sample_period;
321 local64_set(&hwc->period_left, hwc->sample_period);
323 hwc->config_base = perf_ibs->msr;
324 hwc->config = config;
329 static int perf_ibs_set_period(struct perf_ibs *perf_ibs,
330 struct hw_perf_event *hwc, u64 *period)
334 /* ignore lower 4 bits in min count: */
335 overflow = perf_event_set_period(hwc, 1<<4, perf_ibs->max_period, period);
336 local64_set(&hwc->prev_count, 0);
341 static u64 get_ibs_fetch_count(u64 config)
343 return (config & IBS_FETCH_CNT) >> 12;
346 static u64 get_ibs_op_count(u64 config)
351 * If the internal 27-bit counter rolled over, the count is MaxCnt
352 * and the lower 7 bits of CurCnt are randomized.
353 * Otherwise CurCnt has the full 27-bit current counter value.
355 if (config & IBS_OP_VAL)
356 count = (config & IBS_OP_MAX_CNT) << 4;
357 else if (ibs_caps & IBS_CAPS_RDWROPCNT)
358 count = (config & IBS_OP_CUR_CNT) >> 32;
364 perf_ibs_event_update(struct perf_ibs *perf_ibs, struct perf_event *event,
367 u64 count = perf_ibs->get_count(*config);
370 * Set width to 64 since we do not overflow on max width but
371 * instead on max count. In perf_ibs_set_period() we clear
372 * prev count manually on overflow.
374 while (!perf_event_try_update(event, count, 64)) {
375 rdmsrl(event->hw.config_base, *config);
376 count = perf_ibs->get_count(*config);
380 static inline void perf_ibs_enable_event(struct perf_ibs *perf_ibs,
381 struct hw_perf_event *hwc, u64 config)
383 u64 tmp = hwc->config | config;
385 if (perf_ibs->fetch_count_reset_broken)
386 wrmsrl(hwc->config_base, tmp & ~perf_ibs->enable_mask);
388 wrmsrl(hwc->config_base, tmp | perf_ibs->enable_mask);
392 * Erratum #420 Instruction-Based Sampling Engine May Generate
393 * Interrupt that Cannot Be Cleared:
395 * Must clear counter mask first, then clear the enable bit. See
396 * Revision Guide for AMD Family 10h Processors, Publication #41322.
398 static inline void perf_ibs_disable_event(struct perf_ibs *perf_ibs,
399 struct hw_perf_event *hwc, u64 config)
401 config &= ~perf_ibs->cnt_mask;
402 if (boot_cpu_data.x86 == 0x10)
403 wrmsrl(hwc->config_base, config);
404 config &= ~perf_ibs->enable_mask;
405 wrmsrl(hwc->config_base, config);
409 * We cannot restore the ibs pmu state, so we always needs to update
410 * the event while stopping it and then reset the state when starting
411 * again. Thus, ignoring PERF_EF_RELOAD and PERF_EF_UPDATE flags in
412 * perf_ibs_start()/perf_ibs_stop() and instead always do it.
414 static void perf_ibs_start(struct perf_event *event, int flags)
416 struct hw_perf_event *hwc = &event->hw;
417 struct perf_ibs *perf_ibs = container_of(event->pmu, struct perf_ibs, pmu);
418 struct cpu_perf_ibs *pcpu = this_cpu_ptr(perf_ibs->pcpu);
421 if (WARN_ON_ONCE(!(hwc->state & PERF_HES_STOPPED)))
424 WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
427 perf_ibs_set_period(perf_ibs, hwc, &period);
429 * Set STARTED before enabling the hardware, such that a subsequent NMI
432 set_bit(IBS_STARTED, pcpu->state);
433 clear_bit(IBS_STOPPING, pcpu->state);
434 perf_ibs_enable_event(perf_ibs, hwc, period >> 4);
436 perf_event_update_userpage(event);
439 static void perf_ibs_stop(struct perf_event *event, int flags)
441 struct hw_perf_event *hwc = &event->hw;
442 struct perf_ibs *perf_ibs = container_of(event->pmu, struct perf_ibs, pmu);
443 struct cpu_perf_ibs *pcpu = this_cpu_ptr(perf_ibs->pcpu);
447 if (test_and_set_bit(IBS_STOPPING, pcpu->state))
450 stopping = test_bit(IBS_STARTED, pcpu->state);
452 if (!stopping && (hwc->state & PERF_HES_UPTODATE))
455 rdmsrl(hwc->config_base, config);
459 * Set STOPPED before disabling the hardware, such that it
460 * must be visible to NMIs the moment we clear the EN bit,
461 * at which point we can generate an !VALID sample which
462 * we need to consume.
464 set_bit(IBS_STOPPED, pcpu->state);
465 perf_ibs_disable_event(perf_ibs, hwc, config);
467 * Clear STARTED after disabling the hardware; if it were
468 * cleared before an NMI hitting after the clear but before
469 * clearing the EN bit might think it a spurious NMI and not
472 * Clearing it after, however, creates the problem of the NMI
473 * handler seeing STARTED but not having a valid sample.
475 clear_bit(IBS_STARTED, pcpu->state);
476 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
477 hwc->state |= PERF_HES_STOPPED;
480 if (hwc->state & PERF_HES_UPTODATE)
484 * Clear valid bit to not count rollovers on update, rollovers
485 * are only updated in the irq handler.
487 config &= ~perf_ibs->valid_mask;
489 perf_ibs_event_update(perf_ibs, event, &config);
490 hwc->state |= PERF_HES_UPTODATE;
493 static int perf_ibs_add(struct perf_event *event, int flags)
495 struct perf_ibs *perf_ibs = container_of(event->pmu, struct perf_ibs, pmu);
496 struct cpu_perf_ibs *pcpu = this_cpu_ptr(perf_ibs->pcpu);
498 if (test_and_set_bit(IBS_ENABLED, pcpu->state))
501 event->hw.state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
505 if (flags & PERF_EF_START)
506 perf_ibs_start(event, PERF_EF_RELOAD);
511 static void perf_ibs_del(struct perf_event *event, int flags)
513 struct perf_ibs *perf_ibs = container_of(event->pmu, struct perf_ibs, pmu);
514 struct cpu_perf_ibs *pcpu = this_cpu_ptr(perf_ibs->pcpu);
516 if (!test_and_clear_bit(IBS_ENABLED, pcpu->state))
519 perf_ibs_stop(event, PERF_EF_UPDATE);
523 perf_event_update_userpage(event);
526 static void perf_ibs_read(struct perf_event *event) { }
528 PMU_FORMAT_ATTR(rand_en, "config:57");
529 PMU_FORMAT_ATTR(cnt_ctl, "config:19");
531 static struct attribute *ibs_fetch_format_attrs[] = {
532 &format_attr_rand_en.attr,
536 static struct attribute *ibs_op_format_attrs[] = {
537 NULL, /* &format_attr_cnt_ctl.attr if IBS_CAPS_OPCNT */
541 static struct perf_ibs perf_ibs_fetch = {
543 .task_ctx_nr = perf_invalid_context,
545 .event_init = perf_ibs_init,
548 .start = perf_ibs_start,
549 .stop = perf_ibs_stop,
550 .read = perf_ibs_read,
552 .msr = MSR_AMD64_IBSFETCHCTL,
553 .config_mask = IBS_FETCH_CONFIG_MASK,
554 .cnt_mask = IBS_FETCH_MAX_CNT,
555 .enable_mask = IBS_FETCH_ENABLE,
556 .valid_mask = IBS_FETCH_VAL,
557 .max_period = IBS_FETCH_MAX_CNT << 4,
558 .offset_mask = { MSR_AMD64_IBSFETCH_REG_MASK },
559 .offset_max = MSR_AMD64_IBSFETCH_REG_COUNT,
560 .format_attrs = ibs_fetch_format_attrs,
562 .get_count = get_ibs_fetch_count,
565 static struct perf_ibs perf_ibs_op = {
567 .task_ctx_nr = perf_invalid_context,
569 .event_init = perf_ibs_init,
572 .start = perf_ibs_start,
573 .stop = perf_ibs_stop,
574 .read = perf_ibs_read,
576 .msr = MSR_AMD64_IBSOPCTL,
577 .config_mask = IBS_OP_CONFIG_MASK,
578 .cnt_mask = IBS_OP_MAX_CNT | IBS_OP_CUR_CNT |
580 .enable_mask = IBS_OP_ENABLE,
581 .valid_mask = IBS_OP_VAL,
582 .max_period = IBS_OP_MAX_CNT << 4,
583 .offset_mask = { MSR_AMD64_IBSOP_REG_MASK },
584 .offset_max = MSR_AMD64_IBSOP_REG_COUNT,
585 .format_attrs = ibs_op_format_attrs,
587 .get_count = get_ibs_op_count,
590 static int perf_ibs_handle_irq(struct perf_ibs *perf_ibs, struct pt_regs *iregs)
592 struct cpu_perf_ibs *pcpu = this_cpu_ptr(perf_ibs->pcpu);
593 struct perf_event *event = pcpu->event;
594 struct hw_perf_event *hwc;
595 struct perf_sample_data data;
596 struct perf_raw_record raw;
598 struct perf_ibs_data ibs_data;
599 int offset, size, check_rip, offset_max, throttle = 0;
601 u64 *buf, *config, period;
603 if (!test_bit(IBS_STARTED, pcpu->state)) {
606 * Catch spurious interrupts after stopping IBS: After
607 * disabling IBS there could be still incoming NMIs
608 * with samples that even have the valid bit cleared.
609 * Mark all this NMIs as handled.
611 if (test_and_clear_bit(IBS_STOPPED, pcpu->state))
617 if (WARN_ON_ONCE(!event))
621 msr = hwc->config_base;
624 if (!(*buf++ & perf_ibs->valid_mask))
627 config = &ibs_data.regs[0];
628 perf_ibs_event_update(perf_ibs, event, config);
629 perf_sample_data_init(&data, 0, hwc->last_period);
630 if (!perf_ibs_set_period(perf_ibs, hwc, &period))
631 goto out; /* no sw counter overflow */
633 ibs_data.caps = ibs_caps;
636 check_rip = (perf_ibs == &perf_ibs_op && (ibs_caps & IBS_CAPS_RIPINVALIDCHK));
637 if (event->attr.sample_type & PERF_SAMPLE_RAW)
638 offset_max = perf_ibs->offset_max;
644 rdmsrl(msr + offset, *buf++);
646 offset = find_next_bit(perf_ibs->offset_mask,
647 perf_ibs->offset_max,
649 } while (offset < offset_max);
651 * Read IbsBrTarget, IbsOpData4, and IbsExtdCtl separately
652 * depending on their availability.
653 * Can't add to offset_max as they are staggered
655 if (event->attr.sample_type & PERF_SAMPLE_RAW) {
656 if (perf_ibs == &perf_ibs_op) {
657 if (ibs_caps & IBS_CAPS_BRNTRGT) {
658 rdmsrl(MSR_AMD64_IBSBRTARGET, *buf++);
661 if (ibs_caps & IBS_CAPS_OPDATA4) {
662 rdmsrl(MSR_AMD64_IBSOPDATA4, *buf++);
666 if (perf_ibs == &perf_ibs_fetch && (ibs_caps & IBS_CAPS_FETCHCTLEXTD)) {
667 rdmsrl(MSR_AMD64_ICIBSEXTDCTL, *buf++);
671 ibs_data.size = sizeof(u64) * size;
674 if (check_rip && (ibs_data.regs[2] & IBS_RIP_INVALID)) {
675 regs.flags &= ~PERF_EFLAGS_EXACT;
677 /* Workaround for erratum #1197 */
678 if (perf_ibs->fetch_ignore_if_zero_rip && !(ibs_data.regs[1]))
681 set_linear_ip(®s, ibs_data.regs[1]);
682 regs.flags |= PERF_EFLAGS_EXACT;
685 if (event->attr.sample_type & PERF_SAMPLE_RAW) {
686 raw = (struct perf_raw_record){
688 .size = sizeof(u32) + ibs_data.size,
689 .data = ibs_data.data,
695 throttle = perf_event_overflow(event, &data, ®s);
698 perf_ibs_stop(event, 0);
702 if ((ibs_caps & IBS_CAPS_RDWROPCNT) &&
703 (*config & IBS_OP_CNT_CTL))
704 period |= *config & IBS_OP_CUR_CNT_RAND;
706 perf_ibs_enable_event(perf_ibs, hwc, period);
709 perf_event_update_userpage(event);
715 perf_ibs_nmi_handler(unsigned int cmd, struct pt_regs *regs)
717 u64 stamp = sched_clock();
720 handled += perf_ibs_handle_irq(&perf_ibs_fetch, regs);
721 handled += perf_ibs_handle_irq(&perf_ibs_op, regs);
724 inc_irq_stat(apic_perf_irqs);
726 perf_sample_event_took(sched_clock() - stamp);
730 NOKPROBE_SYMBOL(perf_ibs_nmi_handler);
732 static __init int perf_ibs_pmu_init(struct perf_ibs *perf_ibs, char *name)
734 struct cpu_perf_ibs __percpu *pcpu;
737 pcpu = alloc_percpu(struct cpu_perf_ibs);
741 perf_ibs->pcpu = pcpu;
743 /* register attributes */
744 if (perf_ibs->format_attrs[0]) {
745 memset(&perf_ibs->format_group, 0, sizeof(perf_ibs->format_group));
746 perf_ibs->format_group.name = "format";
747 perf_ibs->format_group.attrs = perf_ibs->format_attrs;
749 memset(&perf_ibs->attr_groups, 0, sizeof(perf_ibs->attr_groups));
750 perf_ibs->attr_groups[0] = &perf_ibs->format_group;
751 perf_ibs->pmu.attr_groups = perf_ibs->attr_groups;
754 ret = perf_pmu_register(&perf_ibs->pmu, name, -1);
756 perf_ibs->pcpu = NULL;
763 static __init void perf_event_ibs_init(void)
765 struct attribute **attr = ibs_op_format_attrs;
768 * Some chips fail to reset the fetch count when it is written; instead
769 * they need a 0-1 transition of IbsFetchEn.
771 if (boot_cpu_data.x86 >= 0x16 && boot_cpu_data.x86 <= 0x18)
772 perf_ibs_fetch.fetch_count_reset_broken = 1;
774 if (boot_cpu_data.x86 == 0x19 && boot_cpu_data.x86_model < 0x10)
775 perf_ibs_fetch.fetch_ignore_if_zero_rip = 1;
777 perf_ibs_pmu_init(&perf_ibs_fetch, "ibs_fetch");
779 if (ibs_caps & IBS_CAPS_OPCNT) {
780 perf_ibs_op.config_mask |= IBS_OP_CNT_CTL;
781 *attr++ = &format_attr_cnt_ctl.attr;
783 perf_ibs_pmu_init(&perf_ibs_op, "ibs_op");
785 register_nmi_handler(NMI_LOCAL, perf_ibs_nmi_handler, 0, "perf_ibs");
786 pr_info("perf: AMD IBS detected (0x%08x)\n", ibs_caps);
789 #else /* defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_AMD) */
791 static __init void perf_event_ibs_init(void) { }
795 /* IBS - apic initialization, for perf and oprofile */
797 static __init u32 __get_ibs_caps(void)
800 unsigned int max_level;
802 if (!boot_cpu_has(X86_FEATURE_IBS))
805 /* check IBS cpuid feature flags */
806 max_level = cpuid_eax(0x80000000);
807 if (max_level < IBS_CPUID_FEATURES)
808 return IBS_CAPS_DEFAULT;
810 caps = cpuid_eax(IBS_CPUID_FEATURES);
811 if (!(caps & IBS_CAPS_AVAIL))
812 /* cpuid flags not valid */
813 return IBS_CAPS_DEFAULT;
818 u32 get_ibs_caps(void)
823 EXPORT_SYMBOL(get_ibs_caps);
825 static inline int get_eilvt(int offset)
827 return !setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_NMI, 1);
830 static inline int put_eilvt(int offset)
832 return !setup_APIC_eilvt(offset, 0, 0, 1);
836 * Check and reserve APIC extended interrupt LVT offset for IBS if available.
838 static inline int ibs_eilvt_valid(void)
846 rdmsrl(MSR_AMD64_IBSCTL, val);
847 offset = val & IBSCTL_LVT_OFFSET_MASK;
849 if (!(val & IBSCTL_LVT_OFFSET_VALID)) {
850 pr_err(FW_BUG "cpu %d, invalid IBS interrupt offset %d (MSR%08X=0x%016llx)\n",
851 smp_processor_id(), offset, MSR_AMD64_IBSCTL, val);
855 if (!get_eilvt(offset)) {
856 pr_err(FW_BUG "cpu %d, IBS interrupt offset %d not available (MSR%08X=0x%016llx)\n",
857 smp_processor_id(), offset, MSR_AMD64_IBSCTL, val);
868 static int setup_ibs_ctl(int ibs_eilvt_off)
870 struct pci_dev *cpu_cfg;
877 cpu_cfg = pci_get_device(PCI_VENDOR_ID_AMD,
878 PCI_DEVICE_ID_AMD_10H_NB_MISC,
883 pci_write_config_dword(cpu_cfg, IBSCTL, ibs_eilvt_off
884 | IBSCTL_LVT_OFFSET_VALID);
885 pci_read_config_dword(cpu_cfg, IBSCTL, &value);
886 if (value != (ibs_eilvt_off | IBSCTL_LVT_OFFSET_VALID)) {
887 pci_dev_put(cpu_cfg);
888 pr_debug("Failed to setup IBS LVT offset, IBSCTL = 0x%08x\n",
895 pr_debug("No CPU node configured for IBS\n");
903 * This runs only on the current cpu. We try to find an LVT offset and
904 * setup the local APIC. For this we must disable preemption. On
905 * success we initialize all nodes with this offset. This updates then
906 * the offset in the IBS_CTL per-node msr. The per-core APIC setup of
907 * the IBS interrupt vector is handled by perf_ibs_cpu_notifier that
908 * is using the new offset.
910 static void force_ibs_eilvt_setup(void)
916 /* find the next free available EILVT entry, skip offset 0 */
917 for (offset = 1; offset < APIC_EILVT_NR_MAX; offset++) {
918 if (get_eilvt(offset))
923 if (offset == APIC_EILVT_NR_MAX) {
924 pr_debug("No EILVT entry available\n");
928 ret = setup_ibs_ctl(offset);
932 if (!ibs_eilvt_valid())
935 pr_info("IBS: LVT offset %d assigned\n", offset);
945 static void ibs_eilvt_setup(void)
948 * Force LVT offset assignment for family 10h: The offsets are
949 * not assigned by the BIOS for this family, so the OS is
950 * responsible for doing it. If the OS assignment fails, fall
951 * back to BIOS settings and try to setup this.
953 if (boot_cpu_data.x86 == 0x10)
954 force_ibs_eilvt_setup();
957 static inline int get_ibs_lvt_offset(void)
961 rdmsrl(MSR_AMD64_IBSCTL, val);
962 if (!(val & IBSCTL_LVT_OFFSET_VALID))
965 return val & IBSCTL_LVT_OFFSET_MASK;
968 static void setup_APIC_ibs(void)
972 offset = get_ibs_lvt_offset();
976 if (!setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_NMI, 0))
979 pr_warn("perf: IBS APIC setup failed on cpu #%d\n",
983 static void clear_APIC_ibs(void)
987 offset = get_ibs_lvt_offset();
989 setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_FIX, 1);
992 static int x86_pmu_amd_ibs_starting_cpu(unsigned int cpu)
1000 static int perf_ibs_suspend(void)
1006 static void perf_ibs_resume(void)
1012 static struct syscore_ops perf_ibs_syscore_ops = {
1013 .resume = perf_ibs_resume,
1014 .suspend = perf_ibs_suspend,
1017 static void perf_ibs_pm_init(void)
1019 register_syscore_ops(&perf_ibs_syscore_ops);
1024 static inline void perf_ibs_pm_init(void) { }
1028 static int x86_pmu_amd_ibs_dying_cpu(unsigned int cpu)
1034 static __init int amd_ibs_init(void)
1038 caps = __get_ibs_caps();
1040 return -ENODEV; /* ibs not supported by the cpu */
1044 if (!ibs_eilvt_valid())
1050 /* make ibs_caps visible to other cpus: */
1053 * x86_pmu_amd_ibs_starting_cpu will be called from core on
1056 cpuhp_setup_state(CPUHP_AP_PERF_X86_AMD_IBS_STARTING,
1057 "AP_PERF_X86_AMD_IBS_STARTING",
1058 x86_pmu_amd_ibs_starting_cpu,
1059 x86_pmu_amd_ibs_dying_cpu);
1061 perf_event_ibs_init();
1066 /* Since we need the pci subsystem to init ibs we can't do this earlier: */
1067 device_initcall(amd_ibs_init);