1 /* SPDX-License-Identifier: GPL-2.0 */
3 * linux/arch/x86_64/entry.S
5 * Copyright (C) 1991, 1992 Linus Torvalds
6 * Copyright (C) 2000, 2001, 2002 Andi Kleen SuSE Labs
7 * Copyright (C) 2000 Pavel Machek <pavel@suse.cz>
9 * entry.S contains the system-call and fault low-level handling routines.
11 * Some of this is documented in Documentation/x86/entry_64.rst
13 * A note on terminology:
14 * - iret frame: Architecture defined interrupt frame from SS to RIP
15 * at the top of the kernel process stack.
18 * - ENTRY/END: Define functions in the symbol table.
19 * - TRACE_IRQ_*: Trace hardirq state for lock debugging.
20 * - idtentry: Define exception entry points.
22 #include <linux/linkage.h>
23 #include <asm/segment.h>
24 #include <asm/cache.h>
25 #include <asm/errno.h>
26 #include <asm/asm-offsets.h>
28 #include <asm/unistd.h>
29 #include <asm/thread_info.h>
30 #include <asm/hw_irq.h>
31 #include <asm/page_types.h>
32 #include <asm/irqflags.h>
33 #include <asm/paravirt.h>
34 #include <asm/percpu.h>
37 #include <asm/pgtable_types.h>
38 #include <asm/export.h>
39 #include <asm/frame.h>
40 #include <asm/nospec-branch.h>
41 #include <linux/err.h>
46 .section .entry.text, "ax"
48 #ifdef CONFIG_PARAVIRT
49 ENTRY(native_usergs_sysret64)
53 END(native_usergs_sysret64)
54 #endif /* CONFIG_PARAVIRT */
56 .macro TRACE_IRQS_FLAGS flags:req
57 #ifdef CONFIG_TRACE_IRQFLAGS
58 btl $9, \flags /* interrupts off? */
65 .macro TRACE_IRQS_IRETQ
66 TRACE_IRQS_FLAGS EFLAGS(%rsp)
70 * When dynamic function tracer is enabled it will add a breakpoint
71 * to all locations that it is about to modify, sync CPUs, update
72 * all the code, sync CPUs, then remove the breakpoints. In this time
73 * if lockdep is enabled, it might jump back into the debug handler
74 * outside the updating of the IST protection. (TRACE_IRQS_ON/OFF).
76 * We need to change the IDT table before calling TRACE_IRQS_ON/OFF to
77 * make sure the stack pointer does not get reset back to the top
78 * of the debug stack, and instead just reuses the current stack.
80 #if defined(CONFIG_DYNAMIC_FTRACE) && defined(CONFIG_TRACE_IRQFLAGS)
82 .macro TRACE_IRQS_OFF_DEBUG
83 call debug_stack_set_zero
85 call debug_stack_reset
88 .macro TRACE_IRQS_ON_DEBUG
89 call debug_stack_set_zero
91 call debug_stack_reset
94 .macro TRACE_IRQS_IRETQ_DEBUG
95 btl $9, EFLAGS(%rsp) /* interrupts off? */
102 # define TRACE_IRQS_OFF_DEBUG TRACE_IRQS_OFF
103 # define TRACE_IRQS_ON_DEBUG TRACE_IRQS_ON
104 # define TRACE_IRQS_IRETQ_DEBUG TRACE_IRQS_IRETQ
108 * 64-bit SYSCALL instruction entry. Up to 6 arguments in registers.
110 * This is the only entry point used for 64-bit system calls. The
111 * hardware interface is reasonably well designed and the register to
112 * argument mapping Linux uses fits well with the registers that are
113 * available when SYSCALL is used.
115 * SYSCALL instructions can be found inlined in libc implementations as
116 * well as some other programs and libraries. There are also a handful
117 * of SYSCALL instructions in the vDSO used, for example, as a
118 * clock_gettimeofday fallback.
120 * 64-bit SYSCALL saves rip to rcx, clears rflags.RF, then saves rflags to r11,
121 * then loads new ss, cs, and rip from previously programmed MSRs.
122 * rflags gets masked by a value from another MSR (so CLD and CLAC
123 * are not needed). SYSCALL does not save anything on the stack
124 * and does not change rsp.
126 * Registers on entry:
127 * rax system call number
129 * r11 saved rflags (note: r11 is callee-clobbered register in C ABI)
133 * r10 arg3 (needs to be moved to rcx to conform to C ABI)
136 * (note: r12-r15, rbp, rbx are callee-preserved in C ABI)
138 * Only called from user space.
140 * When user can change pt_regs->foo always force IRET. That is because
141 * it deals with uncanonical addresses better. SYSRET has trouble
142 * with them due to bugs in both AMD and Intel CPUs.
145 ENTRY(entry_SYSCALL_64)
148 * Interrupts are off on entry.
149 * We do not frame this tiny irq-off block with TRACE_IRQS_OFF/ON,
150 * it is too small to ever cause noticeable irq latency.
154 /* tss.sp2 is scratch space. */
155 movq %rsp, PER_CPU_VAR(cpu_tss_rw + TSS_sp2)
156 SWITCH_TO_KERNEL_CR3 scratch_reg=%rsp
157 movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp
159 /* Construct struct pt_regs on stack */
160 pushq $__USER_DS /* pt_regs->ss */
161 pushq PER_CPU_VAR(cpu_tss_rw + TSS_sp2) /* pt_regs->sp */
162 pushq %r11 /* pt_regs->flags */
163 pushq $__USER_CS /* pt_regs->cs */
164 pushq %rcx /* pt_regs->ip */
165 GLOBAL(entry_SYSCALL_64_after_hwframe)
166 pushq %rax /* pt_regs->orig_ax */
168 PUSH_AND_CLEAR_REGS rax=$-ENOSYS
176 /* clobbers %rax, make sure it is after saving the syscall nr */
179 call do_syscall_64 /* returns with IRQs disabled */
181 TRACE_IRQS_IRETQ /* we're about to change IF */
184 * Try to use SYSRET instead of IRET if we're returning to
185 * a completely clean 64-bit userspace context. If we're not,
186 * go to the slow exit path.
191 cmpq %rcx, %r11 /* SYSRET requires RCX == RIP */
192 jne swapgs_restore_regs_and_return_to_usermode
195 * On Intel CPUs, SYSRET with non-canonical RCX/RIP will #GP
196 * in kernel space. This essentially lets the user take over
197 * the kernel, since userspace controls RSP.
199 * If width of "canonical tail" ever becomes variable, this will need
200 * to be updated to remain correct on both old and new CPUs.
202 * Change top bits to match most significant bit (47th or 56th bit
203 * depending on paging mode) in the address.
205 #ifdef CONFIG_X86_5LEVEL
206 ALTERNATIVE "shl $(64 - 48), %rcx; sar $(64 - 48), %rcx", \
207 "shl $(64 - 57), %rcx; sar $(64 - 57), %rcx", X86_FEATURE_LA57
209 shl $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx
210 sar $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx
213 /* If this changed %rcx, it was not canonical */
215 jne swapgs_restore_regs_and_return_to_usermode
217 cmpq $__USER_CS, CS(%rsp) /* CS must match SYSRET */
218 jne swapgs_restore_regs_and_return_to_usermode
221 cmpq %r11, EFLAGS(%rsp) /* R11 == RFLAGS */
222 jne swapgs_restore_regs_and_return_to_usermode
225 * SYSCALL clears RF when it saves RFLAGS in R11 and SYSRET cannot
226 * restore RF properly. If the slowpath sets it for whatever reason, we
227 * need to restore it correctly.
229 * SYSRET can restore TF, but unlike IRET, restoring TF results in a
230 * trap from userspace immediately after SYSRET. This would cause an
231 * infinite loop whenever #DB happens with register state that satisfies
232 * the opportunistic SYSRET conditions. For example, single-stepping
235 * movq $stuck_here, %rcx
240 * would never get past 'stuck_here'.
242 testq $(X86_EFLAGS_RF|X86_EFLAGS_TF), %r11
243 jnz swapgs_restore_regs_and_return_to_usermode
245 /* nothing to check for RSP */
247 cmpq $__USER_DS, SS(%rsp) /* SS must match SYSRET */
248 jne swapgs_restore_regs_and_return_to_usermode
251 * We win! This label is here just for ease of understanding
252 * perf profiles. Nothing jumps here.
254 syscall_return_via_sysret:
259 * Now all regs are restored except RSP and RDI.
260 * Save old stack pointer and switch to trampoline stack.
263 movq PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %rsp
266 pushq RSP-RDI(%rdi) /* RSP */
267 pushq (%rdi) /* RDI */
270 * We are on the trampoline stack. All regs except RDI are live.
271 * We can do future final exit work right here.
273 STACKLEAK_ERASE_NOCLOBBER
275 SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi
280 END(entry_SYSCALL_64)
286 ENTRY(__switch_to_asm)
289 * Save callee-saved registers
290 * This must match the order in inactive_task_frame
300 movq %rsp, TASK_threadsp(%rdi)
301 movq TASK_threadsp(%rsi), %rsp
303 #ifdef CONFIG_STACKPROTECTOR
304 movq TASK_stack_canary(%rsi), %rbx
305 movq %rbx, PER_CPU_VAR(fixed_percpu_data) + stack_canary_offset
309 * When switching from a shallower to a deeper call stack
310 * the RSB may either underflow or use entries populated
311 * with userspace addresses. On CPUs where those concerns
312 * exist, overwrite the RSB with entries which capture
313 * speculative execution to prevent attack.
315 FILL_RETURN_BUFFER %r12, RSB_CLEAR_LOOPS, X86_FEATURE_RSB_CTXSW
317 /* restore callee-saved registers */
329 * A newly forked process directly context switches into this address.
331 * rax: prev task we switched from
332 * rbx: kernel thread func (NULL for user thread)
333 * r12: kernel thread arg
338 call schedule_tail /* rdi: 'prev' task parameter */
340 testq %rbx, %rbx /* from kernel_thread? */
341 jnz 1f /* kernel threads are uncommon */
346 call syscall_return_slowpath /* returns with IRQs disabled */
347 TRACE_IRQS_ON /* user mode is traced as IRQS on */
348 jmp swapgs_restore_regs_and_return_to_usermode
356 * A kernel thread is allowed to return here after successfully
357 * calling do_execve(). Exit to userspace to complete the execve()
365 * Build the entry stubs with some assembler magic.
366 * We pack 1 stub into every 8-byte block.
369 ENTRY(irq_entries_start)
370 vector=FIRST_EXTERNAL_VECTOR
371 .rept (FIRST_SYSTEM_VECTOR - FIRST_EXTERNAL_VECTOR)
372 UNWIND_HINT_IRET_REGS
373 pushq $(~vector+0x80) /* Note: always in signed byte range */
378 END(irq_entries_start)
381 ENTRY(spurious_entries_start)
382 vector=FIRST_SYSTEM_VECTOR
383 .rept (NR_VECTORS - FIRST_SYSTEM_VECTOR)
384 UNWIND_HINT_IRET_REGS
385 pushq $(~vector+0x80) /* Note: always in signed byte range */
390 END(spurious_entries_start)
392 .macro DEBUG_ENTRY_ASSERT_IRQS_OFF
393 #ifdef CONFIG_DEBUG_ENTRY
396 testl $X86_EFLAGS_IF, %eax
405 * Enters the IRQ stack if we're not already using it. NMI-safe. Clobbers
406 * flags and puts old RSP into old_rsp, and leaves all other GPRs alone.
407 * Requires kernel GSBASE.
409 * The invariant is that, if irq_count != -1, then the IRQ stack is in use.
411 .macro ENTER_IRQ_STACK regs=1 old_rsp save_ret=0
412 DEBUG_ENTRY_ASSERT_IRQS_OFF
416 * If save_ret is set, the original stack contains one additional
417 * entry -- the return address. Therefore, move the address one
418 * entry below %rsp to \old_rsp.
420 leaq 8(%rsp), \old_rsp
426 UNWIND_HINT_REGS base=\old_rsp
429 incl PER_CPU_VAR(irq_count)
430 jnz .Lirq_stack_push_old_rsp_\@
433 * Right now, if we just incremented irq_count to zero, we've
434 * claimed the IRQ stack but we haven't switched to it yet.
436 * If anything is added that can interrupt us here without using IST,
437 * it must be *extremely* careful to limit its stack usage. This
438 * could include kprobes and a hypothetical future IST-less #DB
441 * The OOPS unwinder relies on the word at the top of the IRQ
442 * stack linking back to the previous RSP for the entire time we're
443 * on the IRQ stack. For this to work reliably, we need to write
444 * it before we actually move ourselves to the IRQ stack.
447 movq \old_rsp, PER_CPU_VAR(irq_stack_backing_store + IRQ_STACK_SIZE - 8)
448 movq PER_CPU_VAR(hardirq_stack_ptr), %rsp
450 #ifdef CONFIG_DEBUG_ENTRY
452 * If the first movq above becomes wrong due to IRQ stack layout
453 * changes, the only way we'll notice is if we try to unwind right
454 * here. Assert that we set up the stack right to catch this type
457 cmpq -8(%rsp), \old_rsp
458 je .Lirq_stack_okay\@
463 .Lirq_stack_push_old_rsp_\@:
467 UNWIND_HINT_REGS indirect=1
472 * Push the return address to the stack. This return address can
473 * be found at the "real" original RSP, which was offset by 8 at
474 * the beginning of this macro.
481 * Undoes ENTER_IRQ_STACK.
483 .macro LEAVE_IRQ_STACK regs=1
484 DEBUG_ENTRY_ASSERT_IRQS_OFF
485 /* We need to be off the IRQ stack before decrementing irq_count. */
493 * As in ENTER_IRQ_STACK, irq_count == 0, we are still claiming
494 * the irq stack but we're not on it.
497 decl PER_CPU_VAR(irq_count)
501 * Interrupt entry helper function.
503 * Entry runs with interrupts off. Stack layout at entry:
504 * +----------------------------------------------------+
510 * +----------------------------------------------------+
511 * | regs->orig_ax = ~(interrupt number) |
512 * +----------------------------------------------------+
514 * +----------------------------------------------------+
516 ENTRY(interrupt_entry)
517 UNWIND_HINT_IRET_REGS offset=16
521 testb $3, CS-ORIG_RAX+8(%rsp)
524 FENCE_SWAPGS_USER_ENTRY
526 * Switch to the thread stack. The IRET frame and orig_ax are
527 * on the stack, as well as the return address. RDI..R12 are
528 * not (yet) on the stack and space has not (yet) been
529 * allocated for them.
533 /* Need to switch before accessing the thread stack. */
534 SWITCH_TO_KERNEL_CR3 scratch_reg=%rdi
536 movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp
539 * We have RDI, return address, and orig_ax on the stack on
540 * top of the IRET frame. That means offset=24
542 UNWIND_HINT_IRET_REGS base=%rdi offset=24
544 pushq 7*8(%rdi) /* regs->ss */
545 pushq 6*8(%rdi) /* regs->rsp */
546 pushq 5*8(%rdi) /* regs->eflags */
547 pushq 4*8(%rdi) /* regs->cs */
548 pushq 3*8(%rdi) /* regs->ip */
549 UNWIND_HINT_IRET_REGS
550 pushq 2*8(%rdi) /* regs->orig_ax */
551 pushq 8(%rdi) /* return address */
556 FENCE_SWAPGS_KERNEL_ENTRY
558 PUSH_AND_CLEAR_REGS save_ret=1
559 ENCODE_FRAME_POINTER 8
565 * IRQ from user mode.
567 * We need to tell lockdep that IRQs are off. We can't do this until
568 * we fix gsbase, and we should do it before enter_from_user_mode
569 * (which can take locks). Since TRACE_IRQS_OFF is idempotent,
570 * the simplest way to handle it is to just call it twice if
571 * we enter from user mode. There's no reason to optimize this since
572 * TRACE_IRQS_OFF is a no-op if lockdep is off.
576 CALL_enter_from_user_mode
579 ENTER_IRQ_STACK old_rsp=%rdi save_ret=1
580 /* We entered an interrupt context - irqs are off: */
585 _ASM_NOKPROBE(interrupt_entry)
588 /* Interrupt entry/exit. */
591 * The interrupt stubs push (~vector+0x80) onto the stack and
592 * then jump to common_spurious/interrupt.
595 addq $-0x80, (%rsp) /* Adjust vector to [-256, -1] range */
597 UNWIND_HINT_REGS indirect=1
598 call smp_spurious_interrupt /* rdi points to pt_regs */
601 _ASM_NOKPROBE(common_spurious)
603 /* common_interrupt is a hotpath. Align it */
604 .p2align CONFIG_X86_L1_CACHE_SHIFT
606 addq $-0x80, (%rsp) /* Adjust vector to [-256, -1] range */
608 UNWIND_HINT_REGS indirect=1
609 call do_IRQ /* rdi points to pt_regs */
610 /* 0(%rsp): old RSP */
612 DISABLE_INTERRUPTS(CLBR_ANY)
620 /* Interrupt came from user space */
623 call prepare_exit_to_usermode
626 GLOBAL(swapgs_restore_regs_and_return_to_usermode)
628 #ifdef CONFIG_DEBUG_ENTRY
629 /* Assert that pt_regs indicates user mode. */
638 * The stack is now user RDI, orig_ax, RIP, CS, EFLAGS, RSP, SS.
639 * Save old stack pointer and switch to trampoline stack.
642 movq PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %rsp
645 /* Copy the IRET frame to the trampoline stack. */
646 pushq 6*8(%rdi) /* SS */
647 pushq 5*8(%rdi) /* RSP */
648 pushq 4*8(%rdi) /* EFLAGS */
649 pushq 3*8(%rdi) /* CS */
650 pushq 2*8(%rdi) /* RIP */
652 /* Push user RDI on the trampoline stack. */
656 * We are on the trampoline stack. All regs except RDI are live.
657 * We can do future final exit work right here.
659 STACKLEAK_ERASE_NOCLOBBER
661 SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi
669 /* Returning to kernel space */
671 #ifdef CONFIG_PREEMPTION
672 /* Interrupts are off */
673 /* Check if we need preemption */
674 btl $9, EFLAGS(%rsp) /* were interrupts off? */
676 cmpl $0, PER_CPU_VAR(__preempt_count)
678 call preempt_schedule_irq
682 * The iretq could re-enable interrupts:
686 GLOBAL(restore_regs_and_return_to_kernel)
687 #ifdef CONFIG_DEBUG_ENTRY
688 /* Assert that pt_regs indicates kernel mode. */
695 addq $8, %rsp /* skip regs->orig_ax */
697 * ARCH_HAS_MEMBARRIER_SYNC_CORE rely on IRET core serialization
698 * when returning from IPI handler.
703 UNWIND_HINT_IRET_REGS
705 * Are we returning to a stack segment from the LDT? Note: in
706 * 64-bit mode SS:RSP on the exception stack is always valid.
708 #ifdef CONFIG_X86_ESPFIX64
709 testb $4, (SS-RIP)(%rsp)
710 jnz native_irq_return_ldt
713 .global native_irq_return_iret
714 native_irq_return_iret:
716 * This may fault. Non-paranoid faults on return to userspace are
717 * handled by fixup_bad_iret. These include #SS, #GP, and #NP.
718 * Double-faults due to espfix64 are handled in do_double_fault.
719 * Other faults here are fatal.
723 #ifdef CONFIG_X86_ESPFIX64
724 native_irq_return_ldt:
726 * We are running with user GSBASE. All GPRs contain their user
727 * values. We have a percpu ESPFIX stack that is eight slots
728 * long (see ESPFIX_STACK_SIZE). espfix_waddr points to the bottom
729 * of the ESPFIX stack.
731 * We clobber RAX and RDI in this code. We stash RDI on the
732 * normal stack and RAX on the ESPFIX stack.
734 * The ESPFIX stack layout we set up looks like this:
736 * --- top of ESPFIX stack ---
741 * RIP <-- RSP points here when we're done
742 * RAX <-- espfix_waddr points here
743 * --- bottom of ESPFIX stack ---
746 pushq %rdi /* Stash user RDI */
747 SWAPGS /* to kernel GS */
748 SWITCH_TO_KERNEL_CR3 scratch_reg=%rdi /* to kernel CR3 */
750 movq PER_CPU_VAR(espfix_waddr), %rdi
751 movq %rax, (0*8)(%rdi) /* user RAX */
752 movq (1*8)(%rsp), %rax /* user RIP */
753 movq %rax, (1*8)(%rdi)
754 movq (2*8)(%rsp), %rax /* user CS */
755 movq %rax, (2*8)(%rdi)
756 movq (3*8)(%rsp), %rax /* user RFLAGS */
757 movq %rax, (3*8)(%rdi)
758 movq (5*8)(%rsp), %rax /* user SS */
759 movq %rax, (5*8)(%rdi)
760 movq (4*8)(%rsp), %rax /* user RSP */
761 movq %rax, (4*8)(%rdi)
762 /* Now RAX == RSP. */
764 andl $0xffff0000, %eax /* RAX = (RSP & 0xffff0000) */
767 * espfix_stack[31:16] == 0. The page tables are set up such that
768 * (espfix_stack | (X & 0xffff0000)) points to a read-only alias of
769 * espfix_waddr for any X. That is, there are 65536 RO aliases of
770 * the same page. Set up RSP so that RSP[31:16] contains the
771 * respective 16 bits of the /userspace/ RSP and RSP nonetheless
772 * still points to an RO alias of the ESPFIX stack.
774 orq PER_CPU_VAR(espfix_stack), %rax
776 SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi
777 SWAPGS /* to user GS */
778 popq %rdi /* Restore user RDI */
781 UNWIND_HINT_IRET_REGS offset=8
784 * At this point, we cannot write to the stack any more, but we can
787 popq %rax /* Restore user RAX */
790 * RSP now points to an ordinary IRET frame, except that the page
791 * is read-only and RSP[31:16] are preloaded with the userspace
792 * values. We can now IRET back to userspace.
794 jmp native_irq_return_iret
796 END(common_interrupt)
797 _ASM_NOKPROBE(common_interrupt)
802 .macro apicinterrupt3 num sym do_sym
804 UNWIND_HINT_IRET_REGS
808 UNWIND_HINT_REGS indirect=1
809 call \do_sym /* rdi points to pt_regs */
815 /* Make sure APIC interrupt handlers end up in the irqentry section: */
816 #define PUSH_SECTION_IRQENTRY .pushsection .irqentry.text, "ax"
817 #define POP_SECTION_IRQENTRY .popsection
819 .macro apicinterrupt num sym do_sym
820 PUSH_SECTION_IRQENTRY
821 apicinterrupt3 \num \sym \do_sym
826 apicinterrupt3 IRQ_MOVE_CLEANUP_VECTOR irq_move_cleanup_interrupt smp_irq_move_cleanup_interrupt
827 apicinterrupt3 REBOOT_VECTOR reboot_interrupt smp_reboot_interrupt
831 apicinterrupt3 UV_BAU_MESSAGE uv_bau_message_intr1 uv_bau_message_interrupt
834 apicinterrupt LOCAL_TIMER_VECTOR apic_timer_interrupt smp_apic_timer_interrupt
835 apicinterrupt X86_PLATFORM_IPI_VECTOR x86_platform_ipi smp_x86_platform_ipi
837 #ifdef CONFIG_HAVE_KVM
838 apicinterrupt3 POSTED_INTR_VECTOR kvm_posted_intr_ipi smp_kvm_posted_intr_ipi
839 apicinterrupt3 POSTED_INTR_WAKEUP_VECTOR kvm_posted_intr_wakeup_ipi smp_kvm_posted_intr_wakeup_ipi
840 apicinterrupt3 POSTED_INTR_NESTED_VECTOR kvm_posted_intr_nested_ipi smp_kvm_posted_intr_nested_ipi
843 #ifdef CONFIG_X86_MCE_THRESHOLD
844 apicinterrupt THRESHOLD_APIC_VECTOR threshold_interrupt smp_threshold_interrupt
847 #ifdef CONFIG_X86_MCE_AMD
848 apicinterrupt DEFERRED_ERROR_VECTOR deferred_error_interrupt smp_deferred_error_interrupt
851 #ifdef CONFIG_X86_THERMAL_VECTOR
852 apicinterrupt THERMAL_APIC_VECTOR thermal_interrupt smp_thermal_interrupt
856 apicinterrupt CALL_FUNCTION_SINGLE_VECTOR call_function_single_interrupt smp_call_function_single_interrupt
857 apicinterrupt CALL_FUNCTION_VECTOR call_function_interrupt smp_call_function_interrupt
858 apicinterrupt RESCHEDULE_VECTOR reschedule_interrupt smp_reschedule_interrupt
861 apicinterrupt ERROR_APIC_VECTOR error_interrupt smp_error_interrupt
862 apicinterrupt SPURIOUS_APIC_VECTOR spurious_interrupt smp_spurious_interrupt
864 #ifdef CONFIG_IRQ_WORK
865 apicinterrupt IRQ_WORK_VECTOR irq_work_interrupt smp_irq_work_interrupt
869 * Exception entry points.
871 #define CPU_TSS_IST(x) PER_CPU_VAR(cpu_tss_rw) + (TSS_ist + (x) * 8)
873 .macro idtentry_part do_sym, has_error_code:req, read_cr2:req, paranoid:req, shift_ist=-1, ist_offset=0
877 /* returned flag: ebx=0: need swapgs on exit, ebx=1: don't need it */
885 * Store CR2 early so subsequent faults cannot clobber it. Use R12 as
886 * intermediate storage as RDX can be clobbered in enter_from_user_mode().
887 * GET_CR2_INTO can clobber RAX.
893 TRACE_IRQS_OFF_DEBUG /* reload IDT in case of recursion */
900 jz .Lfrom_kernel_no_context_tracking_\@
901 CALL_enter_from_user_mode
902 .Lfrom_kernel_no_context_tracking_\@:
905 movq %rsp, %rdi /* pt_regs pointer */
908 movq ORIG_RAX(%rsp), %rsi /* get error code */
909 movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */
911 xorl %esi, %esi /* no error code */
915 subq $\ist_offset, CPU_TSS_IST(\shift_ist)
919 movq %r12, %rdx /* Move CR2 into 3rd argument */
925 addq $\ist_offset, CPU_TSS_IST(\shift_ist)
929 /* this procedure expect "no swapgs" flag in ebx */
938 * idtentry - Generate an IDT entry stub
939 * @sym: Name of the generated entry point
940 * @do_sym: C function to be called
941 * @has_error_code: True if this IDT vector has an error code on the stack
942 * @paranoid: non-zero means that this vector may be invoked from
943 * kernel mode with user GSBASE and/or user CR3.
944 * 2 is special -- see below.
945 * @shift_ist: Set to an IST index if entries from kernel mode should
946 * decrement the IST stack so that nested entries get a
947 * fresh stack. (This is for #DB, which has a nasty habit
949 * @create_gap: create a 6-word stack gap when coming from kernel mode.
950 * @read_cr2: load CR2 into the 3rd argument; done before calling any C code
952 * idtentry generates an IDT stub that sets up a usable kernel context,
953 * creates struct pt_regs, and calls @do_sym. The stub has the following
956 * On an entry from user mode, the stub switches from the trampoline or
957 * IST stack to the normal thread stack. On an exit to user mode, the
958 * normal exit-to-usermode path is invoked.
960 * On an exit to kernel mode, if @paranoid == 0, we check for preemption,
961 * whereas we omit the preemption check if @paranoid != 0. This is purely
962 * because the implementation is simpler this way. The kernel only needs
963 * to check for asynchronous kernel preemption when IRQ handlers return.
965 * If @paranoid == 0, then the stub will handle IRET faults by pretending
966 * that the fault came from user mode. It will handle gs_change faults by
967 * pretending that the fault happened with kernel GSBASE. Since this handling
968 * is omitted for @paranoid != 0, the #GP, #SS, and #NP stubs must have
969 * @paranoid == 0. This special handling will do the wrong thing for
970 * espfix-induced #DF on IRET, so #DF must not use @paranoid == 0.
972 * @paranoid == 2 is special: the stub will never switch stacks. This is for
973 * #DF: if the thread stack is somehow unusable, we'll still get a useful OOPS.
975 .macro idtentry sym do_sym has_error_code:req paranoid=0 shift_ist=-1 ist_offset=0 create_gap=0 read_cr2=0
977 UNWIND_HINT_IRET_REGS offset=\has_error_code*8
980 .if \shift_ist != -1 && \paranoid != 1
981 .error "using shift_ist requires paranoid=1"
984 .if \create_gap && \paranoid
985 .error "using create_gap requires paranoid=0"
990 .if \has_error_code == 0
991 pushq $-1 /* ORIG_RAX: no syscall to restart */
995 testb $3, CS-ORIG_RAX(%rsp) /* If coming from userspace, switch stacks */
996 jnz .Lfrom_usermode_switch_stack_\@
1001 * If coming from kernel space, create a 6-word gap to allow the
1002 * int3 handler to emulate a call instruction.
1004 testb $3, CS-ORIG_RAX(%rsp)
1005 jnz .Lfrom_usermode_no_gap_\@
1009 UNWIND_HINT_IRET_REGS offset=8
1010 .Lfrom_usermode_no_gap_\@:
1013 idtentry_part \do_sym, \has_error_code, \read_cr2, \paranoid, \shift_ist, \ist_offset
1017 * Entry from userspace. Switch stacks and treat it
1018 * as a normal entry. This means that paranoid handlers
1019 * run in real process context if user_mode(regs).
1021 .Lfrom_usermode_switch_stack_\@:
1022 idtentry_part \do_sym, \has_error_code, \read_cr2, paranoid=0
1029 idtentry divide_error do_divide_error has_error_code=0
1030 idtentry overflow do_overflow has_error_code=0
1031 idtentry bounds do_bounds has_error_code=0
1032 idtentry invalid_op do_invalid_op has_error_code=0
1033 idtentry device_not_available do_device_not_available has_error_code=0
1034 idtentry double_fault do_double_fault has_error_code=1 paranoid=2 read_cr2=1
1035 idtentry coprocessor_segment_overrun do_coprocessor_segment_overrun has_error_code=0
1036 idtentry invalid_TSS do_invalid_TSS has_error_code=1
1037 idtentry segment_not_present do_segment_not_present has_error_code=1
1038 idtentry spurious_interrupt_bug do_spurious_interrupt_bug has_error_code=0
1039 idtentry coprocessor_error do_coprocessor_error has_error_code=0
1040 idtentry alignment_check do_alignment_check has_error_code=1
1041 idtentry simd_coprocessor_error do_simd_coprocessor_error has_error_code=0
1045 * Reload gs selector with exception handling
1048 ENTRY(native_load_gs_index)
1051 DISABLE_INTERRUPTS(CLBR_ANY & ~CLBR_RDI)
1056 2: ALTERNATIVE "", "mfence", X86_BUG_SWAPGS_FENCE
1058 TRACE_IRQS_FLAGS (%rsp)
1062 ENDPROC(native_load_gs_index)
1063 EXPORT_SYMBOL(native_load_gs_index)
1065 _ASM_EXTABLE(.Lgs_change, .Lbad_gs)
1066 .section .fixup, "ax"
1067 /* running with kernelgs */
1069 SWAPGS /* switch back to user gs */
1071 /* This can't be a string because the preprocessor needs to see it. */
1072 movl $__USER_DS, %eax
1075 ALTERNATIVE "", "ZAP_GS", X86_BUG_NULL_SEG
1081 /* Call softirq on interrupt stack. Interrupts are off. */
1082 ENTRY(do_softirq_own_stack)
1085 ENTER_IRQ_STACK regs=0 old_rsp=%r11
1087 LEAVE_IRQ_STACK regs=0
1090 ENDPROC(do_softirq_own_stack)
1092 #ifdef CONFIG_XEN_PV
1093 idtentry hypervisor_callback xen_do_hypervisor_callback has_error_code=0
1096 * A note on the "critical region" in our callback handler.
1097 * We want to avoid stacking callback handlers due to events occurring
1098 * during handling of the last event. To do this, we keep events disabled
1099 * until we've done all processing. HOWEVER, we must enable events before
1100 * popping the stack frame (can't be done atomically) and so it would still
1101 * be possible to get enough handler activations to overflow the stack.
1102 * Although unlikely, bugs of that kind are hard to track down, so we'd
1103 * like to avoid the possibility.
1104 * So, on entry to the handler we detect whether we interrupted an
1105 * existing activation in its critical region -- if so, we pop the current
1106 * activation and restart the handler using the previous one.
1108 ENTRY(xen_do_hypervisor_callback) /* do_hypervisor_callback(struct *pt_regs) */
1111 * Since we don't modify %rdi, evtchn_do_upall(struct *pt_regs) will
1112 * see the correct pointer to the pt_regs
1115 movq %rdi, %rsp /* we don't return, adjust the stack frame */
1118 ENTER_IRQ_STACK old_rsp=%r10
1119 call xen_evtchn_do_upcall
1122 #ifndef CONFIG_PREEMPTION
1123 call xen_maybe_preempt_hcall
1126 END(xen_do_hypervisor_callback)
1129 * Hypervisor uses this for application faults while it executes.
1130 * We get here for two reasons:
1131 * 1. Fault while reloading DS, ES, FS or GS
1132 * 2. Fault while executing IRET
1133 * Category 1 we do not need to fix up as Xen has already reloaded all segment
1134 * registers that could be reloaded and zeroed the others.
1135 * Category 2 we fix up by killing the current process. We cannot use the
1136 * normal Linux return path in this case because if we use the IRET hypercall
1137 * to pop the stack frame we end up in an infinite loop of failsafe callbacks.
1138 * We distinguish between categories by comparing each saved segment register
1139 * with its current contents: any discrepancy means we in category 1.
1141 ENTRY(xen_failsafe_callback)
1144 cmpw %cx, 0x10(%rsp)
1147 cmpw %cx, 0x18(%rsp)
1150 cmpw %cx, 0x20(%rsp)
1153 cmpw %cx, 0x28(%rsp)
1155 /* All segments match their saved values => Category 2 (Bad IRET). */
1160 UNWIND_HINT_IRET_REGS offset=8
1161 jmp general_protection
1162 1: /* Segment mismatch => Category 1 (Bad segment). Retry the IRET. */
1166 UNWIND_HINT_IRET_REGS
1167 pushq $-1 /* orig_ax = -1 => not a system call */
1169 ENCODE_FRAME_POINTER
1171 END(xen_failsafe_callback)
1172 #endif /* CONFIG_XEN_PV */
1174 #ifdef CONFIG_XEN_PVHVM
1175 apicinterrupt3 HYPERVISOR_CALLBACK_VECTOR \
1176 xen_hvm_callback_vector xen_evtchn_do_upcall
1180 #if IS_ENABLED(CONFIG_HYPERV)
1181 apicinterrupt3 HYPERVISOR_CALLBACK_VECTOR \
1182 hyperv_callback_vector hyperv_vector_handler
1184 apicinterrupt3 HYPERV_REENLIGHTENMENT_VECTOR \
1185 hyperv_reenlightenment_vector hyperv_reenlightenment_intr
1187 apicinterrupt3 HYPERV_STIMER0_VECTOR \
1188 hv_stimer0_callback_vector hv_stimer0_vector_handler
1189 #endif /* CONFIG_HYPERV */
1191 #if IS_ENABLED(CONFIG_ACRN_GUEST)
1192 apicinterrupt3 HYPERVISOR_CALLBACK_VECTOR \
1193 acrn_hv_callback_vector acrn_hv_vector_handler
1196 idtentry debug do_debug has_error_code=0 paranoid=1 shift_ist=IST_INDEX_DB ist_offset=DB_STACK_OFFSET
1197 idtentry int3 do_int3 has_error_code=0 create_gap=1
1198 idtentry stack_segment do_stack_segment has_error_code=1
1200 #ifdef CONFIG_XEN_PV
1201 idtentry xennmi do_nmi has_error_code=0
1202 idtentry xendebug do_debug has_error_code=0
1205 idtentry general_protection do_general_protection has_error_code=1
1206 idtentry page_fault do_page_fault has_error_code=1 read_cr2=1
1208 #ifdef CONFIG_KVM_GUEST
1209 idtentry async_page_fault do_async_page_fault has_error_code=1 read_cr2=1
1212 #ifdef CONFIG_X86_MCE
1213 idtentry machine_check do_mce has_error_code=0 paranoid=1
1217 * Save all registers in pt_regs, and switch gs if needed.
1218 * Use slow, but surefire "are we in kernel?" check.
1219 * Return: ebx=0: need swapgs on exit, ebx=1: otherwise
1221 ENTRY(paranoid_entry)
1224 PUSH_AND_CLEAR_REGS save_ret=1
1225 ENCODE_FRAME_POINTER 8
1227 movl $MSR_GS_BASE, %ecx
1230 js 1f /* negative -> in kernel */
1236 * Always stash CR3 in %r14. This value will be restored,
1237 * verbatim, at exit. Needed if paranoid_entry interrupted
1238 * another entry that already switched to the user CR3 value
1239 * but has not yet returned to userspace.
1241 * This is also why CS (stashed in the "iret frame" by the
1242 * hardware at entry) can not be used: this may be a return
1243 * to kernel code, but with a user CR3 value.
1245 SAVE_AND_SWITCH_TO_KERNEL_CR3 scratch_reg=%rax save_reg=%r14
1248 * The above SAVE_AND_SWITCH_TO_KERNEL_CR3 macro doesn't do an
1249 * unconditional CR3 write, even in the PTI case. So do an lfence
1250 * to prevent GS speculation, regardless of whether PTI is enabled.
1252 FENCE_SWAPGS_KERNEL_ENTRY
1255 * Once we have CR3 and %GS setup save and set SPEC_CTRL. Just like
1256 * CR3 above, keep the old value in a callee saved register.
1258 IBRS_ENTER save_reg=%r15
1264 * "Paranoid" exit path from exception stack. This is invoked
1265 * only on return from non-NMI IST interrupts that came
1266 * from kernel space.
1268 * We may be returning to very strange contexts (e.g. very early
1269 * in syscall entry), so checking for preemption here would
1270 * be complicated. Fortunately, we there's no good reason
1271 * to try to handle preemption here.
1273 * On entry, ebx is "no swapgs" flag (1: don't need swapgs, 0: need it)
1275 ENTRY(paranoid_exit)
1277 DISABLE_INTERRUPTS(CLBR_ANY)
1278 TRACE_IRQS_OFF_DEBUG
1279 testl %ebx, %ebx /* swapgs needed? */
1280 jnz .Lparanoid_exit_no_swapgs
1282 /* Always restore stashed CR3 value (see paranoid_entry) */
1283 RESTORE_CR3 scratch_reg=%rbx save_reg=%r14
1285 jmp .Lparanoid_exit_restore
1286 .Lparanoid_exit_no_swapgs:
1287 TRACE_IRQS_IRETQ_DEBUG
1290 * Must restore IBRS state before both CR3 and %GS since we need access
1291 * to the per-CPU x86_spec_ctrl_shadow variable.
1293 IBRS_EXIT save_reg=%r15
1295 /* Always restore stashed CR3 value (see paranoid_entry) */
1296 RESTORE_CR3 scratch_reg=%rbx save_reg=%r14
1297 .Lparanoid_exit_restore:
1298 jmp restore_regs_and_return_to_kernel
1303 * Save all registers in pt_regs, and switch GS if needed.
1308 PUSH_AND_CLEAR_REGS save_ret=1
1309 ENCODE_FRAME_POINTER 8
1310 testb $3, CS+8(%rsp)
1311 jz .Lerror_kernelspace
1314 * We entered from user mode or we're pretending to have entered
1315 * from user mode due to an IRET fault.
1318 FENCE_SWAPGS_USER_ENTRY
1319 /* We have user CR3. Change to kernel CR3. */
1320 SWITCH_TO_KERNEL_CR3 scratch_reg=%rax
1323 .Lerror_entry_from_usermode_after_swapgs:
1324 /* Put us onto the real thread stack. */
1325 popq %r12 /* save return addr in %12 */
1326 movq %rsp, %rdi /* arg0 = pt_regs pointer */
1328 movq %rax, %rsp /* switch stack */
1329 ENCODE_FRAME_POINTER
1333 .Lerror_entry_done_lfence:
1334 FENCE_SWAPGS_KERNEL_ENTRY
1339 * There are two places in the kernel that can potentially fault with
1340 * usergs. Handle them here. B stepping K8s sometimes report a
1341 * truncated RIP for IRET exceptions returning to compat mode. Check
1342 * for these here too.
1344 .Lerror_kernelspace:
1345 leaq native_irq_return_iret(%rip), %rcx
1346 cmpq %rcx, RIP+8(%rsp)
1348 movl %ecx, %eax /* zero extend */
1349 cmpq %rax, RIP+8(%rsp)
1351 cmpq $.Lgs_change, RIP+8(%rsp)
1352 jne .Lerror_entry_done_lfence
1355 * hack: .Lgs_change can fail with user gsbase. If this happens, fix up
1356 * gsbase and proceed. We'll fix up the exception and land in
1357 * .Lgs_change's error handler with kernel gsbase.
1360 FENCE_SWAPGS_USER_ENTRY
1361 SWITCH_TO_KERNEL_CR3 scratch_reg=%rax
1362 jmp .Lerror_entry_done
1365 /* Fix truncated RIP */
1366 movq %rcx, RIP+8(%rsp)
1371 * We came from an IRET to user mode, so we have user
1372 * gsbase and CR3. Switch to kernel gsbase and CR3:
1375 FENCE_SWAPGS_USER_ENTRY
1376 SWITCH_TO_KERNEL_CR3 scratch_reg=%rax
1380 * Pretend that the exception came from user mode: set up pt_regs
1381 * as if we faulted immediately after IRET.
1386 jmp .Lerror_entry_from_usermode_after_swapgs
1391 DISABLE_INTERRUPTS(CLBR_ANY)
1399 * Runs on exception stack. Xen PV does not go through this path at all,
1400 * so we can use real assembly here.
1403 * %r14: Used to save/restore the CR3 of the interrupted context
1404 * when PAGE_TABLE_ISOLATION is in use. Do not clobber.
1407 UNWIND_HINT_IRET_REGS
1410 * We allow breakpoints in NMIs. If a breakpoint occurs, then
1411 * the iretq it performs will take us out of NMI context.
1412 * This means that we can have nested NMIs where the next
1413 * NMI is using the top of the stack of the previous NMI. We
1414 * can't let it execute because the nested NMI will corrupt the
1415 * stack of the previous NMI. NMI handlers are not re-entrant
1418 * To handle this case we do the following:
1419 * Check the a special location on the stack that contains
1420 * a variable that is set when NMIs are executing.
1421 * The interrupted task's stack is also checked to see if it
1423 * If the variable is not set and the stack is not the NMI
1425 * o Set the special variable on the stack
1426 * o Copy the interrupt frame into an "outermost" location on the
1428 * o Copy the interrupt frame into an "iret" location on the stack
1429 * o Continue processing the NMI
1430 * If the variable is set or the previous stack is the NMI stack:
1431 * o Modify the "iret" location to jump to the repeat_nmi
1432 * o return back to the first NMI
1434 * Now on exit of the first NMI, we first clear the stack variable
1435 * The NMI stack will tell any nested NMIs at that point that it is
1436 * nested. Then we pop the stack normally with iret, and if there was
1437 * a nested NMI that updated the copy interrupt stack frame, a
1438 * jump will be made to the repeat_nmi code that will handle the second
1441 * However, espfix prevents us from directly returning to userspace
1442 * with a single IRET instruction. Similarly, IRET to user mode
1443 * can fault. We therefore handle NMIs from user space like
1444 * other IST entries.
1449 /* Use %rdx as our temp variable throughout */
1452 testb $3, CS-RIP+8(%rsp)
1453 jz .Lnmi_from_kernel
1456 * NMI from user mode. We need to run on the thread stack, but we
1457 * can't go through the normal entry paths: NMIs are masked, and
1458 * we don't want to enable interrupts, because then we'll end
1459 * up in an awkward situation in which IRQs are on but NMIs
1462 * We also must not push anything to the stack before switching
1463 * stacks lest we corrupt the "NMI executing" variable.
1468 FENCE_SWAPGS_USER_ENTRY
1469 SWITCH_TO_KERNEL_CR3 scratch_reg=%rdx
1471 movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp
1472 UNWIND_HINT_IRET_REGS base=%rdx offset=8
1473 pushq 5*8(%rdx) /* pt_regs->ss */
1474 pushq 4*8(%rdx) /* pt_regs->rsp */
1475 pushq 3*8(%rdx) /* pt_regs->flags */
1476 pushq 2*8(%rdx) /* pt_regs->cs */
1477 pushq 1*8(%rdx) /* pt_regs->rip */
1478 UNWIND_HINT_IRET_REGS
1479 pushq $-1 /* pt_regs->orig_ax */
1480 PUSH_AND_CLEAR_REGS rdx=(%rdx)
1481 ENCODE_FRAME_POINTER
1486 * At this point we no longer need to worry about stack damage
1487 * due to nesting -- we're on the normal thread stack and we're
1488 * done with the NMI stack.
1496 * Return back to user mode. We must *not* do the normal exit
1497 * work, because we don't want to enable interrupts.
1499 jmp swapgs_restore_regs_and_return_to_usermode
1503 * Here's what our stack frame will look like:
1504 * +---------------------------------------------------------+
1506 * | original Return RSP |
1507 * | original RFLAGS |
1510 * +---------------------------------------------------------+
1511 * | temp storage for rdx |
1512 * +---------------------------------------------------------+
1513 * | "NMI executing" variable |
1514 * +---------------------------------------------------------+
1515 * | iret SS } Copied from "outermost" frame |
1516 * | iret Return RSP } on each loop iteration; overwritten |
1517 * | iret RFLAGS } by a nested NMI to force another |
1518 * | iret CS } iteration if needed. |
1520 * +---------------------------------------------------------+
1521 * | outermost SS } initialized in first_nmi; |
1522 * | outermost Return RSP } will not be changed before |
1523 * | outermost RFLAGS } NMI processing is done. |
1524 * | outermost CS } Copied to "iret" frame on each |
1525 * | outermost RIP } iteration. |
1526 * +---------------------------------------------------------+
1528 * +---------------------------------------------------------+
1530 * The "original" frame is used by hardware. Before re-enabling
1531 * NMIs, we need to be done with it, and we need to leave enough
1532 * space for the asm code here.
1534 * We return by executing IRET while RSP points to the "iret" frame.
1535 * That will either return for real or it will loop back into NMI
1538 * The "outermost" frame is copied to the "iret" frame on each
1539 * iteration of the loop, so each iteration starts with the "iret"
1540 * frame pointing to the final return target.
1544 * Determine whether we're a nested NMI.
1546 * If we interrupted kernel code between repeat_nmi and
1547 * end_repeat_nmi, then we are a nested NMI. We must not
1548 * modify the "iret" frame because it's being written by
1549 * the outer NMI. That's okay; the outer NMI handler is
1550 * about to about to call do_nmi anyway, so we can just
1551 * resume the outer NMI.
1554 movq $repeat_nmi, %rdx
1557 movq $end_repeat_nmi, %rdx
1563 * Now check "NMI executing". If it's set, then we're nested.
1564 * This will not detect if we interrupted an outer NMI just
1571 * Now test if the previous stack was an NMI stack. This covers
1572 * the case where we interrupt an outer NMI after it clears
1573 * "NMI executing" but before IRET. We need to be careful, though:
1574 * there is one case in which RSP could point to the NMI stack
1575 * despite there being no NMI active: naughty userspace controls
1576 * RSP at the very beginning of the SYSCALL targets. We can
1577 * pull a fast one on naughty userspace, though: we program
1578 * SYSCALL to mask DF, so userspace cannot cause DF to be set
1579 * if it controls the kernel's RSP. We set DF before we clear
1583 /* Compare the NMI stack (rdx) with the stack we came from (4*8(%rsp)) */
1584 cmpq %rdx, 4*8(%rsp)
1585 /* If the stack pointer is above the NMI stack, this is a normal NMI */
1588 subq $EXCEPTION_STKSZ, %rdx
1589 cmpq %rdx, 4*8(%rsp)
1590 /* If it is below the NMI stack, it is a normal NMI */
1593 /* Ah, it is within the NMI stack. */
1595 testb $(X86_EFLAGS_DF >> 8), (3*8 + 1)(%rsp)
1596 jz first_nmi /* RSP was user controlled. */
1598 /* This is a nested NMI. */
1602 * Modify the "iret" frame to point to repeat_nmi, forcing another
1603 * iteration of NMI handling.
1606 leaq -10*8(%rsp), %rdx
1613 /* Put stack back */
1619 /* We are returning to kernel mode, so this cannot result in a fault. */
1626 /* Make room for "NMI executing". */
1629 /* Leave room for the "iret" frame */
1632 /* Copy the "original" frame to the "outermost" frame */
1636 UNWIND_HINT_IRET_REGS
1638 /* Everything up to here is safe from nested NMIs */
1640 #ifdef CONFIG_DEBUG_ENTRY
1642 * For ease of testing, unmask NMIs right away. Disabled by
1643 * default because IRET is very expensive.
1646 pushq %rsp /* RSP (minus 8 because of the previous push) */
1647 addq $8, (%rsp) /* Fix up RSP */
1649 pushq $__KERNEL_CS /* CS */
1651 iretq /* continues at repeat_nmi below */
1652 UNWIND_HINT_IRET_REGS
1658 * If there was a nested NMI, the first NMI's iret will return
1659 * here. But NMIs are still enabled and we can take another
1660 * nested NMI. The nested NMI checks the interrupted RIP to see
1661 * if it is between repeat_nmi and end_repeat_nmi, and if so
1662 * it will just return, as we are about to repeat an NMI anyway.
1663 * This makes it safe to copy to the stack frame that a nested
1666 * RSP is pointing to "outermost RIP". gsbase is unknown, but, if
1667 * we're repeating an NMI, gsbase has the same value that it had on
1668 * the first iteration. paranoid_entry will load the kernel
1669 * gsbase if needed before we call do_nmi. "NMI executing"
1672 movq $1, 10*8(%rsp) /* Set "NMI executing". */
1675 * Copy the "outermost" frame to the "iret" frame. NMIs that nest
1676 * here must not modify the "iret" frame while we're writing to
1677 * it or it will end up containing garbage.
1687 * Everything below this point can be preempted by a nested NMI.
1688 * If this happens, then the inner NMI will change the "iret"
1689 * frame to point back to repeat_nmi.
1691 pushq $-1 /* ORIG_RAX: no syscall to restart */
1694 * Use paranoid_entry to handle SWAPGS, but no need to use paranoid_exit
1695 * as we should not be calling schedule in NMI context.
1696 * Even with normal interrupts enabled. An NMI should not be
1697 * setting NEED_RESCHED or anything that normal interrupts and
1698 * exceptions might do.
1703 /* paranoidentry do_nmi, 0; without TRACE_IRQS_OFF */
1708 /* Always restore stashed SPEC_CTRL value (see paranoid_entry) */
1709 IBRS_EXIT save_reg=%r15
1711 /* Always restore stashed CR3 value (see paranoid_entry) */
1712 RESTORE_CR3 scratch_reg=%r15 save_reg=%r14
1714 testl %ebx, %ebx /* swapgs needed? */
1722 * Skip orig_ax and the "outermost" frame to point RSP at the "iret"
1723 * at the "iret" frame.
1728 * Clear "NMI executing". Set DF first so that we can easily
1729 * distinguish the remaining code between here and IRET from
1730 * the SYSCALL entry and exit paths.
1732 * We arguably should just inspect RIP instead, but I (Andy) wrote
1733 * this code when I had the misapprehension that Xen PV supported
1734 * NMIs, and Xen PV would break that approach.
1737 movq $0, 5*8(%rsp) /* clear "NMI executing" */
1740 * iretq reads the "iret" frame and exits the NMI stack in a
1741 * single instruction. We are returning to kernel mode, so this
1742 * cannot result in a fault. Similarly, we don't need to worry
1743 * about espfix64 on the way back to kernel mode.
1748 #ifndef CONFIG_IA32_EMULATION
1750 * This handles SYSCALL from 32-bit code. There is no way to program
1751 * MSRs to fully disable 32-bit SYSCALL.
1753 ENTRY(ignore_sysret)
1760 ENTRY(rewind_stack_and_make_dead)
1762 /* Prevent any naive code from trying to unwind to our caller. */
1765 movq PER_CPU_VAR(cpu_current_top_of_stack), %rax
1766 leaq -PTREGS_SIZE(%rax), %rsp
1770 END(rewind_stack_and_make_dead)