1 /* SPDX-License-Identifier: GPL-2.0 */
3 * linux/arch/x86_64/entry.S
5 * Copyright (C) 1991, 1992 Linus Torvalds
6 * Copyright (C) 2000, 2001, 2002 Andi Kleen SuSE Labs
7 * Copyright (C) 2000 Pavel Machek <pavel@suse.cz>
9 * entry.S contains the system-call and fault low-level handling routines.
11 * Some of this is documented in Documentation/x86/entry_64.txt
13 * A note on terminology:
14 * - iret frame: Architecture defined interrupt frame from SS to RIP
15 * at the top of the kernel process stack.
18 * - ENTRY/END: Define functions in the symbol table.
19 * - TRACE_IRQ_*: Trace hardirq state for lock debugging.
20 * - idtentry: Define exception entry points.
22 #include <linux/linkage.h>
23 #include <asm/segment.h>
24 #include <asm/cache.h>
25 #include <asm/errno.h>
26 #include <asm/asm-offsets.h>
28 #include <asm/unistd.h>
29 #include <asm/thread_info.h>
30 #include <asm/hw_irq.h>
31 #include <asm/page_types.h>
32 #include <asm/irqflags.h>
33 #include <asm/paravirt.h>
34 #include <asm/percpu.h>
37 #include <asm/pgtable_types.h>
38 #include <asm/export.h>
39 #include <asm/frame.h>
40 #include <asm/nospec-branch.h>
41 #include <linux/err.h>
46 .section .entry.text, "ax"
48 #ifdef CONFIG_PARAVIRT
49 ENTRY(native_usergs_sysret64)
53 END(native_usergs_sysret64)
54 #endif /* CONFIG_PARAVIRT */
56 .macro TRACE_IRQS_IRETQ
57 #ifdef CONFIG_TRACE_IRQFLAGS
58 btl $9, EFLAGS(%rsp) /* interrupts off? */
66 * When dynamic function tracer is enabled it will add a breakpoint
67 * to all locations that it is about to modify, sync CPUs, update
68 * all the code, sync CPUs, then remove the breakpoints. In this time
69 * if lockdep is enabled, it might jump back into the debug handler
70 * outside the updating of the IST protection. (TRACE_IRQS_ON/OFF).
72 * We need to change the IDT table before calling TRACE_IRQS_ON/OFF to
73 * make sure the stack pointer does not get reset back to the top
74 * of the debug stack, and instead just reuses the current stack.
76 #if defined(CONFIG_DYNAMIC_FTRACE) && defined(CONFIG_TRACE_IRQFLAGS)
78 .macro TRACE_IRQS_OFF_DEBUG
79 call debug_stack_set_zero
81 call debug_stack_reset
84 .macro TRACE_IRQS_ON_DEBUG
85 call debug_stack_set_zero
87 call debug_stack_reset
90 .macro TRACE_IRQS_IRETQ_DEBUG
91 btl $9, EFLAGS(%rsp) /* interrupts off? */
98 # define TRACE_IRQS_OFF_DEBUG TRACE_IRQS_OFF
99 # define TRACE_IRQS_ON_DEBUG TRACE_IRQS_ON
100 # define TRACE_IRQS_IRETQ_DEBUG TRACE_IRQS_IRETQ
104 * 64-bit SYSCALL instruction entry. Up to 6 arguments in registers.
106 * This is the only entry point used for 64-bit system calls. The
107 * hardware interface is reasonably well designed and the register to
108 * argument mapping Linux uses fits well with the registers that are
109 * available when SYSCALL is used.
111 * SYSCALL instructions can be found inlined in libc implementations as
112 * well as some other programs and libraries. There are also a handful
113 * of SYSCALL instructions in the vDSO used, for example, as a
114 * clock_gettimeofday fallback.
116 * 64-bit SYSCALL saves rip to rcx, clears rflags.RF, then saves rflags to r11,
117 * then loads new ss, cs, and rip from previously programmed MSRs.
118 * rflags gets masked by a value from another MSR (so CLD and CLAC
119 * are not needed). SYSCALL does not save anything on the stack
120 * and does not change rsp.
122 * Registers on entry:
123 * rax system call number
125 * r11 saved rflags (note: r11 is callee-clobbered register in C ABI)
129 * r10 arg3 (needs to be moved to rcx to conform to C ABI)
132 * (note: r12-r15, rbp, rbx are callee-preserved in C ABI)
134 * Only called from user space.
136 * When user can change pt_regs->foo always force IRET. That is because
137 * it deals with uncanonical addresses better. SYSRET has trouble
138 * with them due to bugs in both AMD and Intel CPUs.
141 .pushsection .entry_trampoline, "ax"
144 * The code in here gets remapped into cpu_entry_area's trampoline. This means
145 * that the assembler and linker have the wrong idea as to where this code
146 * lives (and, in fact, it's mapped more than once, so it's not even at a
147 * fixed address). So we can't reference any symbols outside the entry
148 * trampoline and expect it to work.
150 * Instead, we carefully abuse %rip-relative addressing.
151 * _entry_trampoline(%rip) refers to the start of the remapped) entry
152 * trampoline. We can thus find cpu_entry_area with this macro:
155 #define CPU_ENTRY_AREA \
156 _entry_trampoline - CPU_ENTRY_AREA_entry_trampoline(%rip)
158 /* The top word of the SYSENTER stack is hot and is usable as scratch space. */
159 #define RSP_SCRATCH CPU_ENTRY_AREA_entry_stack + \
160 SIZEOF_entry_stack - 8 + CPU_ENTRY_AREA
162 ENTRY(entry_SYSCALL_64_trampoline)
166 /* Stash the user RSP. */
167 movq %rsp, RSP_SCRATCH
169 /* Note: using %rsp as a scratch reg. */
170 SWITCH_TO_KERNEL_CR3 scratch_reg=%rsp
172 /* Load the top of the task stack into RSP */
173 movq CPU_ENTRY_AREA_tss + TSS_sp1 + CPU_ENTRY_AREA, %rsp
175 /* Start building the simulated IRET frame. */
176 pushq $__USER_DS /* pt_regs->ss */
177 pushq RSP_SCRATCH /* pt_regs->sp */
178 pushq %r11 /* pt_regs->flags */
179 pushq $__USER_CS /* pt_regs->cs */
180 pushq %rcx /* pt_regs->ip */
183 * x86 lacks a near absolute jump, and we can't jump to the real
184 * entry text with a relative jump. We could push the target
185 * address and then use retq, but this destroys the pipeline on
186 * many CPUs (wasting over 20 cycles on Sandy Bridge). Instead,
187 * spill RDI and restore it in a second-stage trampoline.
190 movq $entry_SYSCALL_64_stage2, %rdi
192 END(entry_SYSCALL_64_trampoline)
196 ENTRY(entry_SYSCALL_64_stage2)
199 jmp entry_SYSCALL_64_after_hwframe
200 END(entry_SYSCALL_64_stage2)
202 ENTRY(entry_SYSCALL_64)
205 * Interrupts are off on entry.
206 * We do not frame this tiny irq-off block with TRACE_IRQS_OFF/ON,
207 * it is too small to ever cause noticeable irq latency.
212 * This path is only taken when PAGE_TABLE_ISOLATION is disabled so it
213 * is not required to switch CR3.
215 movq %rsp, PER_CPU_VAR(rsp_scratch)
216 movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp
218 /* Construct struct pt_regs on stack */
219 pushq $__USER_DS /* pt_regs->ss */
220 pushq PER_CPU_VAR(rsp_scratch) /* pt_regs->sp */
221 pushq %r11 /* pt_regs->flags */
222 pushq $__USER_CS /* pt_regs->cs */
223 pushq %rcx /* pt_regs->ip */
224 GLOBAL(entry_SYSCALL_64_after_hwframe)
225 pushq %rax /* pt_regs->orig_ax */
227 PUSH_AND_CLEAR_REGS rax=$-ENOSYS
234 /* clobbers %rax, make sure it is after saving the syscall nr */
237 call do_syscall_64 /* returns with IRQs disabled */
239 TRACE_IRQS_IRETQ /* we're about to change IF */
242 * Try to use SYSRET instead of IRET if we're returning to
243 * a completely clean 64-bit userspace context. If we're not,
244 * go to the slow exit path.
249 cmpq %rcx, %r11 /* SYSRET requires RCX == RIP */
250 jne swapgs_restore_regs_and_return_to_usermode
253 * On Intel CPUs, SYSRET with non-canonical RCX/RIP will #GP
254 * in kernel space. This essentially lets the user take over
255 * the kernel, since userspace controls RSP.
257 * If width of "canonical tail" ever becomes variable, this will need
258 * to be updated to remain correct on both old and new CPUs.
260 * Change top bits to match most significant bit (47th or 56th bit
261 * depending on paging mode) in the address.
263 shl $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx
264 sar $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx
266 /* If this changed %rcx, it was not canonical */
268 jne swapgs_restore_regs_and_return_to_usermode
270 cmpq $__USER_CS, CS(%rsp) /* CS must match SYSRET */
271 jne swapgs_restore_regs_and_return_to_usermode
274 cmpq %r11, EFLAGS(%rsp) /* R11 == RFLAGS */
275 jne swapgs_restore_regs_and_return_to_usermode
278 * SYSCALL clears RF when it saves RFLAGS in R11 and SYSRET cannot
279 * restore RF properly. If the slowpath sets it for whatever reason, we
280 * need to restore it correctly.
282 * SYSRET can restore TF, but unlike IRET, restoring TF results in a
283 * trap from userspace immediately after SYSRET. This would cause an
284 * infinite loop whenever #DB happens with register state that satisfies
285 * the opportunistic SYSRET conditions. For example, single-stepping
288 * movq $stuck_here, %rcx
293 * would never get past 'stuck_here'.
295 testq $(X86_EFLAGS_RF|X86_EFLAGS_TF), %r11
296 jnz swapgs_restore_regs_and_return_to_usermode
298 /* nothing to check for RSP */
300 cmpq $__USER_DS, SS(%rsp) /* SS must match SYSRET */
301 jne swapgs_restore_regs_and_return_to_usermode
304 * We win! This label is here just for ease of understanding
305 * perf profiles. Nothing jumps here.
307 syscall_return_via_sysret:
312 * Now all regs are restored except RSP and RDI.
313 * Save old stack pointer and switch to trampoline stack.
316 movq PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %rsp
319 pushq RSP-RDI(%rdi) /* RSP */
320 pushq (%rdi) /* RDI */
323 * We are on the trampoline stack. All regs except RDI are live.
324 * We can do future final exit work right here.
326 SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi
331 END(entry_SYSCALL_64)
337 ENTRY(__switch_to_asm)
340 * Save callee-saved registers
341 * This must match the order in inactive_task_frame
352 movq %rsp, TASK_threadsp(%rdi)
353 movq TASK_threadsp(%rsi), %rsp
355 #ifdef CONFIG_CC_STACKPROTECTOR
356 movq TASK_stack_canary(%rsi), %rbx
357 movq %rbx, PER_CPU_VAR(irq_stack_union)+stack_canary_offset
361 * When switching from a shallower to a deeper call stack
362 * the RSB may either underflow or use entries populated
363 * with userspace addresses. On CPUs where those concerns
364 * exist, overwrite the RSB with entries which capture
365 * speculative execution to prevent attack.
367 FILL_RETURN_BUFFER %r12, RSB_CLEAR_LOOPS, X86_FEATURE_RSB_CTXSW
369 /* restore callee-saved registers */
382 * A newly forked process directly context switches into this address.
384 * rax: prev task we switched from
385 * rbx: kernel thread func (NULL for user thread)
386 * r12: kernel thread arg
391 call schedule_tail /* rdi: 'prev' task parameter */
393 testq %rbx, %rbx /* from kernel_thread? */
394 jnz 1f /* kernel threads are uncommon */
399 call syscall_return_slowpath /* returns with IRQs disabled */
400 TRACE_IRQS_ON /* user mode is traced as IRQS on */
401 jmp swapgs_restore_regs_and_return_to_usermode
408 * A kernel thread is allowed to return here after successfully
409 * calling do_execve(). Exit to userspace to complete the execve()
417 * Build the entry stubs with some assembler magic.
418 * We pack 1 stub into every 8-byte block.
421 ENTRY(irq_entries_start)
422 vector=FIRST_EXTERNAL_VECTOR
423 .rept (FIRST_SYSTEM_VECTOR - FIRST_EXTERNAL_VECTOR)
424 UNWIND_HINT_IRET_REGS
425 pushq $(~vector+0x80) /* Note: always in signed byte range */
430 END(irq_entries_start)
432 .macro DEBUG_ENTRY_ASSERT_IRQS_OFF
433 #ifdef CONFIG_DEBUG_ENTRY
436 testl $X86_EFLAGS_IF, %eax
445 * Enters the IRQ stack if we're not already using it. NMI-safe. Clobbers
446 * flags and puts old RSP into old_rsp, and leaves all other GPRs alone.
447 * Requires kernel GSBASE.
449 * The invariant is that, if irq_count != -1, then the IRQ stack is in use.
451 .macro ENTER_IRQ_STACK regs=1 old_rsp
452 DEBUG_ENTRY_ASSERT_IRQS_OFF
456 UNWIND_HINT_REGS base=\old_rsp
459 incl PER_CPU_VAR(irq_count)
460 jnz .Lirq_stack_push_old_rsp_\@
463 * Right now, if we just incremented irq_count to zero, we've
464 * claimed the IRQ stack but we haven't switched to it yet.
466 * If anything is added that can interrupt us here without using IST,
467 * it must be *extremely* careful to limit its stack usage. This
468 * could include kprobes and a hypothetical future IST-less #DB
471 * The OOPS unwinder relies on the word at the top of the IRQ
472 * stack linking back to the previous RSP for the entire time we're
473 * on the IRQ stack. For this to work reliably, we need to write
474 * it before we actually move ourselves to the IRQ stack.
477 movq \old_rsp, PER_CPU_VAR(irq_stack_union + IRQ_STACK_SIZE - 8)
478 movq PER_CPU_VAR(irq_stack_ptr), %rsp
480 #ifdef CONFIG_DEBUG_ENTRY
482 * If the first movq above becomes wrong due to IRQ stack layout
483 * changes, the only way we'll notice is if we try to unwind right
484 * here. Assert that we set up the stack right to catch this type
487 cmpq -8(%rsp), \old_rsp
488 je .Lirq_stack_okay\@
493 .Lirq_stack_push_old_rsp_\@:
497 UNWIND_HINT_REGS indirect=1
502 * Undoes ENTER_IRQ_STACK.
504 .macro LEAVE_IRQ_STACK regs=1
505 DEBUG_ENTRY_ASSERT_IRQS_OFF
506 /* We need to be off the IRQ stack before decrementing irq_count. */
514 * As in ENTER_IRQ_STACK, irq_count == 0, we are still claiming
515 * the irq stack but we're not on it.
518 decl PER_CPU_VAR(irq_count)
522 * Interrupt entry/exit.
524 * Interrupt entry points save only callee clobbered registers in fast path.
526 * Entry runs with interrupts off.
529 /* 0(%rsp): ~(interrupt number) */
530 .macro interrupt func
533 testb $3, CS-ORIG_RAX(%rsp)
536 FENCE_SWAPGS_USER_ENTRY
537 call switch_to_thread_stack
540 FENCE_SWAPGS_KERNEL_ENTRY
549 * IRQ from user mode.
551 * We need to tell lockdep that IRQs are off. We can't do this until
552 * we fix gsbase, and we should do it before enter_from_user_mode
553 * (which can take locks). Since TRACE_IRQS_OFF idempotent,
554 * the simplest way to handle it is to just call it twice if
555 * we enter from user mode. There's no reason to optimize this since
556 * TRACE_IRQS_OFF is a no-op if lockdep is off.
560 CALL_enter_from_user_mode
563 ENTER_IRQ_STACK old_rsp=%rdi
564 /* We entered an interrupt context - irqs are off: */
567 call \func /* rdi points to pt_regs */
571 * The interrupt stubs push (~vector+0x80) onto the stack and
572 * then jump to common_interrupt.
574 .p2align CONFIG_X86_L1_CACHE_SHIFT
577 addq $-0x80, (%rsp) /* Adjust vector to [-256, -1] range */
579 /* 0(%rsp): old RSP */
581 DISABLE_INTERRUPTS(CLBR_ANY)
589 /* Interrupt came from user space */
592 call prepare_exit_to_usermode
595 GLOBAL(swapgs_restore_regs_and_return_to_usermode)
597 #ifdef CONFIG_DEBUG_ENTRY
598 /* Assert that pt_regs indicates user mode. */
607 * The stack is now user RDI, orig_ax, RIP, CS, EFLAGS, RSP, SS.
608 * Save old stack pointer and switch to trampoline stack.
611 movq PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %rsp
614 /* Copy the IRET frame to the trampoline stack. */
615 pushq 6*8(%rdi) /* SS */
616 pushq 5*8(%rdi) /* RSP */
617 pushq 4*8(%rdi) /* EFLAGS */
618 pushq 3*8(%rdi) /* CS */
619 pushq 2*8(%rdi) /* RIP */
621 /* Push user RDI on the trampoline stack. */
625 * We are on the trampoline stack. All regs except RDI are live.
626 * We can do future final exit work right here.
629 SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi
637 /* Returning to kernel space */
639 #ifdef CONFIG_PREEMPT
640 /* Interrupts are off */
641 /* Check if we need preemption */
642 btl $9, EFLAGS(%rsp) /* were interrupts off? */
644 0: cmpl $0, PER_CPU_VAR(__preempt_count)
646 call preempt_schedule_irq
651 * The iretq could re-enable interrupts:
655 GLOBAL(restore_regs_and_return_to_kernel)
656 #ifdef CONFIG_DEBUG_ENTRY
657 /* Assert that pt_regs indicates kernel mode. */
664 addq $8, %rsp /* skip regs->orig_ax */
668 UNWIND_HINT_IRET_REGS
670 * Are we returning to a stack segment from the LDT? Note: in
671 * 64-bit mode SS:RSP on the exception stack is always valid.
673 #ifdef CONFIG_X86_ESPFIX64
674 testb $4, (SS-RIP)(%rsp)
675 jnz native_irq_return_ldt
678 .global native_irq_return_iret
679 native_irq_return_iret:
681 * This may fault. Non-paranoid faults on return to userspace are
682 * handled by fixup_bad_iret. These include #SS, #GP, and #NP.
683 * Double-faults due to espfix64 are handled in do_double_fault.
684 * Other faults here are fatal.
688 #ifdef CONFIG_X86_ESPFIX64
689 native_irq_return_ldt:
691 * We are running with user GSBASE. All GPRs contain their user
692 * values. We have a percpu ESPFIX stack that is eight slots
693 * long (see ESPFIX_STACK_SIZE). espfix_waddr points to the bottom
694 * of the ESPFIX stack.
696 * We clobber RAX and RDI in this code. We stash RDI on the
697 * normal stack and RAX on the ESPFIX stack.
699 * The ESPFIX stack layout we set up looks like this:
701 * --- top of ESPFIX stack ---
706 * RIP <-- RSP points here when we're done
707 * RAX <-- espfix_waddr points here
708 * --- bottom of ESPFIX stack ---
711 pushq %rdi /* Stash user RDI */
712 SWAPGS /* to kernel GS */
713 SWITCH_TO_KERNEL_CR3 scratch_reg=%rdi /* to kernel CR3 */
715 movq PER_CPU_VAR(espfix_waddr), %rdi
716 movq %rax, (0*8)(%rdi) /* user RAX */
717 movq (1*8)(%rsp), %rax /* user RIP */
718 movq %rax, (1*8)(%rdi)
719 movq (2*8)(%rsp), %rax /* user CS */
720 movq %rax, (2*8)(%rdi)
721 movq (3*8)(%rsp), %rax /* user RFLAGS */
722 movq %rax, (3*8)(%rdi)
723 movq (5*8)(%rsp), %rax /* user SS */
724 movq %rax, (5*8)(%rdi)
725 movq (4*8)(%rsp), %rax /* user RSP */
726 movq %rax, (4*8)(%rdi)
727 /* Now RAX == RSP. */
729 andl $0xffff0000, %eax /* RAX = (RSP & 0xffff0000) */
732 * espfix_stack[31:16] == 0. The page tables are set up such that
733 * (espfix_stack | (X & 0xffff0000)) points to a read-only alias of
734 * espfix_waddr for any X. That is, there are 65536 RO aliases of
735 * the same page. Set up RSP so that RSP[31:16] contains the
736 * respective 16 bits of the /userspace/ RSP and RSP nonetheless
737 * still points to an RO alias of the ESPFIX stack.
739 orq PER_CPU_VAR(espfix_stack), %rax
741 SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi
742 SWAPGS /* to user GS */
743 popq %rdi /* Restore user RDI */
746 UNWIND_HINT_IRET_REGS offset=8
749 * At this point, we cannot write to the stack any more, but we can
752 popq %rax /* Restore user RAX */
755 * RSP now points to an ordinary IRET frame, except that the page
756 * is read-only and RSP[31:16] are preloaded with the userspace
757 * values. We can now IRET back to userspace.
759 jmp native_irq_return_iret
761 END(common_interrupt)
766 .macro apicinterrupt3 num sym do_sym
768 UNWIND_HINT_IRET_REGS
777 /* Make sure APIC interrupt handlers end up in the irqentry section: */
778 #define PUSH_SECTION_IRQENTRY .pushsection .irqentry.text, "ax"
779 #define POP_SECTION_IRQENTRY .popsection
781 .macro apicinterrupt num sym do_sym
782 PUSH_SECTION_IRQENTRY
783 apicinterrupt3 \num \sym \do_sym
788 apicinterrupt3 IRQ_MOVE_CLEANUP_VECTOR irq_move_cleanup_interrupt smp_irq_move_cleanup_interrupt
789 apicinterrupt3 REBOOT_VECTOR reboot_interrupt smp_reboot_interrupt
793 apicinterrupt3 UV_BAU_MESSAGE uv_bau_message_intr1 uv_bau_message_interrupt
796 apicinterrupt LOCAL_TIMER_VECTOR apic_timer_interrupt smp_apic_timer_interrupt
797 apicinterrupt X86_PLATFORM_IPI_VECTOR x86_platform_ipi smp_x86_platform_ipi
799 #ifdef CONFIG_HAVE_KVM
800 apicinterrupt3 POSTED_INTR_VECTOR kvm_posted_intr_ipi smp_kvm_posted_intr_ipi
801 apicinterrupt3 POSTED_INTR_WAKEUP_VECTOR kvm_posted_intr_wakeup_ipi smp_kvm_posted_intr_wakeup_ipi
802 apicinterrupt3 POSTED_INTR_NESTED_VECTOR kvm_posted_intr_nested_ipi smp_kvm_posted_intr_nested_ipi
805 #ifdef CONFIG_X86_MCE_THRESHOLD
806 apicinterrupt THRESHOLD_APIC_VECTOR threshold_interrupt smp_threshold_interrupt
809 #ifdef CONFIG_X86_MCE_AMD
810 apicinterrupt DEFERRED_ERROR_VECTOR deferred_error_interrupt smp_deferred_error_interrupt
813 #ifdef CONFIG_X86_THERMAL_VECTOR
814 apicinterrupt THERMAL_APIC_VECTOR thermal_interrupt smp_thermal_interrupt
818 apicinterrupt CALL_FUNCTION_SINGLE_VECTOR call_function_single_interrupt smp_call_function_single_interrupt
819 apicinterrupt CALL_FUNCTION_VECTOR call_function_interrupt smp_call_function_interrupt
820 apicinterrupt RESCHEDULE_VECTOR reschedule_interrupt smp_reschedule_interrupt
823 apicinterrupt ERROR_APIC_VECTOR error_interrupt smp_error_interrupt
824 apicinterrupt SPURIOUS_APIC_VECTOR spurious_interrupt smp_spurious_interrupt
826 #ifdef CONFIG_IRQ_WORK
827 apicinterrupt IRQ_WORK_VECTOR irq_work_interrupt smp_irq_work_interrupt
831 * Exception entry points.
833 #define CPU_TSS_IST(x) PER_CPU_VAR(cpu_tss_rw) + (TSS_ist + ((x) - 1) * 8)
836 * Switch to the thread stack. This is called with the IRET frame and
837 * orig_ax on the stack. (That is, RDI..R12 are not on the stack and
838 * space has not been allocated for them.)
840 ENTRY(switch_to_thread_stack)
844 /* Need to switch before accessing the thread stack. */
845 SWITCH_TO_KERNEL_CR3 scratch_reg=%rdi
847 movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp
848 UNWIND_HINT sp_offset=16 sp_reg=ORC_REG_DI
850 pushq 7*8(%rdi) /* regs->ss */
851 pushq 6*8(%rdi) /* regs->rsp */
852 pushq 5*8(%rdi) /* regs->eflags */
853 pushq 4*8(%rdi) /* regs->cs */
854 pushq 3*8(%rdi) /* regs->ip */
855 pushq 2*8(%rdi) /* regs->orig_ax */
856 pushq 8(%rdi) /* return address */
861 END(switch_to_thread_stack)
863 .macro idtentry sym do_sym has_error_code:req paranoid=0 shift_ist=-1 create_gap=0
865 UNWIND_HINT_IRET_REGS offset=\has_error_code*8
868 .if \shift_ist != -1 && \paranoid == 0
869 .error "using shift_ist requires paranoid=1"
874 .if \has_error_code == 0
875 pushq $-1 /* ORIG_RAX: no syscall to restart */
879 testb $3, CS-ORIG_RAX(%rsp) /* If coming from userspace, switch stacks */
880 jnz .Lfrom_usermode_switch_stack_\@
885 * If coming from kernel space, create a 6-word gap to allow the
886 * int3 handler to emulate a call instruction.
888 testb $3, CS-ORIG_RAX(%rsp)
889 jnz .Lfrom_usermode_no_gap_\@
893 UNWIND_HINT_IRET_REGS offset=8
894 .Lfrom_usermode_no_gap_\@:
903 /* returned flag: ebx=0: need swapgs on exit, ebx=1: don't need it */
907 TRACE_IRQS_OFF_DEBUG /* reload IDT in case of recursion */
913 movq %rsp, %rdi /* pt_regs pointer */
916 movq ORIG_RAX(%rsp), %rsi /* get error code */
917 movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */
919 xorl %esi, %esi /* no error code */
923 subq $EXCEPTION_STKSZ, CPU_TSS_IST(\shift_ist)
929 addq $EXCEPTION_STKSZ, CPU_TSS_IST(\shift_ist)
932 /* these procedures expect "no swapgs" flag in ebx */
941 * Entry from userspace. Switch stacks and treat it
942 * as a normal entry. This means that paranoid handlers
943 * run in real process context if user_mode(regs).
945 .Lfrom_usermode_switch_stack_\@:
948 movq %rsp, %rdi /* pt_regs pointer */
951 movq ORIG_RAX(%rsp), %rsi /* get error code */
952 movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */
954 xorl %esi, %esi /* no error code */
964 idtentry divide_error do_divide_error has_error_code=0
965 idtentry overflow do_overflow has_error_code=0
966 idtentry bounds do_bounds has_error_code=0
967 idtentry invalid_op do_invalid_op has_error_code=0
968 idtentry device_not_available do_device_not_available has_error_code=0
969 idtentry double_fault do_double_fault has_error_code=1 paranoid=2
970 idtentry coprocessor_segment_overrun do_coprocessor_segment_overrun has_error_code=0
971 idtentry invalid_TSS do_invalid_TSS has_error_code=1
972 idtentry segment_not_present do_segment_not_present has_error_code=1
973 idtentry spurious_interrupt_bug do_spurious_interrupt_bug has_error_code=0
974 idtentry coprocessor_error do_coprocessor_error has_error_code=0
975 idtentry alignment_check do_alignment_check has_error_code=1
976 idtentry simd_coprocessor_error do_simd_coprocessor_error has_error_code=0
980 * Reload gs selector with exception handling
983 ENTRY(native_load_gs_index)
986 DISABLE_INTERRUPTS(CLBR_ANY & ~CLBR_RDI)
990 2: ALTERNATIVE "", "mfence", X86_BUG_SWAPGS_FENCE
995 ENDPROC(native_load_gs_index)
996 EXPORT_SYMBOL(native_load_gs_index)
998 _ASM_EXTABLE(.Lgs_change, bad_gs)
999 .section .fixup, "ax"
1000 /* running with kernelgs */
1002 SWAPGS /* switch back to user gs */
1004 /* This can't be a string because the preprocessor needs to see it. */
1005 movl $__USER_DS, %eax
1008 ALTERNATIVE "", "ZAP_GS", X86_BUG_NULL_SEG
1014 /* Call softirq on interrupt stack. Interrupts are off. */
1015 ENTRY(do_softirq_own_stack)
1018 ENTER_IRQ_STACK regs=0 old_rsp=%r11
1020 LEAVE_IRQ_STACK regs=0
1023 ENDPROC(do_softirq_own_stack)
1026 idtentry hypervisor_callback xen_do_hypervisor_callback has_error_code=0
1029 * A note on the "critical region" in our callback handler.
1030 * We want to avoid stacking callback handlers due to events occurring
1031 * during handling of the last event. To do this, we keep events disabled
1032 * until we've done all processing. HOWEVER, we must enable events before
1033 * popping the stack frame (can't be done atomically) and so it would still
1034 * be possible to get enough handler activations to overflow the stack.
1035 * Although unlikely, bugs of that kind are hard to track down, so we'd
1036 * like to avoid the possibility.
1037 * So, on entry to the handler we detect whether we interrupted an
1038 * existing activation in its critical region -- if so, we pop the current
1039 * activation and restart the handler using the previous one.
1041 ENTRY(xen_do_hypervisor_callback) /* do_hypervisor_callback(struct *pt_regs) */
1044 * Since we don't modify %rdi, evtchn_do_upall(struct *pt_regs) will
1045 * see the correct pointer to the pt_regs
1048 movq %rdi, %rsp /* we don't return, adjust the stack frame */
1051 ENTER_IRQ_STACK old_rsp=%r10
1052 call xen_evtchn_do_upcall
1055 #ifndef CONFIG_PREEMPT
1056 call xen_maybe_preempt_hcall
1059 END(xen_do_hypervisor_callback)
1062 * Hypervisor uses this for application faults while it executes.
1063 * We get here for two reasons:
1064 * 1. Fault while reloading DS, ES, FS or GS
1065 * 2. Fault while executing IRET
1066 * Category 1 we do not need to fix up as Xen has already reloaded all segment
1067 * registers that could be reloaded and zeroed the others.
1068 * Category 2 we fix up by killing the current process. We cannot use the
1069 * normal Linux return path in this case because if we use the IRET hypercall
1070 * to pop the stack frame we end up in an infinite loop of failsafe callbacks.
1071 * We distinguish between categories by comparing each saved segment register
1072 * with its current contents: any discrepancy means we in category 1.
1074 ENTRY(xen_failsafe_callback)
1077 cmpw %cx, 0x10(%rsp)
1080 cmpw %cx, 0x18(%rsp)
1083 cmpw %cx, 0x20(%rsp)
1086 cmpw %cx, 0x28(%rsp)
1088 /* All segments match their saved values => Category 2 (Bad IRET). */
1093 UNWIND_HINT_IRET_REGS offset=8
1094 jmp general_protection
1095 1: /* Segment mismatch => Category 1 (Bad segment). Retry the IRET. */
1099 UNWIND_HINT_IRET_REGS
1100 pushq $-1 /* orig_ax = -1 => not a system call */
1102 ENCODE_FRAME_POINTER
1104 END(xen_failsafe_callback)
1106 apicinterrupt3 HYPERVISOR_CALLBACK_VECTOR \
1107 xen_hvm_callback_vector xen_evtchn_do_upcall
1109 #endif /* CONFIG_XEN */
1111 #if IS_ENABLED(CONFIG_HYPERV)
1112 apicinterrupt3 HYPERVISOR_CALLBACK_VECTOR \
1113 hyperv_callback_vector hyperv_vector_handler
1114 #endif /* CONFIG_HYPERV */
1116 idtentry debug do_debug has_error_code=0 paranoid=1 shift_ist=DEBUG_STACK
1117 idtentry int3 do_int3 has_error_code=0 create_gap=1
1118 idtentry stack_segment do_stack_segment has_error_code=1
1121 idtentry xennmi do_nmi has_error_code=0
1122 idtentry xendebug do_debug has_error_code=0
1125 idtentry general_protection do_general_protection has_error_code=1
1126 idtentry page_fault do_page_fault has_error_code=1
1128 #ifdef CONFIG_KVM_GUEST
1129 idtentry async_page_fault do_async_page_fault has_error_code=1
1132 #ifdef CONFIG_X86_MCE
1133 idtentry machine_check do_mce has_error_code=0 paranoid=1
1137 * Save all registers in pt_regs, and switch gs if needed.
1138 * Use slow, but surefire "are we in kernel?" check.
1139 * Return: ebx=0: need swapgs on exit, ebx=1: otherwise
1142 * R15 - old SPEC_CTRL
1144 ENTRY(paranoid_entry)
1147 PUSH_AND_CLEAR_REGS save_ret=1
1148 ENCODE_FRAME_POINTER 8
1150 movl $MSR_GS_BASE, %ecx
1153 js 1f /* negative -> in kernel */
1158 SAVE_AND_SWITCH_TO_KERNEL_CR3 scratch_reg=%rax save_reg=%r14
1160 * The above SAVE_AND_SWITCH_TO_KERNEL_CR3 macro doesn't do an
1161 * unconditional CR3 write, even in the PTI case. So do an lfence
1162 * to prevent GS speculation, regardless of whether PTI is enabled.
1164 FENCE_SWAPGS_KERNEL_ENTRY
1167 * Once we have CR3 and %GS setup save and set SPEC_CTRL. Just like
1168 * CR3 above, keep the old value in a callee saved register.
1170 IBRS_ENTER save_reg=%r15
1176 * "Paranoid" exit path from exception stack. This is invoked
1177 * only on return from non-NMI IST interrupts that came
1178 * from kernel space.
1180 * We may be returning to very strange contexts (e.g. very early
1181 * in syscall entry), so checking for preemption here would
1182 * be complicated. Fortunately, we there's no good reason
1183 * to try to handle preemption here.
1185 * On entry, ebx is "no swapgs" flag (1: don't need swapgs, 0: need it)
1188 * R15 - old SPEC_CTRL
1190 ENTRY(paranoid_exit)
1194 * Must restore IBRS state before both CR3 and %GS since we need access
1195 * to the per-CPU x86_spec_ctrl_shadow variable.
1197 IBRS_EXIT save_reg=%r15
1199 DISABLE_INTERRUPTS(CLBR_ANY)
1200 TRACE_IRQS_OFF_DEBUG
1201 testl %ebx, %ebx /* swapgs needed? */
1202 jnz .Lparanoid_exit_no_swapgs
1204 RESTORE_CR3 scratch_reg=%rbx save_reg=%r14
1206 jmp .Lparanoid_exit_restore
1207 .Lparanoid_exit_no_swapgs:
1208 TRACE_IRQS_IRETQ_DEBUG
1209 RESTORE_CR3 scratch_reg=%rbx save_reg=%r14
1210 .Lparanoid_exit_restore:
1211 jmp restore_regs_and_return_to_kernel
1215 * Save all registers in pt_regs, and switch GS if needed.
1220 PUSH_AND_CLEAR_REGS save_ret=1
1221 ENCODE_FRAME_POINTER 8
1222 testb $3, CS+8(%rsp)
1223 jz .Lerror_kernelspace
1226 * We entered from user mode or we're pretending to have entered
1227 * from user mode due to an IRET fault.
1230 FENCE_SWAPGS_USER_ENTRY
1231 /* We have user CR3. Change to kernel CR3. */
1232 SWITCH_TO_KERNEL_CR3 scratch_reg=%rax
1235 .Lerror_entry_from_usermode_after_swapgs:
1237 /* Put us onto the real thread stack. */
1238 popq %r12 /* save return addr in %12 */
1239 movq %rsp, %rdi /* arg0 = pt_regs pointer */
1241 movq %rax, %rsp /* switch stack */
1242 ENCODE_FRAME_POINTER
1246 * We need to tell lockdep that IRQs are off. We can't do this until
1247 * we fix gsbase, and we should do it before enter_from_user_mode
1248 * (which can take locks).
1251 CALL_enter_from_user_mode
1254 .Lerror_entry_done_lfence:
1255 FENCE_SWAPGS_KERNEL_ENTRY
1261 * There are two places in the kernel that can potentially fault with
1262 * usergs. Handle them here. B stepping K8s sometimes report a
1263 * truncated RIP for IRET exceptions returning to compat mode. Check
1264 * for these here too.
1266 .Lerror_kernelspace:
1267 leaq native_irq_return_iret(%rip), %rcx
1268 cmpq %rcx, RIP+8(%rsp)
1270 movl %ecx, %eax /* zero extend */
1271 cmpq %rax, RIP+8(%rsp)
1273 cmpq $.Lgs_change, RIP+8(%rsp)
1274 jne .Lerror_entry_done_lfence
1277 * hack: .Lgs_change can fail with user gsbase. If this happens, fix up
1278 * gsbase and proceed. We'll fix up the exception and land in
1279 * .Lgs_change's error handler with kernel gsbase.
1282 FENCE_SWAPGS_USER_ENTRY
1283 SWITCH_TO_KERNEL_CR3 scratch_reg=%rax
1284 jmp .Lerror_entry_done
1287 /* Fix truncated RIP */
1288 movq %rcx, RIP+8(%rsp)
1293 * We came from an IRET to user mode, so we have user
1294 * gsbase and CR3. Switch to kernel gsbase and CR3:
1297 FENCE_SWAPGS_USER_ENTRY
1298 SWITCH_TO_KERNEL_CR3 scratch_reg=%rax
1302 * Pretend that the exception came from user mode: set up pt_regs
1303 * as if we faulted immediately after IRET.
1308 jmp .Lerror_entry_from_usermode_after_swapgs
1313 DISABLE_INTERRUPTS(CLBR_ANY)
1321 * Runs on exception stack. Xen PV does not go through this path at all,
1322 * so we can use real assembly here.
1325 * %r14: Used to save/restore the CR3 of the interrupted context
1326 * when PAGE_TABLE_ISOLATION is in use. Do not clobber.
1329 UNWIND_HINT_IRET_REGS
1332 * We allow breakpoints in NMIs. If a breakpoint occurs, then
1333 * the iretq it performs will take us out of NMI context.
1334 * This means that we can have nested NMIs where the next
1335 * NMI is using the top of the stack of the previous NMI. We
1336 * can't let it execute because the nested NMI will corrupt the
1337 * stack of the previous NMI. NMI handlers are not re-entrant
1340 * To handle this case we do the following:
1341 * Check the a special location on the stack that contains
1342 * a variable that is set when NMIs are executing.
1343 * The interrupted task's stack is also checked to see if it
1345 * If the variable is not set and the stack is not the NMI
1347 * o Set the special variable on the stack
1348 * o Copy the interrupt frame into an "outermost" location on the
1350 * o Copy the interrupt frame into an "iret" location on the stack
1351 * o Continue processing the NMI
1352 * If the variable is set or the previous stack is the NMI stack:
1353 * o Modify the "iret" location to jump to the repeat_nmi
1354 * o return back to the first NMI
1356 * Now on exit of the first NMI, we first clear the stack variable
1357 * The NMI stack will tell any nested NMIs at that point that it is
1358 * nested. Then we pop the stack normally with iret, and if there was
1359 * a nested NMI that updated the copy interrupt stack frame, a
1360 * jump will be made to the repeat_nmi code that will handle the second
1363 * However, espfix prevents us from directly returning to userspace
1364 * with a single IRET instruction. Similarly, IRET to user mode
1365 * can fault. We therefore handle NMIs from user space like
1366 * other IST entries.
1371 /* Use %rdx as our temp variable throughout */
1374 testb $3, CS-RIP+8(%rsp)
1375 jz .Lnmi_from_kernel
1378 * NMI from user mode. We need to run on the thread stack, but we
1379 * can't go through the normal entry paths: NMIs are masked, and
1380 * we don't want to enable interrupts, because then we'll end
1381 * up in an awkward situation in which IRQs are on but NMIs
1384 * We also must not push anything to the stack before switching
1385 * stacks lest we corrupt the "NMI executing" variable.
1390 FENCE_SWAPGS_USER_ENTRY
1391 SWITCH_TO_KERNEL_CR3 scratch_reg=%rdx
1393 movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp
1394 UNWIND_HINT_IRET_REGS base=%rdx offset=8
1395 pushq 5*8(%rdx) /* pt_regs->ss */
1396 pushq 4*8(%rdx) /* pt_regs->rsp */
1397 pushq 3*8(%rdx) /* pt_regs->flags */
1398 pushq 2*8(%rdx) /* pt_regs->cs */
1399 pushq 1*8(%rdx) /* pt_regs->rip */
1400 UNWIND_HINT_IRET_REGS
1401 pushq $-1 /* pt_regs->orig_ax */
1402 PUSH_AND_CLEAR_REGS rdx=(%rdx)
1403 ENCODE_FRAME_POINTER
1408 * At this point we no longer need to worry about stack damage
1409 * due to nesting -- we're on the normal thread stack and we're
1410 * done with the NMI stack.
1418 * Return back to user mode. We must *not* do the normal exit
1419 * work, because we don't want to enable interrupts.
1421 jmp swapgs_restore_regs_and_return_to_usermode
1425 * Here's what our stack frame will look like:
1426 * +---------------------------------------------------------+
1428 * | original Return RSP |
1429 * | original RFLAGS |
1432 * +---------------------------------------------------------+
1433 * | temp storage for rdx |
1434 * +---------------------------------------------------------+
1435 * | "NMI executing" variable |
1436 * +---------------------------------------------------------+
1437 * | iret SS } Copied from "outermost" frame |
1438 * | iret Return RSP } on each loop iteration; overwritten |
1439 * | iret RFLAGS } by a nested NMI to force another |
1440 * | iret CS } iteration if needed. |
1442 * +---------------------------------------------------------+
1443 * | outermost SS } initialized in first_nmi; |
1444 * | outermost Return RSP } will not be changed before |
1445 * | outermost RFLAGS } NMI processing is done. |
1446 * | outermost CS } Copied to "iret" frame on each |
1447 * | outermost RIP } iteration. |
1448 * +---------------------------------------------------------+
1450 * +---------------------------------------------------------+
1452 * The "original" frame is used by hardware. Before re-enabling
1453 * NMIs, we need to be done with it, and we need to leave enough
1454 * space for the asm code here.
1456 * We return by executing IRET while RSP points to the "iret" frame.
1457 * That will either return for real or it will loop back into NMI
1460 * The "outermost" frame is copied to the "iret" frame on each
1461 * iteration of the loop, so each iteration starts with the "iret"
1462 * frame pointing to the final return target.
1466 * Determine whether we're a nested NMI.
1468 * If we interrupted kernel code between repeat_nmi and
1469 * end_repeat_nmi, then we are a nested NMI. We must not
1470 * modify the "iret" frame because it's being written by
1471 * the outer NMI. That's okay; the outer NMI handler is
1472 * about to about to call do_nmi anyway, so we can just
1473 * resume the outer NMI.
1476 movq $repeat_nmi, %rdx
1479 movq $end_repeat_nmi, %rdx
1485 * Now check "NMI executing". If it's set, then we're nested.
1486 * This will not detect if we interrupted an outer NMI just
1493 * Now test if the previous stack was an NMI stack. This covers
1494 * the case where we interrupt an outer NMI after it clears
1495 * "NMI executing" but before IRET. We need to be careful, though:
1496 * there is one case in which RSP could point to the NMI stack
1497 * despite there being no NMI active: naughty userspace controls
1498 * RSP at the very beginning of the SYSCALL targets. We can
1499 * pull a fast one on naughty userspace, though: we program
1500 * SYSCALL to mask DF, so userspace cannot cause DF to be set
1501 * if it controls the kernel's RSP. We set DF before we clear
1505 /* Compare the NMI stack (rdx) with the stack we came from (4*8(%rsp)) */
1506 cmpq %rdx, 4*8(%rsp)
1507 /* If the stack pointer is above the NMI stack, this is a normal NMI */
1510 subq $EXCEPTION_STKSZ, %rdx
1511 cmpq %rdx, 4*8(%rsp)
1512 /* If it is below the NMI stack, it is a normal NMI */
1515 /* Ah, it is within the NMI stack. */
1517 testb $(X86_EFLAGS_DF >> 8), (3*8 + 1)(%rsp)
1518 jz first_nmi /* RSP was user controlled. */
1520 /* This is a nested NMI. */
1524 * Modify the "iret" frame to point to repeat_nmi, forcing another
1525 * iteration of NMI handling.
1528 leaq -10*8(%rsp), %rdx
1535 /* Put stack back */
1541 /* We are returning to kernel mode, so this cannot result in a fault. */
1548 /* Make room for "NMI executing". */
1551 /* Leave room for the "iret" frame */
1554 /* Copy the "original" frame to the "outermost" frame */
1558 UNWIND_HINT_IRET_REGS
1560 /* Everything up to here is safe from nested NMIs */
1562 #ifdef CONFIG_DEBUG_ENTRY
1564 * For ease of testing, unmask NMIs right away. Disabled by
1565 * default because IRET is very expensive.
1568 pushq %rsp /* RSP (minus 8 because of the previous push) */
1569 addq $8, (%rsp) /* Fix up RSP */
1571 pushq $__KERNEL_CS /* CS */
1573 iretq /* continues at repeat_nmi below */
1574 UNWIND_HINT_IRET_REGS
1580 * If there was a nested NMI, the first NMI's iret will return
1581 * here. But NMIs are still enabled and we can take another
1582 * nested NMI. The nested NMI checks the interrupted RIP to see
1583 * if it is between repeat_nmi and end_repeat_nmi, and if so
1584 * it will just return, as we are about to repeat an NMI anyway.
1585 * This makes it safe to copy to the stack frame that a nested
1588 * RSP is pointing to "outermost RIP". gsbase is unknown, but, if
1589 * we're repeating an NMI, gsbase has the same value that it had on
1590 * the first iteration. paranoid_entry will load the kernel
1591 * gsbase if needed before we call do_nmi. "NMI executing"
1594 movq $1, 10*8(%rsp) /* Set "NMI executing". */
1597 * Copy the "outermost" frame to the "iret" frame. NMIs that nest
1598 * here must not modify the "iret" frame while we're writing to
1599 * it or it will end up containing garbage.
1609 * Everything below this point can be preempted by a nested NMI.
1610 * If this happens, then the inner NMI will change the "iret"
1611 * frame to point back to repeat_nmi.
1613 pushq $-1 /* ORIG_RAX: no syscall to restart */
1616 * Use paranoid_entry to handle SWAPGS, but no need to use paranoid_exit
1617 * as we should not be calling schedule in NMI context.
1618 * Even with normal interrupts enabled. An NMI should not be
1619 * setting NEED_RESCHED or anything that normal interrupts and
1620 * exceptions might do.
1625 /* paranoidentry do_nmi, 0; without TRACE_IRQS_OFF */
1630 /* Always restore stashed SPEC_CTRL value (see paranoid_entry) */
1631 IBRS_EXIT save_reg=%r15
1633 RESTORE_CR3 scratch_reg=%r15 save_reg=%r14
1635 testl %ebx, %ebx /* swapgs needed? */
1643 * Skip orig_ax and the "outermost" frame to point RSP at the "iret"
1644 * at the "iret" frame.
1649 * Clear "NMI executing". Set DF first so that we can easily
1650 * distinguish the remaining code between here and IRET from
1651 * the SYSCALL entry and exit paths.
1653 * We arguably should just inspect RIP instead, but I (Andy) wrote
1654 * this code when I had the misapprehension that Xen PV supported
1655 * NMIs, and Xen PV would break that approach.
1658 movq $0, 5*8(%rsp) /* clear "NMI executing" */
1661 * iretq reads the "iret" frame and exits the NMI stack in a
1662 * single instruction. We are returning to kernel mode, so this
1663 * cannot result in a fault. Similarly, we don't need to worry
1664 * about espfix64 on the way back to kernel mode.
1669 ENTRY(ignore_sysret)
1675 ENTRY(rewind_stack_and_make_dead)
1677 /* Prevent any naive code from trying to unwind to our caller. */
1680 movq PER_CPU_VAR(cpu_current_top_of_stack), %rax
1681 leaq -PTREGS_SIZE(%rax), %rsp
1685 END(rewind_stack_and_make_dead)