1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 1991,1992 Linus Torvalds
5 * entry_32.S contains the system-call and low-level fault and trap handling routines.
7 * Stack layout while running C code:
8 * ptrace needs to have all registers on the stack.
9 * If the order here is changed, it needs to be
10 * updated in fork.c:copy_process(), signal.c:do_signal(),
11 * ptrace.c and ptrace.h
23 * 28(%esp) - %gs saved iff !CONFIG_X86_32_LAZY_GS
32 #include <linux/linkage.h>
33 #include <linux/err.h>
34 #include <asm/thread_info.h>
35 #include <asm/irqflags.h>
36 #include <asm/errno.h>
37 #include <asm/segment.h>
39 #include <asm/percpu.h>
40 #include <asm/processor-flags.h>
41 #include <asm/irq_vectors.h>
42 #include <asm/cpufeatures.h>
43 #include <asm/alternative-asm.h>
46 #include <asm/frame.h>
47 #include <asm/nospec-branch.h>
51 .section .entry.text, "ax"
54 * We use macros for low-level operations which need to be overridden
55 * for paravirtualization. The following will never clobber any registers:
56 * INTERRUPT_RETURN (aka. "iret")
57 * GET_CR0_INTO_EAX (aka. "movl %cr0, %eax")
58 * ENABLE_INTERRUPTS_SYSEXIT (aka "sti; sysexit").
60 * For DISABLE_INTERRUPTS/ENABLE_INTERRUPTS (aka "cli"/"sti"), you must
61 * specify what registers can be overwritten (CLBR_NONE, CLBR_EAX/EDX/ECX/ANY).
62 * Allowing a register to be clobbered can shrink the paravirt replacement
63 * enough to patch inline, increasing performance.
66 #ifdef CONFIG_PREEMPTION
67 # define preempt_stop(clobbers) DISABLE_INTERRUPTS(clobbers); TRACE_IRQS_OFF
69 # define preempt_stop(clobbers)
72 .macro TRACE_IRQS_IRET
73 #ifdef CONFIG_TRACE_IRQFLAGS
74 testl $X86_EFLAGS_IF, PT_EFLAGS(%esp) # interrupts off?
81 #define PTI_SWITCH_MASK (1 << PAGE_SHIFT)
84 * User gs save/restore
86 * %gs is used for userland TLS and kernel only uses it for stack
87 * canary which is required to be at %gs:20 by gcc. Read the comment
88 * at the top of stackprotector.h for more info.
90 * Local labels 98 and 99 are used.
92 #ifdef CONFIG_X86_32_LAZY_GS
94 /* unfortunately push/pop can't be no-op */
99 addl $(4 + \pop), %esp
104 /* all the rest are no-op */
111 .macro REG_TO_PTGS reg
113 .macro SET_KERNEL_GS reg
116 #else /* CONFIG_X86_32_LAZY_GS */
129 .pushsection .fixup, "ax"
133 _ASM_EXTABLE(98b, 99b)
137 98: mov PT_GS(%esp), %gs
140 .pushsection .fixup, "ax"
141 99: movl $0, PT_GS(%esp)
144 _ASM_EXTABLE(98b, 99b)
150 .macro REG_TO_PTGS reg
151 movl \reg, PT_GS(%esp)
153 .macro SET_KERNEL_GS reg
154 movl $(__KERNEL_STACK_CANARY), \reg
158 #endif /* CONFIG_X86_32_LAZY_GS */
160 /* Unconditionally switch to user cr3 */
161 .macro SWITCH_TO_USER_CR3 scratch_reg:req
162 ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI
164 movl %cr3, \scratch_reg
165 orl $PTI_SWITCH_MASK, \scratch_reg
166 movl \scratch_reg, %cr3
170 .macro BUG_IF_WRONG_CR3 no_user_check=0
171 #ifdef CONFIG_DEBUG_ENTRY
172 ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI
173 .if \no_user_check == 0
174 /* coming from usermode? */
175 testl $USER_SEGMENT_RPL_MASK, PT_CS(%esp)
180 testl $PTI_SWITCH_MASK, %eax
182 /* From userspace with kernel cr3 - BUG */
189 * Switch to kernel cr3 if not already loaded and return current cr3 in
192 .macro SWITCH_TO_KERNEL_CR3 scratch_reg:req
193 ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI
194 movl %cr3, \scratch_reg
195 /* Test if we are already on kernel CR3 */
196 testl $PTI_SWITCH_MASK, \scratch_reg
198 andl $(~PTI_SWITCH_MASK), \scratch_reg
199 movl \scratch_reg, %cr3
200 /* Return original CR3 in \scratch_reg */
201 orl $PTI_SWITCH_MASK, \scratch_reg
205 #define CS_FROM_ENTRY_STACK (1 << 31)
206 #define CS_FROM_USER_CR3 (1 << 30)
207 #define CS_FROM_KERNEL (1 << 29)
208 #define CS_FROM_ESPFIX (1 << 28)
212 * The high bits of the CS dword (__csh) are used for CS_FROM_*.
213 * Clear them in case hardware didn't do this for us.
215 andl $0x0000ffff, 4*4(%esp)
218 testl $X86_EFLAGS_VM, 5*4(%esp)
219 jnz .Lfrom_usermode_no_fixup_\@
221 testl $USER_SEGMENT_RPL_MASK, 4*4(%esp)
222 jnz .Lfrom_usermode_no_fixup_\@
224 orl $CS_FROM_KERNEL, 4*4(%esp)
227 * When we're here from kernel mode; the (exception) stack looks like:
229 * 6*4(%esp) - <previous context>
233 * 2*4(%esp) - orig_eax
234 * 1*4(%esp) - gs / function
237 * Lets build a 5 entry IRET frame after that, such that struct pt_regs
238 * is complete and in particular regs->sp is correct. This gives us
239 * the original 6 enties as gap:
241 * 14*4(%esp) - <previous context>
242 * 13*4(%esp) - gap / flags
243 * 12*4(%esp) - gap / cs
244 * 11*4(%esp) - gap / ip
245 * 10*4(%esp) - gap / orig_eax
246 * 9*4(%esp) - gap / gs / function
247 * 8*4(%esp) - gap / fs
253 * 2*4(%esp) - orig_eax
254 * 1*4(%esp) - gs / function
259 pushl %esp # sp (points at ss)
260 addl $7*4, (%esp) # point sp back at the previous context
261 pushl 7*4(%esp) # flags
264 pushl 7*4(%esp) # orig_eax
265 pushl 7*4(%esp) # gs / function
267 .Lfrom_usermode_no_fixup_\@:
272 * We're called with %ds, %es, %fs, and %gs from the interrupted
273 * frame, so we shouldn't use them. Also, we may be in ESPFIX
274 * mode and therefore have a nonzero SS base and an offset ESP,
275 * so any attempt to access the stack needs to use SS. (except for
276 * accesses through %esp, which automatically use SS.)
278 testl $CS_FROM_KERNEL, 1*4(%esp)
279 jz .Lfinished_frame_\@
282 * Reconstruct the 3 entry IRET frame right after the (modified)
283 * regs->sp without lowering %esp in between, such that an NMI in the
284 * middle doesn't scribble our stack.
288 movl 5*4(%esp), %eax # (modified) regs->sp
290 movl 4*4(%esp), %ecx # flags
291 movl %ecx, %ss:-1*4(%eax)
293 movl 3*4(%esp), %ecx # cs
294 andl $0x0000ffff, %ecx
295 movl %ecx, %ss:-2*4(%eax)
297 movl 2*4(%esp), %ecx # ip
298 movl %ecx, %ss:-3*4(%eax)
300 movl 1*4(%esp), %ecx # eax
301 movl %ecx, %ss:-4*4(%eax)
309 .macro SAVE_ALL pt_regs_ax=%eax switch_stacks=0 skip_gs=0 unwind_espfix=0
317 movl $(__KERNEL_PERCPU), %eax
319 .if \unwind_espfix > 0
334 movl $(__USER_DS), %edx
340 /* Switch to kernel stack if necessary */
341 .if \switch_stacks > 0
342 SWITCH_TO_KERNEL_STACK
346 .macro SAVE_ALL_NMI cr3_reg:req unwind_espfix=0
347 SAVE_ALL unwind_espfix=\unwind_espfix
352 * Now switch the CR3 when PTI is enabled.
354 * We can enter with either user or kernel cr3, the code will
355 * store the old cr3 in \cr3_reg and switches to the kernel cr3
358 SWITCH_TO_KERNEL_CR3 scratch_reg=\cr3_reg
363 .macro RESTORE_INT_REGS
373 .macro RESTORE_REGS pop=0
380 .pushsection .fixup, "ax"
394 .macro RESTORE_ALL_NMI cr3_reg:req pop=0
396 * Now switch the CR3 when PTI is enabled.
398 * We enter with kernel cr3 and switch the cr3 to the value
399 * stored on \cr3_reg, which is either a user or a kernel cr3.
401 ALTERNATIVE "jmp .Lswitched_\@", "", X86_FEATURE_PTI
403 testl $PTI_SWITCH_MASK, \cr3_reg
406 /* User cr3 in \cr3_reg - write it to hardware cr3 */
413 RESTORE_REGS pop=\pop
416 .macro CHECK_AND_APPLY_ESPFIX
417 #ifdef CONFIG_X86_ESPFIX32
418 #define GDT_ESPFIX_OFFSET (GDT_ENTRY_ESPFIX_SS * 8)
419 #define GDT_ESPFIX_SS PER_CPU_VAR(gdt_page) + GDT_ESPFIX_OFFSET
421 ALTERNATIVE "jmp .Lend_\@", "", X86_BUG_ESPFIX
423 movl PT_EFLAGS(%esp), %eax # mix EFLAGS, SS and CS
425 * Warning: PT_OLDSS(%esp) contains the wrong/random values if we
426 * are returning to the kernel.
427 * See comments in process.c:copy_thread() for details.
429 movb PT_OLDSS(%esp), %ah
430 movb PT_CS(%esp), %al
431 andl $(X86_EFLAGS_VM | (SEGMENT_TI_MASK << 8) | SEGMENT_RPL_MASK), %eax
432 cmpl $((SEGMENT_LDT << 8) | USER_RPL), %eax
433 jne .Lend_\@ # returning to user-space with LDT SS
436 * Setup and switch to ESPFIX stack
438 * We're returning to userspace with a 16 bit stack. The CPU will not
439 * restore the high word of ESP for us on executing iret... This is an
440 * "official" bug of all the x86-compatible CPUs, which we can work
441 * around to make dosemu and wine happy. We do this by preloading the
442 * high word of ESP with the high word of the userspace ESP while
443 * compensating for the offset by changing to the ESPFIX segment with
444 * a base address that matches for the difference.
446 mov %esp, %edx /* load kernel esp */
447 mov PT_OLDESP(%esp), %eax /* load userspace esp */
448 mov %dx, %ax /* eax: new kernel esp */
449 sub %eax, %edx /* offset (low word is 0) */
451 mov %dl, GDT_ESPFIX_SS + 4 /* bits 16..23 */
452 mov %dh, GDT_ESPFIX_SS + 7 /* bits 24..31 */
454 pushl %eax /* new kernel esp */
456 * Disable interrupts, but do not irqtrace this section: we
457 * will soon execute iret and the tracer was already set to
458 * the irqstate after the IRET:
460 DISABLE_INTERRUPTS(CLBR_ANY)
461 lss (%esp), %esp /* switch to espfix segment */
463 #endif /* CONFIG_X86_ESPFIX32 */
467 * Called with pt_regs fully populated and kernel segments loaded,
468 * so we can access PER_CPU and use the integer registers.
470 * We need to be very careful here with the %esp switch, because an NMI
471 * can happen everywhere. If the NMI handler finds itself on the
472 * entry-stack, it will overwrite the task-stack and everything we
473 * copied there. So allocate the stack-frame on the task-stack and
474 * switch to it before we do any copying.
477 .macro SWITCH_TO_KERNEL_STACK
479 ALTERNATIVE "", "jmp .Lend_\@", X86_FEATURE_XENPV
483 SWITCH_TO_KERNEL_CR3 scratch_reg=%eax
486 * %eax now contains the entry cr3 and we carry it forward in
487 * that register for the time this macro runs
490 /* Are we on the entry stack? Bail out if not! */
491 movl PER_CPU_VAR(cpu_entry_area), %ecx
492 addl $CPU_ENTRY_AREA_entry_stack + SIZEOF_entry_stack, %ecx
493 subl %esp, %ecx /* ecx = (end of entry_stack) - esp */
494 cmpl $SIZEOF_entry_stack, %ecx
497 /* Load stack pointer into %esi and %edi */
501 /* Move %edi to the top of the entry stack */
502 andl $(MASK_entry_stack), %edi
503 addl $(SIZEOF_entry_stack), %edi
505 /* Load top of task-stack into %edi */
506 movl TSS_entry2task_stack(%edi), %edi
508 /* Special case - entry from kernel mode via entry stack */
510 movl PT_EFLAGS(%esp), %ecx # mix EFLAGS and CS
511 movb PT_CS(%esp), %cl
512 andl $(X86_EFLAGS_VM | SEGMENT_RPL_MASK), %ecx
514 movl PT_CS(%esp), %ecx
515 andl $SEGMENT_RPL_MASK, %ecx
518 jb .Lentry_from_kernel_\@
521 movl $PTREGS_SIZE, %ecx
524 testl $X86_EFLAGS_VM, PT_EFLAGS(%esi)
528 * Stack-frame contains 4 additional segment registers when
529 * coming from VM86 mode
536 /* Allocate frame on task-stack */
539 /* Switch to task-stack */
543 * We are now on the task-stack and can safely copy over the
552 .Lentry_from_kernel_\@:
555 * This handles the case when we enter the kernel from
556 * kernel-mode and %esp points to the entry-stack. When this
557 * happens we need to switch to the task-stack to run C code,
558 * but switch back to the entry-stack again when we approach
559 * iret and return to the interrupted code-path. This usually
560 * happens when we hit an exception while restoring user-space
561 * segment registers on the way back to user-space or when the
562 * sysenter handler runs with eflags.tf set.
564 * When we switch to the task-stack here, we can't trust the
565 * contents of the entry-stack anymore, as the exception handler
566 * might be scheduled out or moved to another CPU. Therefore we
567 * copy the complete entry-stack to the task-stack and set a
568 * marker in the iret-frame (bit 31 of the CS dword) to detect
569 * what we've done on the iret path.
571 * On the iret path we copy everything back and switch to the
572 * entry-stack, so that the interrupted kernel code-path
573 * continues on the same stack it was interrupted with.
575 * Be aware that an NMI can happen anytime in this code.
577 * %esi: Entry-Stack pointer (same as %esp)
578 * %edi: Top of the task stack
579 * %eax: CR3 on kernel entry
582 /* Calculate number of bytes on the entry stack in %ecx */
585 /* %ecx to the top of entry-stack */
586 andl $(MASK_entry_stack), %ecx
587 addl $(SIZEOF_entry_stack), %ecx
589 /* Number of bytes on the entry stack to %ecx */
592 /* Mark stackframe as coming from entry stack */
593 orl $CS_FROM_ENTRY_STACK, PT_CS(%esp)
596 * Test the cr3 used to enter the kernel and add a marker
597 * so that we can switch back to it before iret.
599 testl $PTI_SWITCH_MASK, %eax
601 orl $CS_FROM_USER_CR3, PT_CS(%esp)
604 * %esi and %edi are unchanged, %ecx contains the number of
605 * bytes to copy. The code at .Lcopy_pt_regs_\@ will allocate
606 * the stack-frame on task-stack and copy everything over
608 jmp .Lcopy_pt_regs_\@
614 * Switch back from the kernel stack to the entry stack.
616 * The %esp register must point to pt_regs on the task stack. It will
617 * first calculate the size of the stack-frame to copy, depending on
618 * whether we return to VM86 mode or not. With that it uses 'rep movsl'
619 * to copy the contents of the stack over to the entry stack.
621 * We must be very careful here, as we can't trust the contents of the
622 * task-stack once we switched to the entry-stack. When an NMI happens
623 * while on the entry-stack, the NMI handler will switch back to the top
624 * of the task stack, overwriting our stack-frame we are about to copy.
625 * Therefore we switch the stack only after everything is copied over.
627 .macro SWITCH_TO_ENTRY_STACK
629 ALTERNATIVE "", "jmp .Lend_\@", X86_FEATURE_XENPV
632 movl $PTREGS_SIZE, %ecx
635 testl $(X86_EFLAGS_VM), PT_EFLAGS(%esp)
638 /* Additional 4 registers to copy when returning to VM86 mode */
644 /* Initialize source and destination for movsl */
645 movl PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %edi
649 /* Save future stack pointer in %ebx */
652 /* Copy over the stack-frame */
658 * Switch to entry-stack - needs to happen after everything is
659 * copied because the NMI handler will overwrite the task-stack
660 * when on entry-stack
668 * This macro handles the case when we return to kernel-mode on the iret
669 * path and have to switch back to the entry stack and/or user-cr3
671 * See the comments below the .Lentry_from_kernel_\@ label in the
672 * SWITCH_TO_KERNEL_STACK macro for more details.
674 .macro PARANOID_EXIT_TO_KERNEL_MODE
677 * Test if we entered the kernel with the entry-stack. Most
678 * likely we did not, because this code only runs on the
679 * return-to-kernel path.
681 testl $CS_FROM_ENTRY_STACK, PT_CS(%esp)
684 /* Unlikely slow-path */
686 /* Clear marker from stack-frame */
687 andl $(~CS_FROM_ENTRY_STACK), PT_CS(%esp)
689 /* Copy the remaining task-stack contents to entry-stack */
691 movl PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %edi
693 /* Bytes on the task-stack to ecx */
694 movl PER_CPU_VAR(cpu_tss_rw + TSS_sp1), %ecx
697 /* Allocate stack-frame on entry-stack */
701 * Save future stack-pointer, we must not switch until the
702 * copy is done, otherwise the NMI handler could destroy the
703 * contents of the task-stack we are about to copy.
712 /* Safe to switch to entry-stack now */
716 * We came from entry-stack and need to check if we also need to
717 * switch back to user cr3.
719 testl $CS_FROM_USER_CR3, PT_CS(%esp)
722 /* Clear marker from stack-frame */
723 andl $(~CS_FROM_USER_CR3), PT_CS(%esp)
725 SWITCH_TO_USER_CR3 scratch_reg=%eax
733 ENTRY(__switch_to_asm)
735 * Save callee-saved registers
736 * This must match the order in struct inactive_task_frame
745 movl %esp, TASK_threadsp(%eax)
746 movl TASK_threadsp(%edx), %esp
748 #ifdef CONFIG_STACKPROTECTOR
749 movl TASK_stack_canary(%edx), %ebx
750 movl %ebx, PER_CPU_VAR(stack_canary)+stack_canary_offset
754 * When switching from a shallower to a deeper call stack
755 * the RSB may either underflow or use entries populated
756 * with userspace addresses. On CPUs where those concerns
757 * exist, overwrite the RSB with entries which capture
758 * speculative execution to prevent attack.
760 FILL_RETURN_BUFFER %ebx, RSB_CLEAR_LOOPS, X86_FEATURE_RSB_CTXSW
762 /* restore callee-saved registers */
773 * The unwinder expects the last frame on the stack to always be at the same
774 * offset from the end of the page, which allows it to validate the stack.
775 * Calling schedule_tail() directly would break that convention because its an
776 * asmlinkage function so its argument has to be pushed on the stack. This
777 * wrapper creates a proper "end of stack" frame header before the call.
779 ENTRY(schedule_tail_wrapper)
788 ENDPROC(schedule_tail_wrapper)
790 * A newly forked process directly context switches into this address.
792 * eax: prev task we switched from
793 * ebx: kernel thread func (NULL for user thread)
794 * edi: kernel thread arg
797 call schedule_tail_wrapper
800 jnz 1f /* kernel threads are uncommon */
803 /* When we fork, we trace the syscall return in the child, too. */
805 call syscall_return_slowpath
813 * A kernel thread is allowed to return here after successfully
814 * calling do_execve(). Exit to userspace to complete the execve()
817 movl $0, PT_EAX(%esp)
822 * Return to user mode is not as complex as all this looks,
823 * but we want the default path for a system call return to
824 * go as quickly as possible which is why some of this is
825 * less clear than it otherwise should be.
828 # userspace resumption stub bypassing syscall exit tracing
831 preempt_stop(CLBR_ANY)
834 movl PT_EFLAGS(%esp), %eax # mix EFLAGS and CS
835 movb PT_CS(%esp), %al
836 andl $(X86_EFLAGS_VM | SEGMENT_RPL_MASK), %eax
839 * We can be coming here from child spawned by kernel_thread().
841 movl PT_CS(%esp), %eax
842 andl $SEGMENT_RPL_MASK, %eax
845 jb restore_all_kernel # not returning to v8086 or userspace
847 ENTRY(resume_userspace)
848 DISABLE_INTERRUPTS(CLBR_ANY)
851 call prepare_exit_to_usermode
853 END(ret_from_exception)
855 GLOBAL(__begin_SYSENTER_singlestep_region)
857 * All code from here through __end_SYSENTER_singlestep_region is subject
858 * to being single-stepped if a user program sets TF and executes SYSENTER.
859 * There is absolutely nothing that we can do to prevent this from happening
860 * (thanks Intel!). To keep our handling of this situation as simple as
861 * possible, we handle TF just like AC and NT, except that our #DB handler
862 * will ignore all of the single-step traps generated in this range.
867 * Xen doesn't set %esp to be precisely what the normal SYSENTER
868 * entry point expects, so fix it up before using the normal path.
870 SYM_CODE_START(xen_sysenter_target)
871 addl $5*4, %esp /* remove xen-provided frame */
872 jmp .Lsysenter_past_esp
873 SYM_CODE_END(xen_sysenter_target)
877 * 32-bit SYSENTER entry.
879 * 32-bit system calls through the vDSO's __kernel_vsyscall enter here
880 * if X86_FEATURE_SEP is available. This is the preferred system call
881 * entry on 32-bit systems.
883 * The SYSENTER instruction, in principle, should *only* occur in the
884 * vDSO. In practice, a small number of Android devices were shipped
885 * with a copy of Bionic that inlined a SYSENTER instruction. This
886 * never happened in any of Google's Bionic versions -- it only happened
887 * in a narrow range of Intel-provided versions.
889 * SYSENTER loads SS, ESP, CS, and EIP from previously programmed MSRs.
890 * IF and VM in RFLAGS are cleared (IOW: interrupts are off).
891 * SYSENTER does not save anything on the stack,
892 * and does not save old EIP (!!!), ESP, or EFLAGS.
894 * To avoid losing track of EFLAGS.VM (and thus potentially corrupting
895 * user and/or vm86 state), we explicitly disable the SYSENTER
896 * instruction in vm86 mode by reprogramming the MSRs.
899 * eax system call number
908 ENTRY(entry_SYSENTER_32)
910 * On entry-stack with all userspace-regs live - save and
911 * restore eflags and %eax to use it as scratch-reg for the cr3
916 BUG_IF_WRONG_CR3 no_user_check=1
917 SWITCH_TO_KERNEL_CR3 scratch_reg=%eax
921 /* Stack empty again, switch to task stack */
922 movl TSS_entry2task_stack(%esp), %esp
925 pushl $__USER_DS /* pt_regs->ss */
926 pushl %ebp /* pt_regs->sp (stashed in bp) */
927 pushfl /* pt_regs->flags (except IF = 0) */
928 orl $X86_EFLAGS_IF, (%esp) /* Fix IF */
929 pushl $__USER_CS /* pt_regs->cs */
930 pushl $0 /* pt_regs->ip = 0 (placeholder) */
931 pushl %eax /* pt_regs->orig_ax */
932 SAVE_ALL pt_regs_ax=$-ENOSYS /* save rest, stack already switched */
935 * SYSENTER doesn't filter flags, so we need to clear NT, AC
936 * and TF ourselves. To save a few cycles, we can check whether
937 * either was set instead of doing an unconditional popfq.
938 * This needs to happen before enabling interrupts so that
939 * we don't get preempted with NT set.
941 * If TF is set, we will single-step all the way to here -- do_debug
942 * will ignore all the traps. (Yes, this is slow, but so is
943 * single-stepping in general. This allows us to avoid having
944 * a more complicated code to handle the case where a user program
945 * forces us to single-step through the SYSENTER entry code.)
947 * NB.: .Lsysenter_fix_flags is a label with the code under it moved
948 * out-of-line as an optimization: NT is unlikely to be set in the
949 * majority of the cases and instead of polluting the I$ unnecessarily,
950 * we're keeping that code behind a branch which will predict as
951 * not-taken and therefore its instructions won't be fetched.
953 testl $X86_EFLAGS_NT|X86_EFLAGS_AC|X86_EFLAGS_TF, PT_EFLAGS(%esp)
954 jnz .Lsysenter_fix_flags
955 .Lsysenter_flags_fixed:
958 * User mode is traced as though IRQs are on, and SYSENTER
964 call do_fast_syscall_32
965 /* XEN PV guests always use IRET path */
966 ALTERNATIVE "testl %eax, %eax; jz .Lsyscall_32_done", \
967 "jmp .Lsyscall_32_done", X86_FEATURE_XENPV
971 /* Opportunistic SYSEXIT */
972 TRACE_IRQS_ON /* User mode traces as IRQs on. */
975 * Setup entry stack - we keep the pointer in %eax and do the
976 * switch after almost all user-state is restored.
979 /* Load entry stack pointer and allocate frame for eflags/eax */
980 movl PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %eax
983 /* Copy eflags and eax to entry stack */
984 movl PT_EFLAGS(%esp), %edi
985 movl PT_EAX(%esp), %esi
989 /* Restore user registers and segments */
990 movl PT_EIP(%esp), %edx /* pt_regs->ip */
991 movl PT_OLDESP(%esp), %ecx /* pt_regs->sp */
992 1: mov PT_FS(%esp), %fs
995 popl %ebx /* pt_regs->bx */
996 addl $2*4, %esp /* skip pt_regs->cx and pt_regs->dx */
997 popl %esi /* pt_regs->si */
998 popl %edi /* pt_regs->di */
999 popl %ebp /* pt_regs->bp */
1001 /* Switch to entry stack */
1004 /* Now ready to switch the cr3 */
1005 SWITCH_TO_USER_CR3 scratch_reg=%eax
1008 * Restore all flags except IF. (We restore IF separately because
1009 * STI gives a one-instruction window in which we won't be interrupted,
1010 * whereas POPF does not.)
1012 btrl $X86_EFLAGS_IF_BIT, (%esp)
1013 BUG_IF_WRONG_CR3 no_user_check=1
1018 * Return back to the vDSO, which will pop ecx and edx.
1019 * Don't bother with DS and ES (they already contain __USER_DS).
1024 .pushsection .fixup, "ax"
1025 2: movl $0, PT_FS(%esp)
1028 _ASM_EXTABLE(1b, 2b)
1031 .Lsysenter_fix_flags:
1032 pushl $X86_EFLAGS_FIXED
1034 jmp .Lsysenter_flags_fixed
1035 GLOBAL(__end_SYSENTER_singlestep_region)
1036 ENDPROC(entry_SYSENTER_32)
1039 * 32-bit legacy system call entry.
1041 * 32-bit x86 Linux system calls traditionally used the INT $0x80
1042 * instruction. INT $0x80 lands here.
1044 * This entry point can be used by any 32-bit perform system calls.
1045 * Instances of INT $0x80 can be found inline in various programs and
1046 * libraries. It is also used by the vDSO's __kernel_vsyscall
1047 * fallback for hardware that doesn't support a faster entry method.
1048 * Restarted 32-bit system calls also fall back to INT $0x80
1049 * regardless of what instruction was originally used to do the system
1050 * call. (64-bit programs can use INT $0x80 as well, but they can
1051 * only run on 64-bit kernels and therefore land in
1052 * entry_INT80_compat.)
1054 * This is considered a slow path. It is not used by most libc
1055 * implementations on modern hardware except during process startup.
1058 * eax system call number
1066 ENTRY(entry_INT80_32)
1068 pushl %eax /* pt_regs->orig_ax */
1070 SAVE_ALL pt_regs_ax=$-ENOSYS switch_stacks=1 /* save rest */
1073 * User mode is traced as though IRQs are on, and the interrupt gate
1079 call do_int80_syscall_32
1086 SWITCH_TO_ENTRY_STACK
1087 .Lrestore_all_notrace:
1088 CHECK_AND_APPLY_ESPFIX
1090 /* Switch back to user CR3 */
1091 SWITCH_TO_USER_CR3 scratch_reg=%eax
1095 /* Restore user state */
1096 RESTORE_REGS pop=4 # skip orig_eax/error_code
1099 * ARCH_HAS_MEMBARRIER_SYNC_CORE rely on IRET core serialization
1100 * when returning from IPI handler and when returning from
1101 * scheduler to user-space.
1106 #ifdef CONFIG_PREEMPTION
1107 DISABLE_INTERRUPTS(CLBR_ANY)
1108 cmpl $0, PER_CPU_VAR(__preempt_count)
1110 testl $X86_EFLAGS_IF, PT_EFLAGS(%esp) # interrupts off (exception path) ?
1112 call preempt_schedule_irq
1116 PARANOID_EXIT_TO_KERNEL_MODE
1121 .section .fixup, "ax"
1123 pushl $0 # no error code
1124 pushl $do_iret_error
1126 #ifdef CONFIG_DEBUG_ENTRY
1128 * The stack-frame here is the one that iret faulted on, so its a
1129 * return-to-user frame. We are on kernel-cr3 because we come here from
1130 * the fixup code. This confuses the CR3 checker, so switch to user-cr3
1131 * as the checker expects it.
1134 SWITCH_TO_USER_CR3 scratch_reg=%eax
1138 jmp common_exception
1140 _ASM_EXTABLE(.Lirq_return, iret_exc)
1141 ENDPROC(entry_INT80_32)
1143 .macro FIXUP_ESPFIX_STACK
1145 * Switch back for ESPFIX stack to the normal zerobased stack
1147 * We can't call C functions using the ESPFIX stack. This code reads
1148 * the high word of the segment base from the GDT and swiches to the
1149 * normal stack and adjusts ESP with the matching offset.
1151 * We might be on user CR3 here, so percpu data is not mapped and we can't
1152 * access the GDT through the percpu segment. Instead, use SGDT to find
1153 * the cpu_entry_area alias of the GDT.
1155 #ifdef CONFIG_X86_ESPFIX32
1156 /* fixup the stack */
1160 movl 2(%esp), %ecx /* GDT address */
1162 * Careful: ECX is a linear pointer, so we need to force base
1163 * zero. %cs is the only known-linear segment we have right now.
1165 mov %cs:GDT_ESPFIX_OFFSET + 4(%ecx), %al /* bits 16..23 */
1166 mov %cs:GDT_ESPFIX_OFFSET + 7(%ecx), %ah /* bits 24..31 */
1170 addl %esp, %eax /* the adjusted stack pointer */
1173 lss (%esp), %esp /* switch to the normal stack segment */
1177 .macro UNWIND_ESPFIX_STACK
1178 /* It's safe to clobber %eax, all other regs need to be preserved */
1179 #ifdef CONFIG_X86_ESPFIX32
1181 /* see if on espfix stack */
1182 cmpw $__ESPFIX_SS, %ax
1184 /* switch to normal stack */
1191 * Build the entry stubs with some assembler magic.
1192 * We pack 1 stub into every 8-byte block.
1195 ENTRY(irq_entries_start)
1196 vector=FIRST_EXTERNAL_VECTOR
1197 .rept (FIRST_SYSTEM_VECTOR - FIRST_EXTERNAL_VECTOR)
1198 pushl $(~vector+0x80) /* Note: always in signed byte range */
1200 jmp common_interrupt
1203 END(irq_entries_start)
1205 #ifdef CONFIG_X86_LOCAL_APIC
1207 ENTRY(spurious_entries_start)
1208 vector=FIRST_SYSTEM_VECTOR
1209 .rept (NR_VECTORS - FIRST_SYSTEM_VECTOR)
1210 pushl $(~vector+0x80) /* Note: always in signed byte range */
1215 END(spurious_entries_start)
1219 addl $-0x80, (%esp) /* Adjust vector into the [-256, -1] range */
1220 SAVE_ALL switch_stacks=1
1221 ENCODE_FRAME_POINTER
1224 call smp_spurious_interrupt
1226 ENDPROC(common_spurious)
1230 * the CPU automatically disables interrupts when executing an IRQ vector,
1231 * so IRQ-flags tracing has to follow that:
1233 .p2align CONFIG_X86_L1_CACHE_SHIFT
1236 addl $-0x80, (%esp) /* Adjust vector into the [-256, -1] range */
1238 SAVE_ALL switch_stacks=1
1239 ENCODE_FRAME_POINTER
1244 ENDPROC(common_interrupt)
1246 #define BUILD_INTERRUPT3(name, nr, fn) \
1250 SAVE_ALL switch_stacks=1; \
1251 ENCODE_FRAME_POINTER; \
1255 jmp ret_from_intr; \
1258 #define BUILD_INTERRUPT(name, nr) \
1259 BUILD_INTERRUPT3(name, nr, smp_##name); \
1261 /* The include is where all of the SMP etc. interrupts come from */
1262 #include <asm/entry_arch.h>
1264 ENTRY(coprocessor_error)
1267 pushl $do_coprocessor_error
1268 jmp common_exception
1269 END(coprocessor_error)
1271 ENTRY(simd_coprocessor_error)
1274 #ifdef CONFIG_X86_INVD_BUG
1275 /* AMD 486 bug: invd from userspace calls exception 19 instead of #GP */
1276 ALTERNATIVE "pushl $do_general_protection", \
1277 "pushl $do_simd_coprocessor_error", \
1280 pushl $do_simd_coprocessor_error
1282 jmp common_exception
1283 END(simd_coprocessor_error)
1285 ENTRY(device_not_available)
1287 pushl $-1 # mark this as an int
1288 pushl $do_device_not_available
1289 jmp common_exception
1290 END(device_not_available)
1292 #ifdef CONFIG_PARAVIRT
1295 _ASM_EXTABLE(native_iret, iret_exc)
1303 jmp common_exception
1310 jmp common_exception
1316 pushl $do_invalid_op
1317 jmp common_exception
1320 ENTRY(coprocessor_segment_overrun)
1323 pushl $do_coprocessor_segment_overrun
1324 jmp common_exception
1325 END(coprocessor_segment_overrun)
1329 pushl $do_invalid_TSS
1330 jmp common_exception
1333 ENTRY(segment_not_present)
1335 pushl $do_segment_not_present
1336 jmp common_exception
1337 END(segment_not_present)
1339 ENTRY(stack_segment)
1341 pushl $do_stack_segment
1342 jmp common_exception
1345 ENTRY(alignment_check)
1347 pushl $do_alignment_check
1348 jmp common_exception
1349 END(alignment_check)
1353 pushl $0 # no error code
1354 pushl $do_divide_error
1355 jmp common_exception
1358 #ifdef CONFIG_X86_MCE
1359 ENTRY(machine_check)
1362 pushl machine_check_vector
1363 jmp common_exception
1367 ENTRY(spurious_interrupt_bug)
1370 pushl $do_spurious_interrupt_bug
1371 jmp common_exception
1372 END(spurious_interrupt_bug)
1374 #ifdef CONFIG_XEN_PV
1375 ENTRY(xen_hypervisor_callback)
1377 * Check to see if we got the event in the critical
1378 * region in xen_iret_direct, after we've reenabled
1379 * events and checked for pending events. This simulates
1380 * iret instruction's behaviour where it delivers a
1381 * pending interrupt when enabling interrupts:
1383 cmpl $xen_iret_start_crit, (%esp)
1385 cmpl $xen_iret_end_crit, (%esp)
1387 call xen_iret_crit_fixup
1389 pushl $-1 /* orig_ax = -1 => not a system call */
1391 ENCODE_FRAME_POINTER
1394 call xen_evtchn_do_upcall
1395 #ifndef CONFIG_PREEMPTION
1396 call xen_maybe_preempt_hcall
1399 ENDPROC(xen_hypervisor_callback)
1402 * Hypervisor uses this for application faults while it executes.
1403 * We get here for two reasons:
1404 * 1. Fault while reloading DS, ES, FS or GS
1405 * 2. Fault while executing IRET
1406 * Category 1 we fix up by reattempting the load, and zeroing the segment
1407 * register if the load fails.
1408 * Category 2 we fix up by jumping to do_iret_error. We cannot use the
1409 * normal Linux return path in this case because if we use the IRET hypercall
1410 * to pop the stack frame we end up in an infinite loop of failsafe callbacks.
1411 * We distinguish between categories by maintaining a status value in EAX.
1413 ENTRY(xen_failsafe_callback)
1418 3: mov 12(%esp), %fs
1419 4: mov 16(%esp), %gs
1420 /* EAX == 0 => Category 1 (Bad segment)
1421 EAX != 0 => Category 2 (Bad IRET) */
1427 5: pushl $-1 /* orig_ax = -1 => not a system call */
1429 ENCODE_FRAME_POINTER
1430 jmp ret_from_exception
1432 .section .fixup, "ax"
1446 _ASM_EXTABLE(1b, 6b)
1447 _ASM_EXTABLE(2b, 7b)
1448 _ASM_EXTABLE(3b, 8b)
1449 _ASM_EXTABLE(4b, 9b)
1450 ENDPROC(xen_failsafe_callback)
1451 #endif /* CONFIG_XEN_PV */
1453 #ifdef CONFIG_XEN_PVHVM
1454 BUILD_INTERRUPT3(xen_hvm_callback_vector, HYPERVISOR_CALLBACK_VECTOR,
1455 xen_evtchn_do_upcall)
1459 #if IS_ENABLED(CONFIG_HYPERV)
1461 BUILD_INTERRUPT3(hyperv_callback_vector, HYPERVISOR_CALLBACK_VECTOR,
1462 hyperv_vector_handler)
1464 BUILD_INTERRUPT3(hyperv_reenlightenment_vector, HYPERV_REENLIGHTENMENT_VECTOR,
1465 hyperv_reenlightenment_intr)
1467 BUILD_INTERRUPT3(hv_stimer0_callback_vector, HYPERV_STIMER0_VECTOR,
1468 hv_stimer0_vector_handler)
1470 #endif /* CONFIG_HYPERV */
1474 pushl $do_page_fault
1475 jmp common_exception_read_cr2
1478 common_exception_read_cr2:
1479 /* the function address is in %gs's slot on the stack */
1480 SAVE_ALL switch_stacks=1 skip_gs=1 unwind_espfix=1
1482 ENCODE_FRAME_POINTER
1486 movl PT_GS(%esp), %edi
1490 GET_CR2_INTO(%ecx) # might clobber %eax
1492 /* fixup orig %eax */
1493 movl PT_ORIG_EAX(%esp), %edx # get the error code
1494 movl $-1, PT_ORIG_EAX(%esp) # no syscall to restart
1497 movl %esp, %eax # pt_regs pointer
1499 jmp ret_from_exception
1500 END(common_exception_read_cr2)
1503 /* the function address is in %gs's slot on the stack */
1504 SAVE_ALL switch_stacks=1 skip_gs=1 unwind_espfix=1
1505 ENCODE_FRAME_POINTER
1509 movl PT_GS(%esp), %edi # get the function address
1513 /* fixup orig %eax */
1514 movl PT_ORIG_EAX(%esp), %edx # get the error code
1515 movl $-1, PT_ORIG_EAX(%esp) # no syscall to restart
1518 movl %esp, %eax # pt_regs pointer
1520 jmp ret_from_exception
1521 END(common_exception)
1525 * Entry from sysenter is now handled in common_exception
1528 pushl $-1 # mark this as an int
1530 jmp common_exception
1534 * NMI is doubly nasty. It can happen on the first instruction of
1535 * entry_SYSENTER_32 (just like #DB), but it can also interrupt the beginning
1536 * of the #DB handler even if that #DB in turn hit before entry_SYSENTER_32
1537 * switched stacks. We handle both conditions by simply checking whether we
1538 * interrupted kernel code running on the SYSENTER stack.
1543 #ifdef CONFIG_X86_ESPFIX32
1545 * ESPFIX_SS is only ever set on the return to user path
1546 * after we've switched to the entry stack.
1550 cmpw $__ESPFIX_SS, %ax
1552 je .Lnmi_espfix_stack
1555 pushl %eax # pt_regs->orig_ax
1556 SAVE_ALL_NMI cr3_reg=%edi
1557 ENCODE_FRAME_POINTER
1558 xorl %edx, %edx # zero error code
1559 movl %esp, %eax # pt_regs pointer
1561 /* Are we currently on the SYSENTER stack? */
1562 movl PER_CPU_VAR(cpu_entry_area), %ecx
1563 addl $CPU_ENTRY_AREA_entry_stack + SIZEOF_entry_stack, %ecx
1564 subl %eax, %ecx /* ecx = (end of entry_stack) - esp */
1565 cmpl $SIZEOF_entry_stack, %ecx
1566 jb .Lnmi_from_sysenter_stack
1568 /* Not on SYSENTER stack. */
1572 .Lnmi_from_sysenter_stack:
1574 * We're on the SYSENTER stack. Switch off. No one (not even debug)
1575 * is using the thread stack right now, so it's safe for us to use it.
1578 movl PER_CPU_VAR(cpu_current_top_of_stack), %esp
1583 #ifdef CONFIG_X86_ESPFIX32
1584 testl $CS_FROM_ESPFIX, PT_CS(%esp)
1585 jnz .Lnmi_from_espfix
1588 CHECK_AND_APPLY_ESPFIX
1589 RESTORE_ALL_NMI cr3_reg=%edi pop=4
1592 #ifdef CONFIG_X86_ESPFIX32
1595 * Create the pointer to LSS back
1601 /* Copy the (short) IRET frame */
1602 pushl 4*4(%esp) # flags
1603 pushl 4*4(%esp) # cs
1604 pushl 4*4(%esp) # ip
1606 pushl %eax # orig_ax
1608 SAVE_ALL_NMI cr3_reg=%edi unwind_espfix=1
1609 ENCODE_FRAME_POINTER
1611 /* clear CS_FROM_KERNEL, set CS_FROM_ESPFIX */
1612 xorl $(CS_FROM_ESPFIX | CS_FROM_KERNEL), PT_CS(%esp)
1614 xorl %edx, %edx # zero error code
1615 movl %esp, %eax # pt_regs pointer
1616 jmp .Lnmi_from_sysenter_stack
1619 RESTORE_ALL_NMI cr3_reg=%edi
1621 * Because we cleared CS_FROM_KERNEL, IRET_FRAME 'forgot' to
1622 * fix up the gap and long frame:
1624 * 3 - original frame (exception)
1625 * 2 - ESPFIX block (above)
1626 * 6 - gap (FIXUP_FRAME)
1627 * 5 - long frame (FIXUP_FRAME)
1630 lss (1+5+6)*4(%esp), %esp # back to espfix stack
1637 pushl $-1 # mark this as an int
1639 SAVE_ALL switch_stacks=1
1640 ENCODE_FRAME_POINTER
1642 xorl %edx, %edx # zero error code
1643 movl %esp, %eax # pt_regs pointer
1645 jmp ret_from_exception
1648 ENTRY(general_protection)
1650 pushl $do_general_protection
1651 jmp common_exception
1652 END(general_protection)
1654 #ifdef CONFIG_KVM_GUEST
1655 ENTRY(async_page_fault)
1657 pushl $do_async_page_fault
1658 jmp common_exception_read_cr2
1659 END(async_page_fault)
1662 ENTRY(rewind_stack_and_make_dead)
1663 /* Prevent any naive code from trying to unwind to our caller. */
1666 movl PER_CPU_VAR(cpu_current_top_of_stack), %esi
1667 leal -TOP_OF_KERNEL_STACK_PADDING-PTREGS_SIZE(%esi), %esp
1671 END(rewind_stack_and_make_dead)