1 /* SPDX-License-Identifier: GPL-2.0 */
2 #include <linux/jump_label.h>
3 #include <asm/unwind_hints.h>
4 #include <asm/cpufeatures.h>
5 #include <asm/page_types.h>
6 #include <asm/percpu.h>
7 #include <asm/asm-offsets.h>
8 #include <asm/processor-flags.h>
10 #include <asm/nospec-branch.h>
14 x86 function call convention, 64-bit:
15 -------------------------------------
16 arguments | callee-saved | extra caller-saved | return
17 [callee-clobbered] | | [callee-clobbered] |
18 ---------------------------------------------------------------------------
19 rdi rsi rdx rcx r8-9 | rbx rbp [*] r12-15 | r10-11 | rax, rdx [**]
21 ( rsp is obviously invariant across normal function calls. (gcc can 'merge'
22 functions when it sees tail-call optimization possibilities) rflags is
23 clobbered. Leftover arguments are passed over the stack frame.)
25 [*] In the frame-pointers case rbp is fixed to the stack frame.
27 [**] for struct return values wider than 64 bits the return convention is a
28 bit more complex: up to 128 bits width we return small structures
29 straight in rax, rdx. For structures larger than that (3 words or
30 larger) the caller puts a pointer to an on-stack return struct
31 [allocated in the caller's stack frame] into the first argument - i.e.
32 into rdi. All other arguments shift up by one in this case.
33 Fortunately this case is rare in the kernel.
35 For 32-bit we have the following conventions - kernel is built with
36 -mregparm=3 and -freg-struct-return:
38 x86 function calling convention, 32-bit:
39 ----------------------------------------
40 arguments | callee-saved | extra caller-saved | return
41 [callee-clobbered] | | [callee-clobbered] |
42 -------------------------------------------------------------------------
43 eax edx ecx | ebx edi esi ebp [*] | <none> | eax, edx [**]
45 ( here too esp is obviously invariant across normal function calls. eflags
46 is clobbered. Leftover arguments are passed over the stack frame. )
48 [*] In the frame-pointers case ebp is fixed to the stack frame.
50 [**] We build with -freg-struct-return, which on 32-bit means similar
51 semantics as on 64-bit: edx can be used for a second return value
52 (i.e. covering integer and structure sizes up to 64 bits) - after that
53 it gets more complex and more expensive: 3-word or larger struct returns
54 get done in the caller's frame and the pointer to the return struct goes
55 into regparm0, i.e. eax - the other arguments shift up and the
56 function's register parameters degenerate to regparm=2 in essence.
63 * 64-bit system call stack frame layout defines and helpers,
67 /* The layout forms the "struct pt_regs" on the stack: */
69 * C ABI says these regs are callee-preserved. They aren't saved on kernel entry
70 * unless syscall needs a complete, fully filled "struct pt_regs".
78 /* These regs are callee-clobbered. Always saved on kernel entry. */
89 * On syscall entry, this is syscall#. On CPU exception, this is error code.
90 * On hw interrupt, it's IRQ number:
93 /* Return frame for iretq */
100 #define SIZEOF_PTREGS 21*8
102 .macro PUSH_AND_CLEAR_REGS rdx=%rdx rax=%rax save_ret=0
104 pushq %rsi /* pt_regs->si */
105 movq 8(%rsp), %rsi /* temporarily store the return address in %rsi */
106 movq %rdi, 8(%rsp) /* pt_regs->di (overwriting original return address) */
108 pushq %rdi /* pt_regs->di */
109 pushq %rsi /* pt_regs->si */
111 pushq \rdx /* pt_regs->dx */
112 pushq %rcx /* pt_regs->cx */
113 pushq \rax /* pt_regs->ax */
114 pushq %r8 /* pt_regs->r8 */
115 pushq %r9 /* pt_regs->r9 */
116 pushq %r10 /* pt_regs->r10 */
117 pushq %r11 /* pt_regs->r11 */
118 pushq %rbx /* pt_regs->rbx */
119 pushq %rbp /* pt_regs->rbp */
120 pushq %r12 /* pt_regs->r12 */
121 pushq %r13 /* pt_regs->r13 */
122 pushq %r14 /* pt_regs->r14 */
123 pushq %r15 /* pt_regs->r15 */
127 pushq %rsi /* return address on top of stack */
131 * Sanitize registers of values that a speculation attack might
132 * otherwise want to exploit. The lower registers are likely clobbered
133 * well before they could be put to use in a speculative execution
136 xorl %edx, %edx /* nospec dx */
137 xorl %ecx, %ecx /* nospec cx */
138 xorl %r8d, %r8d /* nospec r8 */
139 xorl %r9d, %r9d /* nospec r9 */
140 xorl %r10d, %r10d /* nospec r10 */
141 xorl %r11d, %r11d /* nospec r11 */
142 xorl %ebx, %ebx /* nospec rbx */
143 xorl %ebp, %ebp /* nospec rbp */
144 xorl %r12d, %r12d /* nospec r12 */
145 xorl %r13d, %r13d /* nospec r13 */
146 xorl %r14d, %r14d /* nospec r14 */
147 xorl %r15d, %r15d /* nospec r15 */
151 .macro POP_REGS pop_rdi=1
172 * This is a sneaky trick to help the unwinder find pt_regs on the stack. The
173 * frame pointer is replaced with an encoded pointer to pt_regs. The encoding
174 * is just setting the LSB, which makes it an invalid stack address and is also
175 * a signal to the unwinder that it's a pt_regs pointer in disguise.
177 * NOTE: This macro must be used *after* PUSH_AND_CLEAR_REGS because it corrupts
180 .macro ENCODE_FRAME_POINTER ptregs_offset=0
181 #ifdef CONFIG_FRAME_POINTER
183 leaq \ptregs_offset(%rsp), %rbp
191 #ifdef CONFIG_PAGE_TABLE_ISOLATION
194 * PAGE_TABLE_ISOLATION PGDs are 8k. Flip bit 12 to switch between the two
197 #define PTI_USER_PGTABLE_BIT PAGE_SHIFT
198 #define PTI_USER_PGTABLE_MASK (1 << PTI_USER_PGTABLE_BIT)
199 #define PTI_USER_PCID_BIT X86_CR3_PTI_PCID_USER_BIT
200 #define PTI_USER_PCID_MASK (1 << PTI_USER_PCID_BIT)
201 #define PTI_USER_PGTABLE_AND_PCID_MASK (PTI_USER_PCID_MASK | PTI_USER_PGTABLE_MASK)
203 .macro SET_NOFLUSH_BIT reg:req
204 bts $X86_CR3_PCID_NOFLUSH_BIT, \reg
207 .macro ADJUST_KERNEL_CR3 reg:req
208 ALTERNATIVE "", "SET_NOFLUSH_BIT \reg", X86_FEATURE_PCID
209 /* Clear PCID and "PAGE_TABLE_ISOLATION bit", point CR3 at kernel pagetables: */
210 andq $(~PTI_USER_PGTABLE_AND_PCID_MASK), \reg
213 .macro SWITCH_TO_KERNEL_CR3 scratch_reg:req
214 ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI
215 mov %cr3, \scratch_reg
216 ADJUST_KERNEL_CR3 \scratch_reg
217 mov \scratch_reg, %cr3
221 #define THIS_CPU_user_pcid_flush_mask \
222 PER_CPU_VAR(cpu_tlbstate) + TLB_STATE_user_pcid_flush_mask
224 .macro SWITCH_TO_USER_CR3_NOSTACK scratch_reg:req scratch_reg2:req
225 ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI
226 mov %cr3, \scratch_reg
228 ALTERNATIVE "jmp .Lwrcr3_\@", "", X86_FEATURE_PCID
231 * Test if the ASID needs a flush.
233 movq \scratch_reg, \scratch_reg2
234 andq $(0x7FF), \scratch_reg /* mask ASID */
235 bt \scratch_reg, THIS_CPU_user_pcid_flush_mask
238 /* Flush needed, clear the bit */
239 btr \scratch_reg, THIS_CPU_user_pcid_flush_mask
240 movq \scratch_reg2, \scratch_reg
244 movq \scratch_reg2, \scratch_reg
245 SET_NOFLUSH_BIT \scratch_reg
248 /* Flip the ASID to the user version */
249 orq $(PTI_USER_PCID_MASK), \scratch_reg
252 /* Flip the PGD to the user version */
253 orq $(PTI_USER_PGTABLE_MASK), \scratch_reg
254 mov \scratch_reg, %cr3
258 .macro SWITCH_TO_USER_CR3_STACK scratch_reg:req
260 SWITCH_TO_USER_CR3_NOSTACK scratch_reg=\scratch_reg scratch_reg2=%rax
264 .macro SAVE_AND_SWITCH_TO_KERNEL_CR3 scratch_reg:req save_reg:req
265 ALTERNATIVE "jmp .Ldone_\@", "", X86_FEATURE_PTI
266 movq %cr3, \scratch_reg
267 movq \scratch_reg, \save_reg
269 * Test the user pagetable bit. If set, then the user page tables
270 * are active. If clear CR3 already has the kernel page table
273 bt $PTI_USER_PGTABLE_BIT, \scratch_reg
276 ADJUST_KERNEL_CR3 \scratch_reg
277 movq \scratch_reg, %cr3
282 .macro RESTORE_CR3 scratch_reg:req save_reg:req
283 ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI
285 ALTERNATIVE "jmp .Lwrcr3_\@", "", X86_FEATURE_PCID
288 * KERNEL pages can always resume with NOFLUSH as we do
291 bt $PTI_USER_PGTABLE_BIT, \save_reg
295 * Check if there's a pending flush for the user ASID we're
298 movq \save_reg, \scratch_reg
299 andq $(0x7FF), \scratch_reg
300 bt \scratch_reg, THIS_CPU_user_pcid_flush_mask
303 btr \scratch_reg, THIS_CPU_user_pcid_flush_mask
307 SET_NOFLUSH_BIT \save_reg
311 * The CR3 write could be avoided when not changing its value,
312 * but would require a CR3 read *and* a scratch register.
318 #else /* CONFIG_PAGE_TABLE_ISOLATION=n: */
320 .macro SWITCH_TO_KERNEL_CR3 scratch_reg:req
322 .macro SWITCH_TO_USER_CR3_NOSTACK scratch_reg:req scratch_reg2:req
324 .macro SWITCH_TO_USER_CR3_STACK scratch_reg:req
326 .macro SAVE_AND_SWITCH_TO_KERNEL_CR3 scratch_reg:req save_reg:req
328 .macro RESTORE_CR3 scratch_reg:req save_reg:req
334 * IBRS kernel mitigation for Spectre_v2.
336 * Assumes full context is established (PUSH_REGS, CR3 and GS) and it clobbers
337 * the regs it uses (AX, CX, DX). Must be called before the first RET
338 * instruction (NOTE! UNTRAIN_RET includes a RET instruction)
340 * The optional argument is used to save/restore the current value,
341 * which is used on the paranoid paths.
343 * Assumes x86_spec_ctrl_{base,current} to have SPEC_CTRL_IBRS set.
345 .macro IBRS_ENTER save_reg
346 ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_KERNEL_IBRS
347 movl $MSR_IA32_SPEC_CTRL, %ecx
354 test $SPEC_CTRL_IBRS, %eax
361 movq PER_CPU_VAR(x86_spec_ctrl_current), %rdx
369 * Similar to IBRS_ENTER, requires KERNEL GS,CR3 and clobbers (AX, CX, DX)
370 * regs. Must be called after the last RET.
372 .macro IBRS_EXIT save_reg
373 ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_KERNEL_IBRS
374 movl $MSR_IA32_SPEC_CTRL, %ecx
379 movq PER_CPU_VAR(x86_spec_ctrl_current), %rdx
380 andl $(~SPEC_CTRL_IBRS), %edx
390 * Mitigate Spectre v1 for conditional swapgs code paths.
392 * FENCE_SWAPGS_USER_ENTRY is used in the user entry swapgs code path, to
393 * prevent a speculative swapgs when coming from kernel space.
395 * FENCE_SWAPGS_KERNEL_ENTRY is used in the kernel entry non-swapgs code path,
396 * to prevent the swapgs from getting speculatively skipped when coming from
399 .macro FENCE_SWAPGS_USER_ENTRY
400 ALTERNATIVE "", "lfence", X86_FEATURE_FENCE_SWAPGS_USER
402 .macro FENCE_SWAPGS_KERNEL_ENTRY
403 ALTERNATIVE "", "lfence", X86_FEATURE_FENCE_SWAPGS_KERNEL
406 #endif /* CONFIG_X86_64 */
409 * This does 'call enter_from_user_mode' unless we can avoid it based on
410 * kernel config or using the static jump infrastructure.
412 .macro CALL_enter_from_user_mode
413 #ifdef CONFIG_CONTEXT_TRACKING
414 #ifdef HAVE_JUMP_LABEL
415 STATIC_JUMP_IF_FALSE .Lafter_call_\@, context_tracking_enabled, def=0
417 call enter_from_user_mode