1 /* SPDX-License-Identifier: GPL-2.0 */
2 #include <linux/jump_label.h>
3 #include <asm/unwind_hints.h>
4 #include <asm/cpufeatures.h>
5 #include <asm/page_types.h>
6 #include <asm/percpu.h>
7 #include <asm/asm-offsets.h>
8 #include <asm/processor-flags.h>
10 #include <asm/nospec-branch.h>
14 x86 function call convention, 64-bit:
15 -------------------------------------
16 arguments | callee-saved | extra caller-saved | return
17 [callee-clobbered] | | [callee-clobbered] |
18 ---------------------------------------------------------------------------
19 rdi rsi rdx rcx r8-9 | rbx rbp [*] r12-15 | r10-11 | rax, rdx [**]
21 ( rsp is obviously invariant across normal function calls. (gcc can 'merge'
22 functions when it sees tail-call optimization possibilities) rflags is
23 clobbered. Leftover arguments are passed over the stack frame.)
25 [*] In the frame-pointers case rbp is fixed to the stack frame.
27 [**] for struct return values wider than 64 bits the return convention is a
28 bit more complex: up to 128 bits width we return small structures
29 straight in rax, rdx. For structures larger than that (3 words or
30 larger) the caller puts a pointer to an on-stack return struct
31 [allocated in the caller's stack frame] into the first argument - i.e.
32 into rdi. All other arguments shift up by one in this case.
33 Fortunately this case is rare in the kernel.
35 For 32-bit we have the following conventions - kernel is built with
36 -mregparm=3 and -freg-struct-return:
38 x86 function calling convention, 32-bit:
39 ----------------------------------------
40 arguments | callee-saved | extra caller-saved | return
41 [callee-clobbered] | | [callee-clobbered] |
42 -------------------------------------------------------------------------
43 eax edx ecx | ebx edi esi ebp [*] | <none> | eax, edx [**]
45 ( here too esp is obviously invariant across normal function calls. eflags
46 is clobbered. Leftover arguments are passed over the stack frame. )
48 [*] In the frame-pointers case ebp is fixed to the stack frame.
50 [**] We build with -freg-struct-return, which on 32-bit means similar
51 semantics as on 64-bit: edx can be used for a second return value
52 (i.e. covering integer and structure sizes up to 64 bits) - after that
53 it gets more complex and more expensive: 3-word or larger struct returns
54 get done in the caller's frame and the pointer to the return struct goes
55 into regparm0, i.e. eax - the other arguments shift up and the
56 function's register parameters degenerate to regparm=2 in essence.
63 * 64-bit system call stack frame layout defines and helpers,
67 /* The layout forms the "struct pt_regs" on the stack: */
69 * C ABI says these regs are callee-preserved. They aren't saved on kernel entry
70 * unless syscall needs a complete, fully filled "struct pt_regs".
78 /* These regs are callee-clobbered. Always saved on kernel entry. */
89 * On syscall entry, this is syscall#. On CPU exception, this is error code.
90 * On hw interrupt, it's IRQ number:
93 /* Return frame for iretq */
100 #define SIZEOF_PTREGS 21*8
102 .macro PUSH_AND_CLEAR_REGS rdx=%rdx rax=%rax save_ret=0
104 pushq %rsi /* pt_regs->si */
105 movq 8(%rsp), %rsi /* temporarily store the return address in %rsi */
106 movq %rdi, 8(%rsp) /* pt_regs->di (overwriting original return address) */
108 pushq %rdi /* pt_regs->di */
109 pushq %rsi /* pt_regs->si */
111 pushq \rdx /* pt_regs->dx */
112 pushq %rcx /* pt_regs->cx */
113 pushq \rax /* pt_regs->ax */
114 pushq %r8 /* pt_regs->r8 */
115 pushq %r9 /* pt_regs->r9 */
116 pushq %r10 /* pt_regs->r10 */
117 pushq %r11 /* pt_regs->r11 */
118 pushq %rbx /* pt_regs->rbx */
119 pushq %rbp /* pt_regs->rbp */
120 pushq %r12 /* pt_regs->r12 */
121 pushq %r13 /* pt_regs->r13 */
122 pushq %r14 /* pt_regs->r14 */
123 pushq %r15 /* pt_regs->r15 */
127 pushq %rsi /* return address on top of stack */
131 * Sanitize registers of values that a speculation attack might
132 * otherwise want to exploit. The lower registers are likely clobbered
133 * well before they could be put to use in a speculative execution
136 xorl %edx, %edx /* nospec dx */
137 xorl %ecx, %ecx /* nospec cx */
138 xorl %r8d, %r8d /* nospec r8 */
139 xorl %r9d, %r9d /* nospec r9 */
140 xorl %r10d, %r10d /* nospec r10 */
141 xorl %r11d, %r11d /* nospec r11 */
142 xorl %ebx, %ebx /* nospec rbx */
143 xorl %ebp, %ebp /* nospec rbp */
144 xorl %r12d, %r12d /* nospec r12 */
145 xorl %r13d, %r13d /* nospec r13 */
146 xorl %r14d, %r14d /* nospec r14 */
147 xorl %r15d, %r15d /* nospec r15 */
151 .macro POP_REGS pop_rdi=1
171 #ifdef CONFIG_PAGE_TABLE_ISOLATION
174 * PAGE_TABLE_ISOLATION PGDs are 8k. Flip bit 12 to switch between the two
177 #define PTI_USER_PGTABLE_BIT PAGE_SHIFT
178 #define PTI_USER_PGTABLE_MASK (1 << PTI_USER_PGTABLE_BIT)
179 #define PTI_USER_PCID_BIT X86_CR3_PTI_PCID_USER_BIT
180 #define PTI_USER_PCID_MASK (1 << PTI_USER_PCID_BIT)
181 #define PTI_USER_PGTABLE_AND_PCID_MASK (PTI_USER_PCID_MASK | PTI_USER_PGTABLE_MASK)
183 .macro SET_NOFLUSH_BIT reg:req
184 bts $X86_CR3_PCID_NOFLUSH_BIT, \reg
187 .macro ADJUST_KERNEL_CR3 reg:req
188 ALTERNATIVE "", "SET_NOFLUSH_BIT \reg", X86_FEATURE_PCID
189 /* Clear PCID and "PAGE_TABLE_ISOLATION bit", point CR3 at kernel pagetables: */
190 andq $(~PTI_USER_PGTABLE_AND_PCID_MASK), \reg
193 .macro SWITCH_TO_KERNEL_CR3 scratch_reg:req
194 ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI
195 mov %cr3, \scratch_reg
196 ADJUST_KERNEL_CR3 \scratch_reg
197 mov \scratch_reg, %cr3
201 #define THIS_CPU_user_pcid_flush_mask \
202 PER_CPU_VAR(cpu_tlbstate) + TLB_STATE_user_pcid_flush_mask
204 .macro SWITCH_TO_USER_CR3_NOSTACK scratch_reg:req scratch_reg2:req
205 ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI
206 mov %cr3, \scratch_reg
208 ALTERNATIVE "jmp .Lwrcr3_\@", "", X86_FEATURE_PCID
211 * Test if the ASID needs a flush.
213 movq \scratch_reg, \scratch_reg2
214 andq $(0x7FF), \scratch_reg /* mask ASID */
215 bt \scratch_reg, THIS_CPU_user_pcid_flush_mask
218 /* Flush needed, clear the bit */
219 btr \scratch_reg, THIS_CPU_user_pcid_flush_mask
220 movq \scratch_reg2, \scratch_reg
224 movq \scratch_reg2, \scratch_reg
225 SET_NOFLUSH_BIT \scratch_reg
228 /* Flip the ASID to the user version */
229 orq $(PTI_USER_PCID_MASK), \scratch_reg
232 /* Flip the PGD to the user version */
233 orq $(PTI_USER_PGTABLE_MASK), \scratch_reg
234 mov \scratch_reg, %cr3
238 .macro SWITCH_TO_USER_CR3_STACK scratch_reg:req
240 SWITCH_TO_USER_CR3_NOSTACK scratch_reg=\scratch_reg scratch_reg2=%rax
244 .macro SAVE_AND_SWITCH_TO_KERNEL_CR3 scratch_reg:req save_reg:req
245 ALTERNATIVE "jmp .Ldone_\@", "", X86_FEATURE_PTI
246 movq %cr3, \scratch_reg
247 movq \scratch_reg, \save_reg
249 * Test the user pagetable bit. If set, then the user page tables
250 * are active. If clear CR3 already has the kernel page table
253 bt $PTI_USER_PGTABLE_BIT, \scratch_reg
256 ADJUST_KERNEL_CR3 \scratch_reg
257 movq \scratch_reg, %cr3
262 .macro RESTORE_CR3 scratch_reg:req save_reg:req
263 ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI
265 ALTERNATIVE "jmp .Lwrcr3_\@", "", X86_FEATURE_PCID
268 * KERNEL pages can always resume with NOFLUSH as we do
271 bt $PTI_USER_PGTABLE_BIT, \save_reg
275 * Check if there's a pending flush for the user ASID we're
278 movq \save_reg, \scratch_reg
279 andq $(0x7FF), \scratch_reg
280 bt \scratch_reg, THIS_CPU_user_pcid_flush_mask
283 btr \scratch_reg, THIS_CPU_user_pcid_flush_mask
287 SET_NOFLUSH_BIT \save_reg
291 * The CR3 write could be avoided when not changing its value,
292 * but would require a CR3 read *and* a scratch register.
298 #else /* CONFIG_PAGE_TABLE_ISOLATION=n: */
300 .macro SWITCH_TO_KERNEL_CR3 scratch_reg:req
302 .macro SWITCH_TO_USER_CR3_NOSTACK scratch_reg:req scratch_reg2:req
304 .macro SWITCH_TO_USER_CR3_STACK scratch_reg:req
306 .macro SAVE_AND_SWITCH_TO_KERNEL_CR3 scratch_reg:req save_reg:req
308 .macro RESTORE_CR3 scratch_reg:req save_reg:req
314 * IBRS kernel mitigation for Spectre_v2.
316 * Assumes full context is established (PUSH_REGS, CR3 and GS) and it clobbers
317 * the regs it uses (AX, CX, DX). Must be called before the first RET
318 * instruction (NOTE! UNTRAIN_RET includes a RET instruction)
320 * The optional argument is used to save/restore the current value,
321 * which is used on the paranoid paths.
323 * Assumes x86_spec_ctrl_{base,current} to have SPEC_CTRL_IBRS set.
325 .macro IBRS_ENTER save_reg
326 ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_KERNEL_IBRS
327 movl $MSR_IA32_SPEC_CTRL, %ecx
334 test $SPEC_CTRL_IBRS, %eax
341 movq PER_CPU_VAR(x86_spec_ctrl_current), %rdx
349 * Similar to IBRS_ENTER, requires KERNEL GS,CR3 and clobbers (AX, CX, DX)
350 * regs. Must be called after the last RET.
352 .macro IBRS_EXIT save_reg
353 ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_KERNEL_IBRS
354 movl $MSR_IA32_SPEC_CTRL, %ecx
359 movq PER_CPU_VAR(x86_spec_ctrl_current), %rdx
360 andl $(~SPEC_CTRL_IBRS), %edx
370 * Mitigate Spectre v1 for conditional swapgs code paths.
372 * FENCE_SWAPGS_USER_ENTRY is used in the user entry swapgs code path, to
373 * prevent a speculative swapgs when coming from kernel space.
375 * FENCE_SWAPGS_KERNEL_ENTRY is used in the kernel entry non-swapgs code path,
376 * to prevent the swapgs from getting speculatively skipped when coming from
379 .macro FENCE_SWAPGS_USER_ENTRY
380 ALTERNATIVE "", "lfence", X86_FEATURE_FENCE_SWAPGS_USER
382 .macro FENCE_SWAPGS_KERNEL_ENTRY
383 ALTERNATIVE "", "lfence", X86_FEATURE_FENCE_SWAPGS_KERNEL
386 .macro STACKLEAK_ERASE_NOCLOBBER
387 #ifdef CONFIG_GCC_PLUGIN_STACKLEAK
394 #endif /* CONFIG_X86_64 */
396 .macro STACKLEAK_ERASE
397 #ifdef CONFIG_GCC_PLUGIN_STACKLEAK
403 * This does 'call enter_from_user_mode' unless we can avoid it based on
404 * kernel config or using the static jump infrastructure.
406 .macro CALL_enter_from_user_mode
407 #ifdef CONFIG_CONTEXT_TRACKING
408 #ifdef CONFIG_JUMP_LABEL
409 STATIC_JUMP_IF_FALSE .Lafter_call_\@, context_tracking_enabled, def=0
411 call enter_from_user_mode
416 #ifdef CONFIG_PARAVIRT_XXL
417 #define GET_CR2_INTO(reg) GET_CR2_INTO_AX ; _ASM_MOV %_ASM_AX, reg
419 #define GET_CR2_INTO(reg) _ASM_MOV %cr2, reg