1 /* SPDX-License-Identifier: GPL-2.0 */
2 #include <linux/jump_label.h>
3 #include <asm/unwind_hints.h>
4 #include <asm/cpufeatures.h>
5 #include <asm/page_types.h>
6 #include <asm/percpu.h>
7 #include <asm/asm-offsets.h>
8 #include <asm/processor-flags.h>
12 x86 function call convention, 64-bit:
13 -------------------------------------
14 arguments | callee-saved | extra caller-saved | return
15 [callee-clobbered] | | [callee-clobbered] |
16 ---------------------------------------------------------------------------
17 rdi rsi rdx rcx r8-9 | rbx rbp [*] r12-15 | r10-11 | rax, rdx [**]
19 ( rsp is obviously invariant across normal function calls. (gcc can 'merge'
20 functions when it sees tail-call optimization possibilities) rflags is
21 clobbered. Leftover arguments are passed over the stack frame.)
23 [*] In the frame-pointers case rbp is fixed to the stack frame.
25 [**] for struct return values wider than 64 bits the return convention is a
26 bit more complex: up to 128 bits width we return small structures
27 straight in rax, rdx. For structures larger than that (3 words or
28 larger) the caller puts a pointer to an on-stack return struct
29 [allocated in the caller's stack frame] into the first argument - i.e.
30 into rdi. All other arguments shift up by one in this case.
31 Fortunately this case is rare in the kernel.
33 For 32-bit we have the following conventions - kernel is built with
34 -mregparm=3 and -freg-struct-return:
36 x86 function calling convention, 32-bit:
37 ----------------------------------------
38 arguments | callee-saved | extra caller-saved | return
39 [callee-clobbered] | | [callee-clobbered] |
40 -------------------------------------------------------------------------
41 eax edx ecx | ebx edi esi ebp [*] | <none> | eax, edx [**]
43 ( here too esp is obviously invariant across normal function calls. eflags
44 is clobbered. Leftover arguments are passed over the stack frame. )
46 [*] In the frame-pointers case ebp is fixed to the stack frame.
48 [**] We build with -freg-struct-return, which on 32-bit means similar
49 semantics as on 64-bit: edx can be used for a second return value
50 (i.e. covering integer and structure sizes up to 64 bits) - after that
51 it gets more complex and more expensive: 3-word or larger struct returns
52 get done in the caller's frame and the pointer to the return struct goes
53 into regparm0, i.e. eax - the other arguments shift up and the
54 function's register parameters degenerate to regparm=2 in essence.
61 * 64-bit system call stack frame layout defines and helpers,
65 /* The layout forms the "struct pt_regs" on the stack: */
67 * C ABI says these regs are callee-preserved. They aren't saved on kernel entry
68 * unless syscall needs a complete, fully filled "struct pt_regs".
76 /* These regs are callee-clobbered. Always saved on kernel entry. */
87 * On syscall entry, this is syscall#. On CPU exception, this is error code.
88 * On hw interrupt, it's IRQ number:
91 /* Return frame for iretq */
98 #define SIZEOF_PTREGS 21*8
100 .macro PUSH_AND_CLEAR_REGS rdx=%rdx rax=%rax save_ret=0
102 pushq %rsi /* pt_regs->si */
103 movq 8(%rsp), %rsi /* temporarily store the return address in %rsi */
104 movq %rdi, 8(%rsp) /* pt_regs->di (overwriting original return address) */
106 pushq %rdi /* pt_regs->di */
107 pushq %rsi /* pt_regs->si */
109 pushq \rdx /* pt_regs->dx */
110 pushq %rcx /* pt_regs->cx */
111 pushq \rax /* pt_regs->ax */
112 pushq %r8 /* pt_regs->r8 */
113 pushq %r9 /* pt_regs->r9 */
114 pushq %r10 /* pt_regs->r10 */
115 pushq %r11 /* pt_regs->r11 */
116 pushq %rbx /* pt_regs->rbx */
117 pushq %rbp /* pt_regs->rbp */
118 pushq %r12 /* pt_regs->r12 */
119 pushq %r13 /* pt_regs->r13 */
120 pushq %r14 /* pt_regs->r14 */
121 pushq %r15 /* pt_regs->r15 */
125 pushq %rsi /* return address on top of stack */
129 * Sanitize registers of values that a speculation attack might
130 * otherwise want to exploit. The lower registers are likely clobbered
131 * well before they could be put to use in a speculative execution
134 xorl %edx, %edx /* nospec dx */
135 xorl %ecx, %ecx /* nospec cx */
136 xorl %r8d, %r8d /* nospec r8 */
137 xorl %r9d, %r9d /* nospec r9 */
138 xorl %r10d, %r10d /* nospec r10 */
139 xorl %r11d, %r11d /* nospec r11 */
140 xorl %ebx, %ebx /* nospec rbx */
141 xorl %ebp, %ebp /* nospec rbp */
142 xorl %r12d, %r12d /* nospec r12 */
143 xorl %r13d, %r13d /* nospec r13 */
144 xorl %r14d, %r14d /* nospec r14 */
145 xorl %r15d, %r15d /* nospec r15 */
149 .macro POP_REGS pop_rdi=1 skip_r11rcx=0
178 * This is a sneaky trick to help the unwinder find pt_regs on the stack. The
179 * frame pointer is replaced with an encoded pointer to pt_regs. The encoding
180 * is just setting the LSB, which makes it an invalid stack address and is also
181 * a signal to the unwinder that it's a pt_regs pointer in disguise.
183 * NOTE: This macro must be used *after* PUSH_AND_CLEAR_REGS because it corrupts
186 .macro ENCODE_FRAME_POINTER ptregs_offset=0
187 #ifdef CONFIG_FRAME_POINTER
189 leaq \ptregs_offset(%rsp), %rbp
197 #ifdef CONFIG_PAGE_TABLE_ISOLATION
200 * PAGE_TABLE_ISOLATION PGDs are 8k. Flip bit 12 to switch between the two
203 #define PTI_USER_PGTABLE_BIT PAGE_SHIFT
204 #define PTI_USER_PGTABLE_MASK (1 << PTI_USER_PGTABLE_BIT)
205 #define PTI_USER_PCID_BIT X86_CR3_PTI_PCID_USER_BIT
206 #define PTI_USER_PCID_MASK (1 << PTI_USER_PCID_BIT)
207 #define PTI_USER_PGTABLE_AND_PCID_MASK (PTI_USER_PCID_MASK | PTI_USER_PGTABLE_MASK)
209 .macro SET_NOFLUSH_BIT reg:req
210 bts $X86_CR3_PCID_NOFLUSH_BIT, \reg
213 .macro ADJUST_KERNEL_CR3 reg:req
214 ALTERNATIVE "", "SET_NOFLUSH_BIT \reg", X86_FEATURE_PCID
215 /* Clear PCID and "PAGE_TABLE_ISOLATION bit", point CR3 at kernel pagetables: */
216 andq $(~PTI_USER_PGTABLE_AND_PCID_MASK), \reg
219 .macro SWITCH_TO_KERNEL_CR3 scratch_reg:req
220 ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI
221 mov %cr3, \scratch_reg
222 ADJUST_KERNEL_CR3 \scratch_reg
223 mov \scratch_reg, %cr3
227 #define THIS_CPU_user_pcid_flush_mask \
228 PER_CPU_VAR(cpu_tlbstate) + TLB_STATE_user_pcid_flush_mask
230 .macro SWITCH_TO_USER_CR3_NOSTACK scratch_reg:req scratch_reg2:req
231 ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI
232 mov %cr3, \scratch_reg
234 ALTERNATIVE "jmp .Lwrcr3_\@", "", X86_FEATURE_PCID
237 * Test if the ASID needs a flush.
239 movq \scratch_reg, \scratch_reg2
240 andq $(0x7FF), \scratch_reg /* mask ASID */
241 bt \scratch_reg, THIS_CPU_user_pcid_flush_mask
244 /* Flush needed, clear the bit */
245 btr \scratch_reg, THIS_CPU_user_pcid_flush_mask
246 movq \scratch_reg2, \scratch_reg
250 movq \scratch_reg2, \scratch_reg
251 SET_NOFLUSH_BIT \scratch_reg
254 /* Flip the ASID to the user version */
255 orq $(PTI_USER_PCID_MASK), \scratch_reg
258 /* Flip the PGD to the user version */
259 orq $(PTI_USER_PGTABLE_MASK), \scratch_reg
260 mov \scratch_reg, %cr3
264 .macro SWITCH_TO_USER_CR3_STACK scratch_reg:req
266 SWITCH_TO_USER_CR3_NOSTACK scratch_reg=\scratch_reg scratch_reg2=%rax
270 .macro SAVE_AND_SWITCH_TO_KERNEL_CR3 scratch_reg:req save_reg:req
271 ALTERNATIVE "jmp .Ldone_\@", "", X86_FEATURE_PTI
272 movq %cr3, \scratch_reg
273 movq \scratch_reg, \save_reg
275 * Test the user pagetable bit. If set, then the user page tables
276 * are active. If clear CR3 already has the kernel page table
279 bt $PTI_USER_PGTABLE_BIT, \scratch_reg
282 ADJUST_KERNEL_CR3 \scratch_reg
283 movq \scratch_reg, %cr3
288 .macro RESTORE_CR3 scratch_reg:req save_reg:req
289 ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI
291 ALTERNATIVE "jmp .Lwrcr3_\@", "", X86_FEATURE_PCID
294 * KERNEL pages can always resume with NOFLUSH as we do
297 bt $PTI_USER_PGTABLE_BIT, \save_reg
301 * Check if there's a pending flush for the user ASID we're
304 movq \save_reg, \scratch_reg
305 andq $(0x7FF), \scratch_reg
306 bt \scratch_reg, THIS_CPU_user_pcid_flush_mask
309 btr \scratch_reg, THIS_CPU_user_pcid_flush_mask
313 SET_NOFLUSH_BIT \save_reg
317 * The CR3 write could be avoided when not changing its value,
318 * but would require a CR3 read *and* a scratch register.
324 #else /* CONFIG_PAGE_TABLE_ISOLATION=n: */
326 .macro SWITCH_TO_KERNEL_CR3 scratch_reg:req
328 .macro SWITCH_TO_USER_CR3_NOSTACK scratch_reg:req scratch_reg2:req
330 .macro SWITCH_TO_USER_CR3_STACK scratch_reg:req
332 .macro SAVE_AND_SWITCH_TO_KERNEL_CR3 scratch_reg:req save_reg:req
334 .macro RESTORE_CR3 scratch_reg:req save_reg:req
340 * Mitigate Spectre v1 for conditional swapgs code paths.
342 * FENCE_SWAPGS_USER_ENTRY is used in the user entry swapgs code path, to
343 * prevent a speculative swapgs when coming from kernel space.
345 * FENCE_SWAPGS_KERNEL_ENTRY is used in the kernel entry non-swapgs code path,
346 * to prevent the swapgs from getting speculatively skipped when coming from
349 .macro FENCE_SWAPGS_USER_ENTRY
350 ALTERNATIVE "", "lfence", X86_FEATURE_FENCE_SWAPGS_USER
352 .macro FENCE_SWAPGS_KERNEL_ENTRY
353 ALTERNATIVE "", "lfence", X86_FEATURE_FENCE_SWAPGS_KERNEL
356 #endif /* CONFIG_X86_64 */
359 * This does 'call enter_from_user_mode' unless we can avoid it based on
360 * kernel config or using the static jump infrastructure.
362 .macro CALL_enter_from_user_mode
363 #ifdef CONFIG_CONTEXT_TRACKING
364 #ifdef HAVE_JUMP_LABEL
365 STATIC_JUMP_IF_FALSE .Lafter_call_\@, context_tracking_enabled, def=0
367 call enter_from_user_mode