1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
3 * Copyright 2011 Tilera Corporation. All Rights Reserved.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation, version 2.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
12 * NON INFRINGEMENT. See the GNU General Public License for
16 #ifndef __ARCH_INTERRUPTS_H__
17 #define __ARCH_INTERRUPTS_H__
20 /** Mask for an interrupt. */
22 /* Note: must handle breaking interrupts into high and low words manually. */
23 #define INT_MASK(intno) (1 << (intno))
25 #define INT_MASK(intno) (1ULL << (intno))
30 /** Where a given interrupt executes */
31 #define INTERRUPT_VECTOR(i, pl) (0xFC000000 + ((pl) << 24) + ((i) << 8))
33 /** Where to store a vector for a given interrupt. */
34 #define USER_INTERRUPT_VECTOR(i) INTERRUPT_VECTOR(i, 0)
36 /** The base address of user-level interrupts. */
37 #define USER_INTERRUPT_VECTOR_BASE INTERRUPT_VECTOR(0, 0)
40 /** Additional synthetic interrupt. */
41 #define INT_BREAKPOINT (63)
43 #define INT_MEM_ERROR 0
44 #define INT_SINGLE_STEP_3 1
45 #define INT_SINGLE_STEP_2 2
46 #define INT_SINGLE_STEP_1 3
47 #define INT_SINGLE_STEP_0 4
48 #define INT_IDN_COMPLETE 5
49 #define INT_UDN_COMPLETE 6
50 #define INT_ITLB_MISS 7
53 #define INT_IDN_ACCESS 10
54 #define INT_UDN_ACCESS 11
55 #define INT_SWINT_3 12
56 #define INT_SWINT_2 13
57 #define INT_SWINT_1 14
58 #define INT_SWINT_0 15
59 #define INT_ILL_TRANS 16
60 #define INT_UNALIGN_DATA 17
61 #define INT_DTLB_MISS 18
62 #define INT_DTLB_ACCESS 19
63 #define INT_IDN_FIREWALL 20
64 #define INT_UDN_FIREWALL 21
65 #define INT_TILE_TIMER 22
66 #define INT_AUX_TILE_TIMER 23
67 #define INT_IDN_TIMER 24
68 #define INT_UDN_TIMER 25
69 #define INT_IDN_AVAIL 26
70 #define INT_UDN_AVAIL 27
75 #define INT_PERF_COUNT 32
76 #define INT_AUX_PERF_COUNT 33
77 #define INT_INTCTRL_3 34
78 #define INT_INTCTRL_2 35
79 #define INT_INTCTRL_1 36
80 #define INT_INTCTRL_0 37
81 #define INT_BOOT_ACCESS 38
82 #define INT_WORLD_ACCESS 39
85 #define INT_DOUBLE_FAULT 42
87 #define NUM_INTERRUPTS 43
90 #define QUEUED_INTERRUPTS ( \
91 (1ULL << INT_MEM_ERROR) | \
92 (1ULL << INT_IDN_COMPLETE) | \
93 (1ULL << INT_UDN_COMPLETE) | \
94 (1ULL << INT_IDN_FIREWALL) | \
95 (1ULL << INT_UDN_FIREWALL) | \
96 (1ULL << INT_TILE_TIMER) | \
97 (1ULL << INT_AUX_TILE_TIMER) | \
98 (1ULL << INT_IDN_TIMER) | \
99 (1ULL << INT_UDN_TIMER) | \
100 (1ULL << INT_IDN_AVAIL) | \
101 (1ULL << INT_UDN_AVAIL) | \
102 (1ULL << INT_IPI_3) | \
103 (1ULL << INT_IPI_2) | \
104 (1ULL << INT_IPI_1) | \
105 (1ULL << INT_IPI_0) | \
106 (1ULL << INT_PERF_COUNT) | \
107 (1ULL << INT_AUX_PERF_COUNT) | \
108 (1ULL << INT_INTCTRL_3) | \
109 (1ULL << INT_INTCTRL_2) | \
110 (1ULL << INT_INTCTRL_1) | \
111 (1ULL << INT_INTCTRL_0) | \
112 (1ULL << INT_BOOT_ACCESS) | \
113 (1ULL << INT_WORLD_ACCESS) | \
114 (1ULL << INT_I_ASID) | \
115 (1ULL << INT_D_ASID) | \
116 (1ULL << INT_DOUBLE_FAULT) | \
118 #define NONQUEUED_INTERRUPTS ( \
119 (1ULL << INT_SINGLE_STEP_3) | \
120 (1ULL << INT_SINGLE_STEP_2) | \
121 (1ULL << INT_SINGLE_STEP_1) | \
122 (1ULL << INT_SINGLE_STEP_0) | \
123 (1ULL << INT_ITLB_MISS) | \
124 (1ULL << INT_ILL) | \
125 (1ULL << INT_GPV) | \
126 (1ULL << INT_IDN_ACCESS) | \
127 (1ULL << INT_UDN_ACCESS) | \
128 (1ULL << INT_SWINT_3) | \
129 (1ULL << INT_SWINT_2) | \
130 (1ULL << INT_SWINT_1) | \
131 (1ULL << INT_SWINT_0) | \
132 (1ULL << INT_ILL_TRANS) | \
133 (1ULL << INT_UNALIGN_DATA) | \
134 (1ULL << INT_DTLB_MISS) | \
135 (1ULL << INT_DTLB_ACCESS) | \
137 #define CRITICAL_MASKED_INTERRUPTS ( \
138 (1ULL << INT_MEM_ERROR) | \
139 (1ULL << INT_SINGLE_STEP_3) | \
140 (1ULL << INT_SINGLE_STEP_2) | \
141 (1ULL << INT_SINGLE_STEP_1) | \
142 (1ULL << INT_SINGLE_STEP_0) | \
143 (1ULL << INT_IDN_COMPLETE) | \
144 (1ULL << INT_UDN_COMPLETE) | \
145 (1ULL << INT_IDN_FIREWALL) | \
146 (1ULL << INT_UDN_FIREWALL) | \
147 (1ULL << INT_TILE_TIMER) | \
148 (1ULL << INT_AUX_TILE_TIMER) | \
149 (1ULL << INT_IDN_TIMER) | \
150 (1ULL << INT_UDN_TIMER) | \
151 (1ULL << INT_IDN_AVAIL) | \
152 (1ULL << INT_UDN_AVAIL) | \
153 (1ULL << INT_IPI_3) | \
154 (1ULL << INT_IPI_2) | \
155 (1ULL << INT_IPI_1) | \
156 (1ULL << INT_IPI_0) | \
157 (1ULL << INT_PERF_COUNT) | \
158 (1ULL << INT_AUX_PERF_COUNT) | \
159 (1ULL << INT_INTCTRL_3) | \
160 (1ULL << INT_INTCTRL_2) | \
161 (1ULL << INT_INTCTRL_1) | \
162 (1ULL << INT_INTCTRL_0) | \
164 #define CRITICAL_UNMASKED_INTERRUPTS ( \
165 (1ULL << INT_ITLB_MISS) | \
166 (1ULL << INT_ILL) | \
167 (1ULL << INT_GPV) | \
168 (1ULL << INT_IDN_ACCESS) | \
169 (1ULL << INT_UDN_ACCESS) | \
170 (1ULL << INT_SWINT_3) | \
171 (1ULL << INT_SWINT_2) | \
172 (1ULL << INT_SWINT_1) | \
173 (1ULL << INT_SWINT_0) | \
174 (1ULL << INT_ILL_TRANS) | \
175 (1ULL << INT_UNALIGN_DATA) | \
176 (1ULL << INT_DTLB_MISS) | \
177 (1ULL << INT_DTLB_ACCESS) | \
178 (1ULL << INT_BOOT_ACCESS) | \
179 (1ULL << INT_WORLD_ACCESS) | \
180 (1ULL << INT_I_ASID) | \
181 (1ULL << INT_D_ASID) | \
182 (1ULL << INT_DOUBLE_FAULT) | \
184 #define MASKABLE_INTERRUPTS ( \
185 (1ULL << INT_MEM_ERROR) | \
186 (1ULL << INT_SINGLE_STEP_3) | \
187 (1ULL << INT_SINGLE_STEP_2) | \
188 (1ULL << INT_SINGLE_STEP_1) | \
189 (1ULL << INT_SINGLE_STEP_0) | \
190 (1ULL << INT_IDN_COMPLETE) | \
191 (1ULL << INT_UDN_COMPLETE) | \
192 (1ULL << INT_IDN_FIREWALL) | \
193 (1ULL << INT_UDN_FIREWALL) | \
194 (1ULL << INT_TILE_TIMER) | \
195 (1ULL << INT_AUX_TILE_TIMER) | \
196 (1ULL << INT_IDN_TIMER) | \
197 (1ULL << INT_UDN_TIMER) | \
198 (1ULL << INT_IDN_AVAIL) | \
199 (1ULL << INT_UDN_AVAIL) | \
200 (1ULL << INT_IPI_3) | \
201 (1ULL << INT_IPI_2) | \
202 (1ULL << INT_IPI_1) | \
203 (1ULL << INT_IPI_0) | \
204 (1ULL << INT_PERF_COUNT) | \
205 (1ULL << INT_AUX_PERF_COUNT) | \
206 (1ULL << INT_INTCTRL_3) | \
207 (1ULL << INT_INTCTRL_2) | \
208 (1ULL << INT_INTCTRL_1) | \
209 (1ULL << INT_INTCTRL_0) | \
211 #define UNMASKABLE_INTERRUPTS ( \
212 (1ULL << INT_ITLB_MISS) | \
213 (1ULL << INT_ILL) | \
214 (1ULL << INT_GPV) | \
215 (1ULL << INT_IDN_ACCESS) | \
216 (1ULL << INT_UDN_ACCESS) | \
217 (1ULL << INT_SWINT_3) | \
218 (1ULL << INT_SWINT_2) | \
219 (1ULL << INT_SWINT_1) | \
220 (1ULL << INT_SWINT_0) | \
221 (1ULL << INT_ILL_TRANS) | \
222 (1ULL << INT_UNALIGN_DATA) | \
223 (1ULL << INT_DTLB_MISS) | \
224 (1ULL << INT_DTLB_ACCESS) | \
225 (1ULL << INT_BOOT_ACCESS) | \
226 (1ULL << INT_WORLD_ACCESS) | \
227 (1ULL << INT_I_ASID) | \
228 (1ULL << INT_D_ASID) | \
229 (1ULL << INT_DOUBLE_FAULT) | \
231 #define SYNC_INTERRUPTS ( \
232 (1ULL << INT_SINGLE_STEP_3) | \
233 (1ULL << INT_SINGLE_STEP_2) | \
234 (1ULL << INT_SINGLE_STEP_1) | \
235 (1ULL << INT_SINGLE_STEP_0) | \
236 (1ULL << INT_IDN_COMPLETE) | \
237 (1ULL << INT_UDN_COMPLETE) | \
238 (1ULL << INT_ITLB_MISS) | \
239 (1ULL << INT_ILL) | \
240 (1ULL << INT_GPV) | \
241 (1ULL << INT_IDN_ACCESS) | \
242 (1ULL << INT_UDN_ACCESS) | \
243 (1ULL << INT_SWINT_3) | \
244 (1ULL << INT_SWINT_2) | \
245 (1ULL << INT_SWINT_1) | \
246 (1ULL << INT_SWINT_0) | \
247 (1ULL << INT_ILL_TRANS) | \
248 (1ULL << INT_UNALIGN_DATA) | \
249 (1ULL << INT_DTLB_MISS) | \
250 (1ULL << INT_DTLB_ACCESS) | \
252 #define NON_SYNC_INTERRUPTS ( \
253 (1ULL << INT_MEM_ERROR) | \
254 (1ULL << INT_IDN_FIREWALL) | \
255 (1ULL << INT_UDN_FIREWALL) | \
256 (1ULL << INT_TILE_TIMER) | \
257 (1ULL << INT_AUX_TILE_TIMER) | \
258 (1ULL << INT_IDN_TIMER) | \
259 (1ULL << INT_UDN_TIMER) | \
260 (1ULL << INT_IDN_AVAIL) | \
261 (1ULL << INT_UDN_AVAIL) | \
262 (1ULL << INT_IPI_3) | \
263 (1ULL << INT_IPI_2) | \
264 (1ULL << INT_IPI_1) | \
265 (1ULL << INT_IPI_0) | \
266 (1ULL << INT_PERF_COUNT) | \
267 (1ULL << INT_AUX_PERF_COUNT) | \
268 (1ULL << INT_INTCTRL_3) | \
269 (1ULL << INT_INTCTRL_2) | \
270 (1ULL << INT_INTCTRL_1) | \
271 (1ULL << INT_INTCTRL_0) | \
272 (1ULL << INT_BOOT_ACCESS) | \
273 (1ULL << INT_WORLD_ACCESS) | \
274 (1ULL << INT_I_ASID) | \
275 (1ULL << INT_D_ASID) | \
276 (1ULL << INT_DOUBLE_FAULT) | \
278 #endif /* !__ASSEMBLER__ */
279 #endif /* !__ARCH_INTERRUPTS_H__ */