2 * Copyright 2010 Tilera Corporation. All Rights Reserved.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
15 #ifndef _ASM_TILE_IO_H
16 #define _ASM_TILE_IO_H
18 #include <linux/kernel.h>
19 #include <linux/bug.h>
22 /* Maximum PCI I/O space address supported. */
23 #define IO_SPACE_LIMIT 0xffffffff
26 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
29 #define xlate_dev_mem_ptr(p) __va(p)
32 * Convert a virtual cached pointer to an uncached pointer.
34 #define xlate_dev_kmem_ptr(p) p
37 * Change "struct page" to physical address.
39 #define page_to_phys(page) ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)
42 * Some places try to pass in an loff_t for PHYSADDR (?!), so we cast it to
43 * long before casting it to a pointer to avoid compiler warnings.
46 extern void __iomem *ioremap(resource_size_t offset, unsigned long size);
47 extern void __iomem *ioremap_prot(resource_size_t offset, unsigned long size,
49 extern void iounmap(volatile void __iomem *addr);
51 #define ioremap(physaddr, size) ((void __iomem *)(unsigned long)(physaddr))
52 #define iounmap(addr) ((void)0)
55 #define ioremap_nocache(physaddr, size) ioremap(physaddr, size)
56 #define ioremap_wc(physaddr, size) ioremap(physaddr, size)
57 #define ioremap_wt(physaddr, size) ioremap(physaddr, size)
58 #define ioremap_uc(physaddr, size) ioremap(physaddr, size)
59 #define ioremap_fullcache(physaddr, size) ioremap(physaddr, size)
63 /* Conversion between virtual and physical mappings. */
64 #define mm_ptov(addr) ((void *)phys_to_virt(addr))
65 #define mm_vtop(addr) ((unsigned long)virt_to_phys(addr))
70 * We use inline assembly to guarantee that the compiler does not
71 * split an access into multiple byte-sized accesses as it might
72 * sometimes do if a register data structure is marked "packed".
73 * Obviously on tile we can't tolerate such an access being
74 * actually unaligned, but we want to avoid the case where the
75 * compiler conservatively would generate multiple accesses even
76 * for an aligned read or write.
79 static inline u8 __raw_readb(const volatile void __iomem *addr)
81 return *(const volatile u8 __force *)addr;
84 static inline u16 __raw_readw(const volatile void __iomem *addr)
87 asm volatile("ld2u %0, %1" : "=r" (ret) : "r" (addr));
89 return le16_to_cpu(ret);
92 static inline u32 __raw_readl(const volatile void __iomem *addr)
95 /* Sign-extend to conform to u32 ABI sign-extension convention. */
96 asm volatile("ld4s %0, %1" : "=r" (ret) : "r" (addr));
98 return le32_to_cpu(ret);
101 static inline u64 __raw_readq(const volatile void __iomem *addr)
104 asm volatile("ld %0, %1" : "=r" (ret) : "r" (addr));
106 return le64_to_cpu(ret);
109 static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
111 *(volatile u8 __force *)addr = val;
114 static inline void __raw_writew(u16 val, volatile void __iomem *addr)
116 asm volatile("st2 %0, %1" :: "r" (addr), "r" (cpu_to_le16(val)));
119 static inline void __raw_writel(u32 val, volatile void __iomem *addr)
121 asm volatile("st4 %0, %1" :: "r" (addr), "r" (cpu_to_le32(val)));
124 static inline void __raw_writeq(u64 val, volatile void __iomem *addr)
126 asm volatile("st %0, %1" :: "r" (addr), "r" (cpu_to_le64(val)));
130 * The on-chip I/O hardware on tilegx is configured with VA=PA for the
131 * kernel's PA range. The low-level APIs and field names use "va" and
132 * "void *" nomenclature, to be consistent with the general notion
133 * that the addresses in question are virtualizable, but in the kernel
134 * context we are actually manipulating PA values. (In other contexts,
135 * e.g. access from user space, we do in fact use real virtual addresses
136 * in the va fields.) To allow readers of the code to understand what's
137 * happening, we direct their attention to this comment by using the
138 * following two functions that just duplicate __va() and __pa().
140 typedef unsigned long tile_io_addr_t;
141 static inline tile_io_addr_t va_to_tile_io_addr(void *va)
143 BUILD_BUG_ON(sizeof(phys_addr_t) != sizeof(tile_io_addr_t));
146 static inline void *tile_io_addr_to_va(tile_io_addr_t tile_io_addr)
148 return __va(tile_io_addr);
151 #else /* CHIP_HAS_MMIO() */
155 extern u8 _tile_readb(unsigned long addr);
156 extern u16 _tile_readw(unsigned long addr);
157 extern u32 _tile_readl(unsigned long addr);
158 extern u64 _tile_readq(unsigned long addr);
159 extern void _tile_writeb(u8 val, unsigned long addr);
160 extern void _tile_writew(u16 val, unsigned long addr);
161 extern void _tile_writel(u32 val, unsigned long addr);
162 extern void _tile_writeq(u64 val, unsigned long addr);
164 #define __raw_readb(addr) _tile_readb((unsigned long)(addr))
165 #define __raw_readw(addr) _tile_readw((unsigned long)(addr))
166 #define __raw_readl(addr) _tile_readl((unsigned long)(addr))
167 #define __raw_readq(addr) _tile_readq((unsigned long)(addr))
168 #define __raw_writeb(val, addr) _tile_writeb(val, (unsigned long)(addr))
169 #define __raw_writew(val, addr) _tile_writew(val, (unsigned long)(addr))
170 #define __raw_writel(val, addr) _tile_writel(val, (unsigned long)(addr))
171 #define __raw_writeq(val, addr) _tile_writeq(val, (unsigned long)(addr))
173 #else /* CONFIG_PCI */
176 * The tilepro architecture does not support IOMEM unless PCI is enabled.
177 * Unfortunately we can't yet simply not declare these methods,
178 * since some generic code that compiles into the kernel, but
179 * we never run, uses them unconditionally.
182 static inline int iomem_panic(void)
184 panic("readb/writeb and friends do not exist on tile without PCI");
188 static inline u8 readb(unsigned long addr)
190 return iomem_panic();
193 static inline u16 _readw(unsigned long addr)
195 return iomem_panic();
198 static inline u32 readl(unsigned long addr)
200 return iomem_panic();
203 static inline u64 readq(unsigned long addr)
205 return iomem_panic();
208 static inline void writeb(u8 val, unsigned long addr)
213 static inline void writew(u16 val, unsigned long addr)
218 static inline void writel(u32 val, unsigned long addr)
223 static inline void writeq(u64 val, unsigned long addr)
228 #endif /* CONFIG_PCI */
230 #endif /* CHIP_HAS_MMIO() */
232 #define readb __raw_readb
233 #define readw __raw_readw
234 #define readl __raw_readl
235 #define readq __raw_readq
236 #define writeb __raw_writeb
237 #define writew __raw_writew
238 #define writel __raw_writel
239 #define writeq __raw_writeq
241 #define readb_relaxed readb
242 #define readw_relaxed readw
243 #define readl_relaxed readl
244 #define readq_relaxed readq
245 #define writeb_relaxed writeb
246 #define writew_relaxed writew
247 #define writel_relaxed writel
248 #define writeq_relaxed writeq
250 #define ioread8 readb
251 #define ioread16 readw
252 #define ioread32 readl
253 #define ioread64 readq
254 #define iowrite8 writeb
255 #define iowrite16 writew
256 #define iowrite32 writel
257 #define iowrite64 writeq
259 #if CHIP_HAS_MMIO() || defined(CONFIG_PCI)
261 static inline void memset_io(volatile void *dst, int val, size_t len)
264 BUG_ON((unsigned long)dst & 0x3);
265 val = (val & 0xff) * 0x01010101;
266 for (x = 0; x < len; x += 4)
267 writel(val, dst + x);
270 static inline void memcpy_fromio(void *dst, const volatile void __iomem *src,
274 BUG_ON((unsigned long)src & 0x3);
275 for (x = 0; x < len; x += 4)
276 *(u32 *)(dst + x) = readl(src + x);
279 static inline void memcpy_toio(volatile void __iomem *dst, const void *src,
283 BUG_ON((unsigned long)dst & 0x3);
284 for (x = 0; x < len; x += 4)
285 writel(*(u32 *)(src + x), dst + x);
290 #if CHIP_HAS_MMIO() && defined(CONFIG_TILE_PCI_IO)
292 static inline u8 inb(unsigned long addr)
294 return readb((volatile void __iomem *) addr);
297 static inline u16 inw(unsigned long addr)
299 return readw((volatile void __iomem *) addr);
302 static inline u32 inl(unsigned long addr)
304 return readl((volatile void __iomem *) addr);
307 static inline void outb(u8 b, unsigned long addr)
309 writeb(b, (volatile void __iomem *) addr);
312 static inline void outw(u16 b, unsigned long addr)
314 writew(b, (volatile void __iomem *) addr);
317 static inline void outl(u32 b, unsigned long addr)
319 writel(b, (volatile void __iomem *) addr);
322 static inline void insb(unsigned long addr, void *buffer, int count)
333 static inline void insw(unsigned long addr, void *buffer, int count)
344 static inline void insl(unsigned long addr, void *buffer, int count)
355 static inline void outsb(unsigned long addr, const void *buffer, int count)
358 const u8 *buf = buffer;
365 static inline void outsw(unsigned long addr, const void *buffer, int count)
368 const u16 *buf = buffer;
375 static inline void outsl(unsigned long addr, const void *buffer, int count)
378 const u32 *buf = buffer;
385 extern void __iomem *ioport_map(unsigned long port, unsigned int len);
386 extern void ioport_unmap(void __iomem *addr);
391 * The TilePro architecture does not support IOPORT, even with PCI.
392 * Unfortunately we can't yet simply not declare these methods,
393 * since some generic code that compiles into the kernel, but
394 * we never run, uses them unconditionally.
397 static inline long ioport_panic(void)
400 panic("PCI IO space support is disabled. Configure the kernel with CONFIG_TILE_PCI_IO to enable it");
402 panic("inb/outb and friends do not exist on tile");
407 static inline void __iomem *ioport_map(unsigned long port, unsigned int len)
409 pr_info("ioport_map: mapping IO resources is unsupported on tile\n");
413 static inline void ioport_unmap(void __iomem *addr)
418 static inline u8 inb(unsigned long addr)
420 return ioport_panic();
423 static inline u16 inw(unsigned long addr)
425 return ioport_panic();
428 static inline u32 inl(unsigned long addr)
430 return ioport_panic();
433 static inline void outb(u8 b, unsigned long addr)
438 static inline void outw(u16 b, unsigned long addr)
443 static inline void outl(u32 b, unsigned long addr)
448 static inline void insb(unsigned long addr, void *buffer, int count)
453 static inline void insw(unsigned long addr, void *buffer, int count)
458 static inline void insl(unsigned long addr, void *buffer, int count)
463 static inline void outsb(unsigned long addr, const void *buffer, int count)
468 static inline void outsw(unsigned long addr, const void *buffer, int count)
473 static inline void outsl(unsigned long addr, const void *buffer, int count)
478 #endif /* CHIP_HAS_MMIO() && defined(CONFIG_TILE_PCI_IO) */
480 #define inb_p(addr) inb(addr)
481 #define inw_p(addr) inw(addr)
482 #define inl_p(addr) inl(addr)
483 #define outb_p(x, addr) outb((x), (addr))
484 #define outw_p(x, addr) outw((x), (addr))
485 #define outl_p(x, addr) outl((x), (addr))
487 #define ioread16be(addr) be16_to_cpu(ioread16(addr))
488 #define ioread32be(addr) be32_to_cpu(ioread32(addr))
489 #define iowrite16be(v, addr) iowrite16(be16_to_cpu(v), (addr))
490 #define iowrite32be(v, addr) iowrite32(be32_to_cpu(v), (addr))
492 #define ioread8_rep(p, dst, count) \
493 insb((unsigned long) (p), (dst), (count))
494 #define ioread16_rep(p, dst, count) \
495 insw((unsigned long) (p), (dst), (count))
496 #define ioread32_rep(p, dst, count) \
497 insl((unsigned long) (p), (dst), (count))
499 #define iowrite8_rep(p, src, count) \
500 outsb((unsigned long) (p), (src), (count))
501 #define iowrite16_rep(p, src, count) \
502 outsw((unsigned long) (p), (src), (count))
503 #define iowrite32_rep(p, src, count) \
504 outsl((unsigned long) (p), (src), (count))
506 #define virt_to_bus virt_to_phys
507 #define bus_to_virt phys_to_virt
509 #endif /* _ASM_TILE_IO_H */