2 * Copyright 2012 Tilera Corporation. All Rights Reserved.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
15 /* Machine-generated file; do not edit. */
17 #ifndef __ARCH_TRIO_PCIE_INTFC_H__
18 #define __ARCH_TRIO_PCIE_INTFC_H__
21 #include <arch/trio_pcie_intfc_def.h>
27 * Configuration of the PCIe Port
35 #ifndef __BIG_ENDIAN__
36 /* Provides the state of the strapping pins for this port. */
37 uint_reg_t strap_state : 3;
39 uint_reg_t __reserved_0 : 1;
41 * When 1, the device type will be overridden using OVD_DEV_TYPE_VAL.
42 * When 0, the device type is determined based on the STRAP_STATE.
44 uint_reg_t ovd_dev_type : 1;
45 /* Provides the device type when OVD_DEV_TYPE is 1. */
46 uint_reg_t ovd_dev_type_val : 4;
47 /* Determines how link is trained. */
48 uint_reg_t train_mode : 2;
50 uint_reg_t __reserved_1 : 1;
52 * For PCIe, used to flip physical RX lanes that were not properly wired.
53 * This is not the same as lane reversal which is handled automatically
54 * during link training. When 0, RX Lane0 must be wired to the link
55 * partner (either to its Lane0 or it's LaneN). When RX_LANE_FLIP is 1,
56 * the highest numbered lane for this port becomes Lane0 and Lane0 does
57 * NOT have to be wired to the link partner.
59 uint_reg_t rx_lane_flip : 1;
61 * For PCIe, used to flip physical TX lanes that were not properly wired.
62 * This is not the same as lane reversal which is handled automatically
63 * during link training. When 0, TX Lane0 must be wired to the link
64 * partner (either to its Lane0 or it's LaneN). When TX_LANE_FLIP is 1,
65 * the highest numbered lane for this port becomes Lane0 and Lane0 does
66 * NOT have to be wired to the link partner.
68 uint_reg_t tx_lane_flip : 1;
70 * For StreamIO port, configures the width of the port when TRAIN_MODE is
73 uint_reg_t stream_width : 2;
75 * For StreamIO port, configures the rate of the port when TRAIN_MODE is
78 uint_reg_t stream_rate : 2;
80 uint_reg_t __reserved_2 : 46;
81 #else /* __BIG_ENDIAN__ */
82 uint_reg_t __reserved_2 : 46;
83 uint_reg_t stream_rate : 2;
84 uint_reg_t stream_width : 2;
85 uint_reg_t tx_lane_flip : 1;
86 uint_reg_t rx_lane_flip : 1;
87 uint_reg_t __reserved_1 : 1;
88 uint_reg_t train_mode : 2;
89 uint_reg_t ovd_dev_type_val : 4;
90 uint_reg_t ovd_dev_type : 1;
91 uint_reg_t __reserved_0 : 1;
92 uint_reg_t strap_state : 3;
97 } TRIO_PCIE_INTFC_PORT_CONFIG_t;
101 * Status of the PCIe Port. This register applies to the StreamIO port when
102 * StreamIO is enabled.
110 #ifndef __BIG_ENDIAN__
112 * Indicates the DL state of the port. When 1, the port is up and ready
113 * to receive traffic.
115 uint_reg_t dl_up : 1;
117 * Indicates the number of times the link has gone down. Clears on read.
119 uint_reg_t dl_down_cnt : 7;
120 /* Indicates the SERDES PLL has spun up and is providing a valid clock. */
121 uint_reg_t clock_ready : 1;
123 uint_reg_t __reserved_0 : 7;
124 /* Device revision ID. */
125 uint_reg_t device_rev : 8;
126 /* Link state (PCIe). */
127 uint_reg_t ltssm_state : 6;
128 /* Link power management state (PCIe). */
129 uint_reg_t pm_state : 3;
131 uint_reg_t __reserved_1 : 31;
132 #else /* __BIG_ENDIAN__ */
133 uint_reg_t __reserved_1 : 31;
134 uint_reg_t pm_state : 3;
135 uint_reg_t ltssm_state : 6;
136 uint_reg_t device_rev : 8;
137 uint_reg_t __reserved_0 : 7;
138 uint_reg_t clock_ready : 1;
139 uint_reg_t dl_down_cnt : 7;
140 uint_reg_t dl_up : 1;
145 } TRIO_PCIE_INTFC_PORT_STATUS_t;
148 * Transmit FIFO Control.
149 * Contains TX FIFO thresholds. These registers are for diagnostics purposes
150 * only. Changing these values causes undefined behavior.
158 #ifndef __BIG_ENDIAN__
160 * Almost-Empty level for TX0 data. Typically set to at least
161 * roundup(38.0*M/N) where N=tclk frequency and M=MAC symbol rate in MHz
162 * for a x4 port (250MHz).
164 uint_reg_t tx0_data_ae_lvl : 7;
166 uint_reg_t __reserved_0 : 1;
167 /* Almost-Empty level for TX1 data. */
168 uint_reg_t tx1_data_ae_lvl : 7;
170 uint_reg_t __reserved_1 : 1;
171 /* Almost-Full level for TX0 data. */
172 uint_reg_t tx0_data_af_lvl : 7;
174 uint_reg_t __reserved_2 : 1;
175 /* Almost-Full level for TX1 data. */
176 uint_reg_t tx1_data_af_lvl : 7;
178 uint_reg_t __reserved_3 : 1;
179 /* Almost-Full level for TX0 info. */
180 uint_reg_t tx0_info_af_lvl : 5;
182 uint_reg_t __reserved_4 : 3;
183 /* Almost-Full level for TX1 info. */
184 uint_reg_t tx1_info_af_lvl : 5;
186 uint_reg_t __reserved_5 : 3;
188 * This register provides performance adjustment for high bandwidth
189 * flows. The MAC will assert almost-full to TRIO if non-posted credits
190 * fall below this level. Note that setting this larger than the initial
191 * PORT_CREDIT.NPH value will cause READS to never be sent. If the
192 * initial credit value from the link partner is smaller than this value
193 * when the link comes up, the value will be reset to the initial credit
194 * value to prevent lockup.
196 uint_reg_t min_np_credits : 8;
198 * This register provides performance adjustment for high bandwidth
199 * flows. The MAC will assert almost-full to TRIO if posted credits fall
200 * below this level. Note that setting this larger than the initial
201 * PORT_CREDIT.PH value will cause WRITES to never be sent. If the
202 * initial credit value from the link partner is smaller than this value
203 * when the link comes up, the value will be reset to the initial credit
204 * value to prevent lockup.
206 uint_reg_t min_p_credits : 8;
207 #else /* __BIG_ENDIAN__ */
208 uint_reg_t min_p_credits : 8;
209 uint_reg_t min_np_credits : 8;
210 uint_reg_t __reserved_5 : 3;
211 uint_reg_t tx1_info_af_lvl : 5;
212 uint_reg_t __reserved_4 : 3;
213 uint_reg_t tx0_info_af_lvl : 5;
214 uint_reg_t __reserved_3 : 1;
215 uint_reg_t tx1_data_af_lvl : 7;
216 uint_reg_t __reserved_2 : 1;
217 uint_reg_t tx0_data_af_lvl : 7;
218 uint_reg_t __reserved_1 : 1;
219 uint_reg_t tx1_data_ae_lvl : 7;
220 uint_reg_t __reserved_0 : 1;
221 uint_reg_t tx0_data_ae_lvl : 7;
226 } TRIO_PCIE_INTFC_TX_FIFO_CTL_t;
227 #endif /* !defined(__ASSEMBLER__) */
229 #endif /* !defined(__ARCH_TRIO_PCIE_INTFC_H__) */