1 #include <linux/moduleloader.h>
2 #include <linux/workqueue.h>
3 #include <linux/netdevice.h>
4 #include <linux/filter.h>
5 #include <linux/cache.h>
6 #include <linux/if_vlan.h>
8 #include <asm/cacheflush.h>
9 #include <asm/ptrace.h>
13 static inline bool is_simm13(unsigned int value)
15 return value + 0x1000 < 0x2000;
18 static void bpf_flush_icache(void *start_, void *end_)
21 /* Cheetah's I-cache is fully coherent. */
22 if (tlb_type == spitfire) {
23 unsigned long start = (unsigned long) start_;
24 unsigned long end = (unsigned long) end_;
27 end = (end + 7UL) & ~7UL;
36 #define SEEN_DATAREF 1 /* might call external helpers */
37 #define SEEN_XREG 2 /* ebx is used */
38 #define SEEN_MEM 4 /* use mem[] for temporary storage */
40 #define S13(X) ((X) & 0x1fff)
41 #define IMMED 0x00002000
42 #define RD(X) ((X) << 25)
43 #define RS1(X) ((X) << 14)
45 #define OP(X) ((X) << 30)
46 #define OP2(X) ((X) << 22)
47 #define OP3(X) ((X) << 19)
48 #define COND(X) ((X) << 25)
50 #define F2(X, Y) (OP(X) | OP2(Y))
51 #define F3(X, Y) (OP(X) | OP3(Y))
53 #define CONDN COND(0x0)
54 #define CONDE COND(0x1)
55 #define CONDLE COND(0x2)
56 #define CONDL COND(0x3)
57 #define CONDLEU COND(0x4)
58 #define CONDCS COND(0x5)
59 #define CONDNEG COND(0x6)
60 #define CONDVC COND(0x7)
61 #define CONDA COND(0x8)
62 #define CONDNE COND(0x9)
63 #define CONDG COND(0xa)
64 #define CONDGE COND(0xb)
65 #define CONDGU COND(0xc)
66 #define CONDCC COND(0xd)
67 #define CONDPOS COND(0xe)
68 #define CONDVS COND(0xf)
70 #define CONDGEU CONDCC
73 #define WDISP22(X) (((X) >> 2) & 0x3fffff)
75 #define BA (F2(0, 2) | CONDA)
76 #define BGU (F2(0, 2) | CONDGU)
77 #define BLEU (F2(0, 2) | CONDLEU)
78 #define BGEU (F2(0, 2) | CONDGEU)
79 #define BLU (F2(0, 2) | CONDLU)
80 #define BE (F2(0, 2) | CONDE)
81 #define BNE (F2(0, 2) | CONDNE)
84 #define BE_PTR (F2(0, 1) | CONDE | (2 << 20))
89 #define SETHI(K, REG) \
90 (F2(0, 0x4) | RD(REG) | (((K) >> 10) & 0x3fffff))
91 #define OR_LO(K, REG) \
92 (F3(2, 0x02) | IMMED | RS1(REG) | ((K) & 0x3ff) | RD(REG))
94 #define ADD F3(2, 0x00)
95 #define AND F3(2, 0x01)
96 #define ANDCC F3(2, 0x11)
97 #define OR F3(2, 0x02)
98 #define XOR F3(2, 0x03)
99 #define SUB F3(2, 0x04)
100 #define SUBCC F3(2, 0x14)
101 #define MUL F3(2, 0x0a) /* umul */
102 #define DIV F3(2, 0x0e) /* udiv */
103 #define SLL F3(2, 0x25)
104 #define SRL F3(2, 0x26)
105 #define JMPL F3(2, 0x38)
107 #define BR F2(0, 0x01)
108 #define RD_Y F3(2, 0x28)
109 #define WR_Y F3(2, 0x30)
111 #define LD32 F3(3, 0x00)
112 #define LD8 F3(3, 0x01)
113 #define LD16 F3(3, 0x02)
114 #define LD64 F3(3, 0x0b)
115 #define ST32 F3(3, 0x04)
117 #ifdef CONFIG_SPARC64
119 #define BASE_STACKFRAME 176
122 #define BASE_STACKFRAME 96
125 #define LD32I (LD32 | IMMED)
126 #define LD8I (LD8 | IMMED)
127 #define LD16I (LD16 | IMMED)
128 #define LD64I (LD64 | IMMED)
129 #define LDPTRI (LDPTR | IMMED)
130 #define ST32I (ST32 | IMMED)
134 *prog++ = SETHI(0, G0); \
138 do { /* sub %g0, r_A, r_A */ \
139 *prog++ = SUB | RS1(G0) | RS2(r_A) | RD(r_A); \
142 #define emit_reg_move(FROM, TO) \
143 do { /* or %g0, FROM, TO */ \
144 *prog++ = OR | RS1(G0) | RS2(FROM) | RD(TO); \
147 #define emit_clear(REG) \
148 do { /* or %g0, %g0, REG */ \
149 *prog++ = OR | RS1(G0) | RS2(G0) | RD(REG); \
152 #define emit_set_const(K, REG) \
153 do { /* sethi %hi(K), REG */ \
154 *prog++ = SETHI(K, REG); \
155 /* or REG, %lo(K), REG */ \
156 *prog++ = OR_LO(K, REG); \
163 #define emit_alu_X(OPCODE) \
166 *prog++ = OPCODE | RS1(r_A) | RS2(r_X) | RD(r_A); \
175 * sethi %hi(K), r_TMP
176 * or r_TMP, %lo(K), r_TMP
179 * depending upon whether K fits in a signed 13-bit
180 * immediate instruction field. Emit nothing if K
183 #define emit_alu_K(OPCODE, K) \
185 if (K || OPCODE == AND || OPCODE == MUL) { \
186 unsigned int _insn = OPCODE; \
187 _insn |= RS1(r_A) | RD(r_A); \
188 if (is_simm13(K)) { \
189 *prog++ = _insn | IMMED | S13(K); \
191 emit_set_const(K, r_TMP); \
192 *prog++ = _insn | RS2(r_TMP); \
197 #define emit_loadimm(K, DEST) \
199 if (is_simm13(K)) { \
200 /* or %g0, K, DEST */ \
201 *prog++ = OR | IMMED | RS1(G0) | S13(K) | RD(DEST); \
203 emit_set_const(K, DEST); \
207 #define emit_loadptr(BASE, STRUCT, FIELD, DEST) \
208 do { unsigned int _off = offsetof(STRUCT, FIELD); \
209 BUILD_BUG_ON(FIELD_SIZEOF(STRUCT, FIELD) != sizeof(void *)); \
210 *prog++ = LDPTRI | RS1(BASE) | S13(_off) | RD(DEST); \
213 #define emit_load32(BASE, STRUCT, FIELD, DEST) \
214 do { unsigned int _off = offsetof(STRUCT, FIELD); \
215 BUILD_BUG_ON(FIELD_SIZEOF(STRUCT, FIELD) != sizeof(u32)); \
216 *prog++ = LD32I | RS1(BASE) | S13(_off) | RD(DEST); \
219 #define emit_load16(BASE, STRUCT, FIELD, DEST) \
220 do { unsigned int _off = offsetof(STRUCT, FIELD); \
221 BUILD_BUG_ON(FIELD_SIZEOF(STRUCT, FIELD) != sizeof(u16)); \
222 *prog++ = LD16I | RS1(BASE) | S13(_off) | RD(DEST); \
225 #define __emit_load8(BASE, STRUCT, FIELD, DEST) \
226 do { unsigned int _off = offsetof(STRUCT, FIELD); \
227 *prog++ = LD8I | RS1(BASE) | S13(_off) | RD(DEST); \
230 #define emit_load8(BASE, STRUCT, FIELD, DEST) \
231 do { BUILD_BUG_ON(FIELD_SIZEOF(STRUCT, FIELD) != sizeof(u8)); \
232 __emit_load8(BASE, STRUCT, FIELD, DEST); \
235 #ifdef CONFIG_SPARC64
236 #define BIAS (STACK_BIAS - 4)
241 #define emit_ldmem(OFF, DEST) \
242 do { *prog++ = LD32I | RS1(SP) | S13(BIAS - (OFF)) | RD(DEST); \
245 #define emit_stmem(OFF, SRC) \
246 do { *prog++ = ST32I | RS1(SP) | S13(BIAS - (OFF)) | RD(SRC); \
250 #ifdef CONFIG_SPARC64
251 #define emit_load_cpu(REG) \
252 emit_load16(G6, struct thread_info, cpu, REG)
254 #define emit_load_cpu(REG) \
255 emit_load32(G6, struct thread_info, cpu, REG)
258 #define emit_load_cpu(REG) emit_clear(REG)
261 #define emit_skb_loadptr(FIELD, DEST) \
262 emit_loadptr(r_SKB, struct sk_buff, FIELD, DEST)
263 #define emit_skb_load32(FIELD, DEST) \
264 emit_load32(r_SKB, struct sk_buff, FIELD, DEST)
265 #define emit_skb_load16(FIELD, DEST) \
266 emit_load16(r_SKB, struct sk_buff, FIELD, DEST)
267 #define __emit_skb_load8(FIELD, DEST) \
268 __emit_load8(r_SKB, struct sk_buff, FIELD, DEST)
269 #define emit_skb_load8(FIELD, DEST) \
270 emit_load8(r_SKB, struct sk_buff, FIELD, DEST)
272 #define emit_jmpl(BASE, IMM_OFF, LREG) \
273 *prog++ = (JMPL | IMMED | RS1(BASE) | S13(IMM_OFF) | RD(LREG))
275 #define emit_call(FUNC) \
276 do { void *_here = image + addrs[i] - 8; \
277 unsigned int _off = (void *)(FUNC) - _here; \
278 *prog++ = CALL | (((_off) >> 2) & 0x3fffffff); \
282 #define emit_branch(BR_OPC, DEST) \
283 do { unsigned int _here = addrs[i] - 8; \
284 *prog++ = BR_OPC | WDISP22((DEST) - _here); \
287 #define emit_branch_off(BR_OPC, OFF) \
288 do { *prog++ = BR_OPC | WDISP22(OFF); \
291 #define emit_jump(DEST) emit_branch(BA, DEST)
293 #define emit_read_y(REG) *prog++ = RD_Y | RD(REG)
294 #define emit_write_y(REG) *prog++ = WR_Y | IMMED | RS1(REG) | S13(0)
296 #define emit_cmp(R1, R2) \
297 *prog++ = (SUBCC | RS1(R1) | RS2(R2) | RD(G0))
299 #define emit_cmpi(R1, IMM) \
300 *prog++ = (SUBCC | IMMED | RS1(R1) | S13(IMM) | RD(G0));
302 #define emit_btst(R1, R2) \
303 *prog++ = (ANDCC | RS1(R1) | RS2(R2) | RD(G0))
305 #define emit_btsti(R1, IMM) \
306 *prog++ = (ANDCC | IMMED | RS1(R1) | S13(IMM) | RD(G0));
308 #define emit_sub(R1, R2, R3) \
309 *prog++ = (SUB | RS1(R1) | RS2(R2) | RD(R3))
311 #define emit_subi(R1, IMM, R3) \
312 *prog++ = (SUB | IMMED | RS1(R1) | S13(IMM) | RD(R3))
314 #define emit_add(R1, R2, R3) \
315 *prog++ = (ADD | RS1(R1) | RS2(R2) | RD(R3))
317 #define emit_addi(R1, IMM, R3) \
318 *prog++ = (ADD | IMMED | RS1(R1) | S13(IMM) | RD(R3))
320 #define emit_and(R1, R2, R3) \
321 *prog++ = (AND | RS1(R1) | RS2(R2) | RD(R3))
323 #define emit_andi(R1, IMM, R3) \
324 *prog++ = (AND | IMMED | RS1(R1) | S13(IMM) | RD(R3))
326 #define emit_alloc_stack(SZ) \
327 *prog++ = (SUB | IMMED | RS1(SP) | S13(SZ) | RD(SP))
329 #define emit_release_stack(SZ) \
330 *prog++ = (ADD | IMMED | RS1(SP) | S13(SZ) | RD(SP))
332 /* A note about branch offset calculations. The addrs[] array,
333 * indexed by BPF instruction, records the address after all the
334 * sparc instructions emitted for that BPF instruction.
336 * The most common case is to emit a branch at the end of such
337 * a code sequence. So this would be two instructions, the
338 * branch and it's delay slot.
340 * Therefore by default the branch emitters calculate the branch
343 * destination - (addrs[i] - 8)
345 * This "addrs[i] - 8" is the address of the branch itself or
346 * what "." would be in assembler notation. The "8" part is
347 * how we take into consideration the branch and it's delay
348 * slot mentioned above.
350 * Sometimes we need to emit a branch earlier in the code
351 * sequence. And in these situations we adjust "destination"
352 * to accommodate this difference. For example, if we needed
353 * to emit a branch (and it's delay slot) right before the
354 * final instruction emitted for a BPF opcode, we'd use
355 * "destination + 4" instead of just plain "destination" above.
357 * This is why you see all of these funny emit_branch() and
358 * emit_jump() calls with adjusted offsets.
361 void bpf_jit_compile(struct bpf_prog *fp)
363 unsigned int cleanup_addr, proglen, oldproglen = 0;
364 u32 temp[8], *prog, *func, seen = 0, pass;
365 const struct sock_filter *filter = fp->insns;
366 int i, flen = fp->len, pc_ret0 = -1;
373 addrs = kmalloc(flen * sizeof(*addrs), GFP_KERNEL);
377 /* Before first pass, make a rough estimation of addrs[]
378 * each bpf instruction is translated to less than 64 bytes
380 for (proglen = 0, i = 0; i < flen; i++) {
384 cleanup_addr = proglen; /* epilogue address */
386 for (pass = 0; pass < 10; pass++) {
387 u8 seen_or_pass0 = (pass == 0) ? (SEEN_XREG | SEEN_DATAREF | SEEN_MEM) : seen;
389 /* no prologue/epilogue for trivial filters (RET something) */
395 if (seen_or_pass0 & SEEN_MEM) {
396 unsigned int sz = BASE_STACKFRAME;
397 sz += BPF_MEMWORDS * sizeof(u32);
398 emit_alloc_stack(sz);
401 /* Make sure we dont leek kernel memory. */
402 if (seen_or_pass0 & SEEN_XREG)
405 /* If this filter needs to access skb data,
406 * load %o4 and %o5 with:
407 * %o4 = skb->len - skb->data_len
409 * And also back up %o7 into r_saved_O7 so we can
410 * invoke the stubs using 'call'.
412 if (seen_or_pass0 & SEEN_DATAREF) {
413 emit_load32(r_SKB, struct sk_buff, len, r_HEADLEN);
414 emit_load32(r_SKB, struct sk_buff, data_len, r_TMP);
415 emit_sub(r_HEADLEN, r_TMP, r_HEADLEN);
416 emit_loadptr(r_SKB, struct sk_buff, data, r_SKB_DATA);
419 emit_reg_move(O7, r_saved_O7);
421 /* Make sure we dont leak kernel information to the user. */
422 if (bpf_needs_clear_a(&filter[0]))
423 emit_clear(r_A); /* A = 0 */
425 for (i = 0; i < flen; i++) {
426 unsigned int K = filter[i].k;
427 unsigned int t_offset;
428 unsigned int f_offset;
430 u16 code = bpf_anc_helper(&filter[i]);
434 case BPF_ALU | BPF_ADD | BPF_X: /* A += X; */
437 case BPF_ALU | BPF_ADD | BPF_K: /* A += K; */
440 case BPF_ALU | BPF_SUB | BPF_X: /* A -= X; */
443 case BPF_ALU | BPF_SUB | BPF_K: /* A -= K */
446 case BPF_ALU | BPF_AND | BPF_X: /* A &= X */
449 case BPF_ALU | BPF_AND | BPF_K: /* A &= K */
452 case BPF_ALU | BPF_OR | BPF_X: /* A |= X */
455 case BPF_ALU | BPF_OR | BPF_K: /* A |= K */
458 case BPF_ANC | SKF_AD_ALU_XOR_X: /* A ^= X; */
459 case BPF_ALU | BPF_XOR | BPF_X:
462 case BPF_ALU | BPF_XOR | BPF_K: /* A ^= K */
465 case BPF_ALU | BPF_LSH | BPF_X: /* A <<= X */
468 case BPF_ALU | BPF_LSH | BPF_K: /* A <<= K */
471 case BPF_ALU | BPF_RSH | BPF_X: /* A >>= X */
474 case BPF_ALU | BPF_RSH | BPF_K: /* A >>= K */
477 case BPF_ALU | BPF_MUL | BPF_X: /* A *= X; */
480 case BPF_ALU | BPF_MUL | BPF_K: /* A *= K */
483 case BPF_ALU | BPF_DIV | BPF_K: /* A /= K with K != 0*/
487 #ifdef CONFIG_SPARC32
488 /* The Sparc v8 architecture requires
489 * three instructions between a %y
490 * register write and the first use.
498 case BPF_ALU | BPF_DIV | BPF_X: /* A /= X; */
501 t_offset = addrs[pc_ret0 - 1];
502 #ifdef CONFIG_SPARC32
503 emit_branch(BE, t_offset + 20);
505 emit_branch(BE, t_offset + 8);
507 emit_nop(); /* delay slot */
509 emit_branch_off(BNE, 16);
511 #ifdef CONFIG_SPARC32
512 emit_jump(cleanup_addr + 20);
514 emit_jump(cleanup_addr + 8);
519 #ifdef CONFIG_SPARC32
520 /* The Sparc v8 architecture requires
521 * three instructions between a %y
522 * register write and the first use.
530 case BPF_ALU | BPF_NEG:
533 case BPF_RET | BPF_K:
539 emit_loadimm(K, r_A);
542 case BPF_RET | BPF_A:
545 emit_jump(cleanup_addr);
549 if (seen_or_pass0 & SEEN_MEM) {
550 unsigned int sz = BASE_STACKFRAME;
551 sz += BPF_MEMWORDS * sizeof(u32);
552 emit_release_stack(sz);
555 /* jmpl %r_saved_O7 + 8, %g0 */
556 emit_jmpl(r_saved_O7, 8, G0);
557 emit_reg_move(r_A, O0); /* delay slot */
559 case BPF_MISC | BPF_TAX:
561 emit_reg_move(r_A, r_X);
563 case BPF_MISC | BPF_TXA:
565 emit_reg_move(r_X, r_A);
567 case BPF_ANC | SKF_AD_CPU:
570 case BPF_ANC | SKF_AD_PROTOCOL:
571 emit_skb_load16(protocol, r_A);
573 case BPF_ANC | SKF_AD_PKTTYPE:
574 __emit_skb_load8(__pkt_type_offset, r_A);
575 emit_andi(r_A, PKT_TYPE_MAX, r_A);
578 case BPF_ANC | SKF_AD_IFINDEX:
579 emit_skb_loadptr(dev, r_A);
581 emit_branch(BE_PTR, cleanup_addr + 4);
583 emit_load32(r_A, struct net_device, ifindex, r_A);
585 case BPF_ANC | SKF_AD_MARK:
586 emit_skb_load32(mark, r_A);
588 case BPF_ANC | SKF_AD_QUEUE:
589 emit_skb_load16(queue_mapping, r_A);
591 case BPF_ANC | SKF_AD_HATYPE:
592 emit_skb_loadptr(dev, r_A);
594 emit_branch(BE_PTR, cleanup_addr + 4);
596 emit_load16(r_A, struct net_device, type, r_A);
598 case BPF_ANC | SKF_AD_RXHASH:
599 emit_skb_load32(hash, r_A);
601 case BPF_ANC | SKF_AD_VLAN_TAG:
602 case BPF_ANC | SKF_AD_VLAN_TAG_PRESENT:
603 emit_skb_load16(vlan_tci, r_A);
604 if (code != (BPF_ANC | SKF_AD_VLAN_TAG)) {
606 emit_andi(r_A, 1, r_A);
608 emit_loadimm(~VLAN_TAG_PRESENT, r_TMP);
609 emit_and(r_A, r_TMP, r_A);
612 case BPF_LD | BPF_W | BPF_LEN:
613 emit_skb_load32(len, r_A);
615 case BPF_LDX | BPF_W | BPF_LEN:
616 emit_skb_load32(len, r_X);
618 case BPF_LD | BPF_IMM:
619 emit_loadimm(K, r_A);
621 case BPF_LDX | BPF_IMM:
622 emit_loadimm(K, r_X);
624 case BPF_LD | BPF_MEM:
626 emit_ldmem(K * 4, r_A);
628 case BPF_LDX | BPF_MEM:
629 seen |= SEEN_MEM | SEEN_XREG;
630 emit_ldmem(K * 4, r_X);
634 emit_stmem(K * 4, r_A);
637 seen |= SEEN_MEM | SEEN_XREG;
638 emit_stmem(K * 4, r_X);
641 #define CHOOSE_LOAD_FUNC(K, func) \
642 ((int)K < 0 ? ((int)K >= SKF_LL_OFF ? func##_negative_offset : func) : func##_positive_offset)
644 case BPF_LD | BPF_W | BPF_ABS:
645 func = CHOOSE_LOAD_FUNC(K, bpf_jit_load_word);
646 common_load: seen |= SEEN_DATAREF;
647 emit_loadimm(K, r_OFF);
650 case BPF_LD | BPF_H | BPF_ABS:
651 func = CHOOSE_LOAD_FUNC(K, bpf_jit_load_half);
653 case BPF_LD | BPF_B | BPF_ABS:
654 func = CHOOSE_LOAD_FUNC(K, bpf_jit_load_byte);
656 case BPF_LDX | BPF_B | BPF_MSH:
657 func = CHOOSE_LOAD_FUNC(K, bpf_jit_load_byte_msh);
659 case BPF_LD | BPF_W | BPF_IND:
660 func = bpf_jit_load_word;
661 common_load_ind: seen |= SEEN_DATAREF | SEEN_XREG;
664 emit_addi(r_X, K, r_OFF);
666 emit_loadimm(K, r_TMP);
667 emit_add(r_X, r_TMP, r_OFF);
670 emit_reg_move(r_X, r_OFF);
674 case BPF_LD | BPF_H | BPF_IND:
675 func = bpf_jit_load_half;
676 goto common_load_ind;
677 case BPF_LD | BPF_B | BPF_IND:
678 func = bpf_jit_load_byte;
679 goto common_load_ind;
680 case BPF_JMP | BPF_JA:
681 emit_jump(addrs[i + K]);
685 #define COND_SEL(CODE, TOP, FOP) \
691 COND_SEL(BPF_JMP | BPF_JGT | BPF_K, BGU, BLEU);
692 COND_SEL(BPF_JMP | BPF_JGE | BPF_K, BGEU, BLU);
693 COND_SEL(BPF_JMP | BPF_JEQ | BPF_K, BE, BNE);
694 COND_SEL(BPF_JMP | BPF_JSET | BPF_K, BNE, BE);
695 COND_SEL(BPF_JMP | BPF_JGT | BPF_X, BGU, BLEU);
696 COND_SEL(BPF_JMP | BPF_JGE | BPF_X, BGEU, BLU);
697 COND_SEL(BPF_JMP | BPF_JEQ | BPF_X, BE, BNE);
698 COND_SEL(BPF_JMP | BPF_JSET | BPF_X, BNE, BE);
700 cond_branch: f_offset = addrs[i + filter[i].jf];
701 t_offset = addrs[i + filter[i].jt];
703 /* same targets, can avoid doing the test :) */
704 if (filter[i].jt == filter[i].jf) {
711 case BPF_JMP | BPF_JGT | BPF_X:
712 case BPF_JMP | BPF_JGE | BPF_X:
713 case BPF_JMP | BPF_JEQ | BPF_X:
717 case BPF_JMP | BPF_JSET | BPF_X:
721 case BPF_JMP | BPF_JEQ | BPF_K:
722 case BPF_JMP | BPF_JGT | BPF_K:
723 case BPF_JMP | BPF_JGE | BPF_K:
727 emit_loadimm(K, r_TMP);
728 emit_cmp(r_A, r_TMP);
731 case BPF_JMP | BPF_JSET | BPF_K:
735 emit_loadimm(K, r_TMP);
736 emit_btst(r_A, r_TMP);
740 if (filter[i].jt != 0) {
743 emit_branch(t_op, t_offset);
744 emit_nop(); /* delay slot */
751 emit_branch(f_op, f_offset);
752 emit_nop(); /* delay slot */
756 /* hmm, too complex filter, give up with jit compiler */
759 ilen = (void *) prog - (void *) temp;
761 if (unlikely(proglen + ilen > oldproglen)) {
762 pr_err("bpb_jit_compile fatal error\n");
764 module_memfree(image);
767 memcpy(image + proglen, temp, ilen);
773 /* last bpf instruction is always a RET :
774 * use it to give the cleanup instruction(s) addr
776 cleanup_addr = proglen - 8; /* jmpl; mov r_A,%o0; */
777 if (seen_or_pass0 & SEEN_MEM)
778 cleanup_addr -= 4; /* add %sp, X, %sp; */
781 if (proglen != oldproglen)
782 pr_err("bpb_jit_compile proglen=%u != oldproglen=%u\n",
783 proglen, oldproglen);
786 if (proglen == oldproglen) {
787 image = module_alloc(proglen);
791 oldproglen = proglen;
794 if (bpf_jit_enable > 1)
795 bpf_jit_dump(flen, proglen, pass + 1, image);
798 bpf_flush_icache(image, image + proglen);
799 fp->bpf_func = (void *)image;
807 void bpf_jit_free(struct bpf_prog *fp)
810 module_memfree(fp->bpf_func);
812 bpf_prog_unlock_free(fp);