GNU Linux-libre 4.9.296-gnu1
[releases.git] / arch / sparc / mm / srmmu.c
1 /*
2  * srmmu.c:  SRMMU specific routines for memory management.
3  *
4  * Copyright (C) 1995 David S. Miller  (davem@caip.rutgers.edu)
5  * Copyright (C) 1995,2002 Pete Zaitcev (zaitcev@yahoo.com)
6  * Copyright (C) 1996 Eddie C. Dost    (ecd@skynet.be)
7  * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
8  * Copyright (C) 1999,2000 Anton Blanchard (anton@samba.org)
9  */
10
11 #include <linux/seq_file.h>
12 #include <linux/spinlock.h>
13 #include <linux/bootmem.h>
14 #include <linux/pagemap.h>
15 #include <linux/vmalloc.h>
16 #include <linux/kdebug.h>
17 #include <linux/export.h>
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/log2.h>
21 #include <linux/gfp.h>
22 #include <linux/fs.h>
23 #include <linux/mm.h>
24
25 #include <asm/mmu_context.h>
26 #include <asm/cacheflush.h>
27 #include <asm/tlbflush.h>
28 #include <asm/io-unit.h>
29 #include <asm/pgalloc.h>
30 #include <asm/pgtable.h>
31 #include <asm/bitext.h>
32 #include <asm/vaddrs.h>
33 #include <asm/cache.h>
34 #include <asm/traps.h>
35 #include <asm/oplib.h>
36 #include <asm/mbus.h>
37 #include <asm/page.h>
38 #include <asm/asi.h>
39 #include <asm/msi.h>
40 #include <asm/smp.h>
41 #include <asm/io.h>
42
43 /* Now the cpu specific definitions. */
44 #include <asm/turbosparc.h>
45 #include <asm/tsunami.h>
46 #include <asm/viking.h>
47 #include <asm/swift.h>
48 #include <asm/leon.h>
49 #include <asm/mxcc.h>
50 #include <asm/ross.h>
51
52 #include "mm_32.h"
53
54 enum mbus_module srmmu_modtype;
55 static unsigned int hwbug_bitmask;
56 int vac_cache_size;
57 EXPORT_SYMBOL(vac_cache_size);
58 int vac_line_size;
59
60 extern struct resource sparc_iomap;
61
62 extern unsigned long last_valid_pfn;
63
64 static pgd_t *srmmu_swapper_pg_dir;
65
66 const struct sparc32_cachetlb_ops *sparc32_cachetlb_ops;
67 EXPORT_SYMBOL(sparc32_cachetlb_ops);
68
69 #ifdef CONFIG_SMP
70 const struct sparc32_cachetlb_ops *local_ops;
71
72 #define FLUSH_BEGIN(mm)
73 #define FLUSH_END
74 #else
75 #define FLUSH_BEGIN(mm) if ((mm)->context != NO_CONTEXT) {
76 #define FLUSH_END       }
77 #endif
78
79 int flush_page_for_dma_global = 1;
80
81 char *srmmu_name;
82
83 ctxd_t *srmmu_ctx_table_phys;
84 static ctxd_t *srmmu_context_table;
85
86 int viking_mxcc_present;
87 static DEFINE_SPINLOCK(srmmu_context_spinlock);
88
89 static int is_hypersparc;
90
91 static int srmmu_cache_pagetables;
92
93 /* these will be initialized in srmmu_nocache_calcsize() */
94 static unsigned long srmmu_nocache_size;
95 static unsigned long srmmu_nocache_end;
96
97 /* 1 bit <=> 256 bytes of nocache <=> 64 PTEs */
98 #define SRMMU_NOCACHE_BITMAP_SHIFT (PAGE_SHIFT - 4)
99
100 /* The context table is a nocache user with the biggest alignment needs. */
101 #define SRMMU_NOCACHE_ALIGN_MAX (sizeof(ctxd_t)*SRMMU_MAX_CONTEXTS)
102
103 void *srmmu_nocache_pool;
104 static struct bit_map srmmu_nocache_map;
105
106 static inline int srmmu_pmd_none(pmd_t pmd)
107 { return !(pmd_val(pmd) & 0xFFFFFFF); }
108
109 /* XXX should we hyper_flush_whole_icache here - Anton */
110 static inline void srmmu_ctxd_set(ctxd_t *ctxp, pgd_t *pgdp)
111 {
112         pte_t pte;
113
114         pte = __pte((SRMMU_ET_PTD | (__nocache_pa(pgdp) >> 4)));
115         set_pte((pte_t *)ctxp, pte);
116 }
117
118 void pmd_set(pmd_t *pmdp, pte_t *ptep)
119 {
120         unsigned long ptp;      /* Physical address, shifted right by 4 */
121         int i;
122
123         ptp = __nocache_pa(ptep) >> 4;
124         for (i = 0; i < PTRS_PER_PTE/SRMMU_REAL_PTRS_PER_PTE; i++) {
125                 set_pte((pte_t *)&pmdp->pmdv[i], __pte(SRMMU_ET_PTD | ptp));
126                 ptp += (SRMMU_REAL_PTRS_PER_PTE * sizeof(pte_t) >> 4);
127         }
128 }
129
130 void pmd_populate(struct mm_struct *mm, pmd_t *pmdp, struct page *ptep)
131 {
132         unsigned long ptp;      /* Physical address, shifted right by 4 */
133         int i;
134
135         ptp = page_to_pfn(ptep) << (PAGE_SHIFT-4);      /* watch for overflow */
136         for (i = 0; i < PTRS_PER_PTE/SRMMU_REAL_PTRS_PER_PTE; i++) {
137                 set_pte((pte_t *)&pmdp->pmdv[i], __pte(SRMMU_ET_PTD | ptp));
138                 ptp += (SRMMU_REAL_PTRS_PER_PTE * sizeof(pte_t) >> 4);
139         }
140 }
141
142 /* Find an entry in the third-level page table.. */
143 pte_t *pte_offset_kernel(pmd_t *dir, unsigned long address)
144 {
145         void *pte;
146
147         pte = __nocache_va((dir->pmdv[0] & SRMMU_PTD_PMASK) << 4);
148         return (pte_t *) pte +
149             ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1));
150 }
151
152 /*
153  * size: bytes to allocate in the nocache area.
154  * align: bytes, number to align at.
155  * Returns the virtual address of the allocated area.
156  */
157 static void *__srmmu_get_nocache(int size, int align)
158 {
159         int offset;
160         unsigned long addr;
161
162         if (size < SRMMU_NOCACHE_BITMAP_SHIFT) {
163                 printk(KERN_ERR "Size 0x%x too small for nocache request\n",
164                        size);
165                 size = SRMMU_NOCACHE_BITMAP_SHIFT;
166         }
167         if (size & (SRMMU_NOCACHE_BITMAP_SHIFT - 1)) {
168                 printk(KERN_ERR "Size 0x%x unaligned int nocache request\n",
169                        size);
170                 size += SRMMU_NOCACHE_BITMAP_SHIFT - 1;
171         }
172         BUG_ON(align > SRMMU_NOCACHE_ALIGN_MAX);
173
174         offset = bit_map_string_get(&srmmu_nocache_map,
175                                     size >> SRMMU_NOCACHE_BITMAP_SHIFT,
176                                     align >> SRMMU_NOCACHE_BITMAP_SHIFT);
177         if (offset == -1) {
178                 printk(KERN_ERR "srmmu: out of nocache %d: %d/%d\n",
179                        size, (int) srmmu_nocache_size,
180                        srmmu_nocache_map.used << SRMMU_NOCACHE_BITMAP_SHIFT);
181                 return NULL;
182         }
183
184         addr = SRMMU_NOCACHE_VADDR + (offset << SRMMU_NOCACHE_BITMAP_SHIFT);
185         return (void *)addr;
186 }
187
188 void *srmmu_get_nocache(int size, int align)
189 {
190         void *tmp;
191
192         tmp = __srmmu_get_nocache(size, align);
193
194         if (tmp)
195                 memset(tmp, 0, size);
196
197         return tmp;
198 }
199
200 void srmmu_free_nocache(void *addr, int size)
201 {
202         unsigned long vaddr;
203         int offset;
204
205         vaddr = (unsigned long)addr;
206         if (vaddr < SRMMU_NOCACHE_VADDR) {
207                 printk("Vaddr %lx is smaller than nocache base 0x%lx\n",
208                     vaddr, (unsigned long)SRMMU_NOCACHE_VADDR);
209                 BUG();
210         }
211         if (vaddr + size > srmmu_nocache_end) {
212                 printk("Vaddr %lx is bigger than nocache end 0x%lx\n",
213                     vaddr, srmmu_nocache_end);
214                 BUG();
215         }
216         if (!is_power_of_2(size)) {
217                 printk("Size 0x%x is not a power of 2\n", size);
218                 BUG();
219         }
220         if (size < SRMMU_NOCACHE_BITMAP_SHIFT) {
221                 printk("Size 0x%x is too small\n", size);
222                 BUG();
223         }
224         if (vaddr & (size - 1)) {
225                 printk("Vaddr %lx is not aligned to size 0x%x\n", vaddr, size);
226                 BUG();
227         }
228
229         offset = (vaddr - SRMMU_NOCACHE_VADDR) >> SRMMU_NOCACHE_BITMAP_SHIFT;
230         size = size >> SRMMU_NOCACHE_BITMAP_SHIFT;
231
232         bit_map_clear(&srmmu_nocache_map, offset, size);
233 }
234
235 static void srmmu_early_allocate_ptable_skeleton(unsigned long start,
236                                                  unsigned long end);
237
238 /* Return how much physical memory we have.  */
239 static unsigned long __init probe_memory(void)
240 {
241         unsigned long total = 0;
242         int i;
243
244         for (i = 0; sp_banks[i].num_bytes; i++)
245                 total += sp_banks[i].num_bytes;
246
247         return total;
248 }
249
250 /*
251  * Reserve nocache dynamically proportionally to the amount of
252  * system RAM. -- Tomas Szepe <szepe@pinerecords.com>, June 2002
253  */
254 static void __init srmmu_nocache_calcsize(void)
255 {
256         unsigned long sysmemavail = probe_memory() / 1024;
257         int srmmu_nocache_npages;
258
259         srmmu_nocache_npages =
260                 sysmemavail / SRMMU_NOCACHE_ALCRATIO / 1024 * 256;
261
262  /* P3 XXX The 4x overuse: corroborated by /proc/meminfo. */
263         // if (srmmu_nocache_npages < 256) srmmu_nocache_npages = 256;
264         if (srmmu_nocache_npages < SRMMU_MIN_NOCACHE_PAGES)
265                 srmmu_nocache_npages = SRMMU_MIN_NOCACHE_PAGES;
266
267         /* anything above 1280 blows up */
268         if (srmmu_nocache_npages > SRMMU_MAX_NOCACHE_PAGES)
269                 srmmu_nocache_npages = SRMMU_MAX_NOCACHE_PAGES;
270
271         srmmu_nocache_size = srmmu_nocache_npages * PAGE_SIZE;
272         srmmu_nocache_end = SRMMU_NOCACHE_VADDR + srmmu_nocache_size;
273 }
274
275 static void __init srmmu_nocache_init(void)
276 {
277         void *srmmu_nocache_bitmap;
278         unsigned int bitmap_bits;
279         pgd_t *pgd;
280         pmd_t *pmd;
281         pte_t *pte;
282         unsigned long paddr, vaddr;
283         unsigned long pteval;
284
285         bitmap_bits = srmmu_nocache_size >> SRMMU_NOCACHE_BITMAP_SHIFT;
286
287         srmmu_nocache_pool = __alloc_bootmem(srmmu_nocache_size,
288                 SRMMU_NOCACHE_ALIGN_MAX, 0UL);
289         memset(srmmu_nocache_pool, 0, srmmu_nocache_size);
290
291         srmmu_nocache_bitmap =
292                 __alloc_bootmem(BITS_TO_LONGS(bitmap_bits) * sizeof(long),
293                                 SMP_CACHE_BYTES, 0UL);
294         bit_map_init(&srmmu_nocache_map, srmmu_nocache_bitmap, bitmap_bits);
295
296         srmmu_swapper_pg_dir = __srmmu_get_nocache(SRMMU_PGD_TABLE_SIZE, SRMMU_PGD_TABLE_SIZE);
297         memset(__nocache_fix(srmmu_swapper_pg_dir), 0, SRMMU_PGD_TABLE_SIZE);
298         init_mm.pgd = srmmu_swapper_pg_dir;
299
300         srmmu_early_allocate_ptable_skeleton(SRMMU_NOCACHE_VADDR, srmmu_nocache_end);
301
302         paddr = __pa((unsigned long)srmmu_nocache_pool);
303         vaddr = SRMMU_NOCACHE_VADDR;
304
305         while (vaddr < srmmu_nocache_end) {
306                 pgd = pgd_offset_k(vaddr);
307                 pmd = pmd_offset(__nocache_fix(pgd), vaddr);
308                 pte = pte_offset_kernel(__nocache_fix(pmd), vaddr);
309
310                 pteval = ((paddr >> 4) | SRMMU_ET_PTE | SRMMU_PRIV);
311
312                 if (srmmu_cache_pagetables)
313                         pteval |= SRMMU_CACHE;
314
315                 set_pte(__nocache_fix(pte), __pte(pteval));
316
317                 vaddr += PAGE_SIZE;
318                 paddr += PAGE_SIZE;
319         }
320
321         flush_cache_all();
322         flush_tlb_all();
323 }
324
325 pgd_t *get_pgd_fast(void)
326 {
327         pgd_t *pgd = NULL;
328
329         pgd = __srmmu_get_nocache(SRMMU_PGD_TABLE_SIZE, SRMMU_PGD_TABLE_SIZE);
330         if (pgd) {
331                 pgd_t *init = pgd_offset_k(0);
332                 memset(pgd, 0, USER_PTRS_PER_PGD * sizeof(pgd_t));
333                 memcpy(pgd + USER_PTRS_PER_PGD, init + USER_PTRS_PER_PGD,
334                                                 (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t));
335         }
336
337         return pgd;
338 }
339
340 /*
341  * Hardware needs alignment to 256 only, but we align to whole page size
342  * to reduce fragmentation problems due to the buddy principle.
343  * XXX Provide actual fragmentation statistics in /proc.
344  *
345  * Alignments up to the page size are the same for physical and virtual
346  * addresses of the nocache area.
347  */
348 pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long address)
349 {
350         unsigned long pte;
351         struct page *page;
352
353         if ((pte = (unsigned long)pte_alloc_one_kernel(mm, address)) == 0)
354                 return NULL;
355         page = pfn_to_page(__nocache_pa(pte) >> PAGE_SHIFT);
356         if (!pgtable_page_ctor(page)) {
357                 __free_page(page);
358                 return NULL;
359         }
360         return page;
361 }
362
363 void pte_free(struct mm_struct *mm, pgtable_t pte)
364 {
365         unsigned long p;
366
367         pgtable_page_dtor(pte);
368         p = (unsigned long)page_address(pte);   /* Cached address (for test) */
369         if (p == 0)
370                 BUG();
371         p = page_to_pfn(pte) << PAGE_SHIFT;     /* Physical address */
372
373         /* free non cached virtual address*/
374         srmmu_free_nocache(__nocache_va(p), PTE_SIZE);
375 }
376
377 /* context handling - a dynamically sized pool is used */
378 #define NO_CONTEXT      -1
379
380 struct ctx_list {
381         struct ctx_list *next;
382         struct ctx_list *prev;
383         unsigned int ctx_number;
384         struct mm_struct *ctx_mm;
385 };
386
387 static struct ctx_list *ctx_list_pool;
388 static struct ctx_list ctx_free;
389 static struct ctx_list ctx_used;
390
391 /* At boot time we determine the number of contexts */
392 static int num_contexts;
393
394 static inline void remove_from_ctx_list(struct ctx_list *entry)
395 {
396         entry->next->prev = entry->prev;
397         entry->prev->next = entry->next;
398 }
399
400 static inline void add_to_ctx_list(struct ctx_list *head, struct ctx_list *entry)
401 {
402         entry->next = head;
403         (entry->prev = head->prev)->next = entry;
404         head->prev = entry;
405 }
406 #define add_to_free_ctxlist(entry) add_to_ctx_list(&ctx_free, entry)
407 #define add_to_used_ctxlist(entry) add_to_ctx_list(&ctx_used, entry)
408
409
410 static inline void alloc_context(struct mm_struct *old_mm, struct mm_struct *mm)
411 {
412         struct ctx_list *ctxp;
413
414         ctxp = ctx_free.next;
415         if (ctxp != &ctx_free) {
416                 remove_from_ctx_list(ctxp);
417                 add_to_used_ctxlist(ctxp);
418                 mm->context = ctxp->ctx_number;
419                 ctxp->ctx_mm = mm;
420                 return;
421         }
422         ctxp = ctx_used.next;
423         if (ctxp->ctx_mm == old_mm)
424                 ctxp = ctxp->next;
425         if (ctxp == &ctx_used)
426                 panic("out of mmu contexts");
427         flush_cache_mm(ctxp->ctx_mm);
428         flush_tlb_mm(ctxp->ctx_mm);
429         remove_from_ctx_list(ctxp);
430         add_to_used_ctxlist(ctxp);
431         ctxp->ctx_mm->context = NO_CONTEXT;
432         ctxp->ctx_mm = mm;
433         mm->context = ctxp->ctx_number;
434 }
435
436 static inline void free_context(int context)
437 {
438         struct ctx_list *ctx_old;
439
440         ctx_old = ctx_list_pool + context;
441         remove_from_ctx_list(ctx_old);
442         add_to_free_ctxlist(ctx_old);
443 }
444
445 static void __init sparc_context_init(int numctx)
446 {
447         int ctx;
448         unsigned long size;
449
450         size = numctx * sizeof(struct ctx_list);
451         ctx_list_pool = __alloc_bootmem(size, SMP_CACHE_BYTES, 0UL);
452
453         for (ctx = 0; ctx < numctx; ctx++) {
454                 struct ctx_list *clist;
455
456                 clist = (ctx_list_pool + ctx);
457                 clist->ctx_number = ctx;
458                 clist->ctx_mm = NULL;
459         }
460         ctx_free.next = ctx_free.prev = &ctx_free;
461         ctx_used.next = ctx_used.prev = &ctx_used;
462         for (ctx = 0; ctx < numctx; ctx++)
463                 add_to_free_ctxlist(ctx_list_pool + ctx);
464 }
465
466 void switch_mm(struct mm_struct *old_mm, struct mm_struct *mm,
467                struct task_struct *tsk)
468 {
469         unsigned long flags;
470
471         if (mm->context == NO_CONTEXT) {
472                 spin_lock_irqsave(&srmmu_context_spinlock, flags);
473                 alloc_context(old_mm, mm);
474                 spin_unlock_irqrestore(&srmmu_context_spinlock, flags);
475                 srmmu_ctxd_set(&srmmu_context_table[mm->context], mm->pgd);
476         }
477
478         if (sparc_cpu_model == sparc_leon)
479                 leon_switch_mm();
480
481         if (is_hypersparc)
482                 hyper_flush_whole_icache();
483
484         srmmu_set_context(mm->context);
485 }
486
487 /* Low level IO area allocation on the SRMMU. */
488 static inline void srmmu_mapioaddr(unsigned long physaddr,
489                                    unsigned long virt_addr, int bus_type)
490 {
491         pgd_t *pgdp;
492         pmd_t *pmdp;
493         pte_t *ptep;
494         unsigned long tmp;
495
496         physaddr &= PAGE_MASK;
497         pgdp = pgd_offset_k(virt_addr);
498         pmdp = pmd_offset(pgdp, virt_addr);
499         ptep = pte_offset_kernel(pmdp, virt_addr);
500         tmp = (physaddr >> 4) | SRMMU_ET_PTE;
501
502         /* I need to test whether this is consistent over all
503          * sun4m's.  The bus_type represents the upper 4 bits of
504          * 36-bit physical address on the I/O space lines...
505          */
506         tmp |= (bus_type << 28);
507         tmp |= SRMMU_PRIV;
508         __flush_page_to_ram(virt_addr);
509         set_pte(ptep, __pte(tmp));
510 }
511
512 void srmmu_mapiorange(unsigned int bus, unsigned long xpa,
513                       unsigned long xva, unsigned int len)
514 {
515         while (len != 0) {
516                 len -= PAGE_SIZE;
517                 srmmu_mapioaddr(xpa, xva, bus);
518                 xva += PAGE_SIZE;
519                 xpa += PAGE_SIZE;
520         }
521         flush_tlb_all();
522 }
523
524 static inline void srmmu_unmapioaddr(unsigned long virt_addr)
525 {
526         pgd_t *pgdp;
527         pmd_t *pmdp;
528         pte_t *ptep;
529
530         pgdp = pgd_offset_k(virt_addr);
531         pmdp = pmd_offset(pgdp, virt_addr);
532         ptep = pte_offset_kernel(pmdp, virt_addr);
533
534         /* No need to flush uncacheable page. */
535         __pte_clear(ptep);
536 }
537
538 void srmmu_unmapiorange(unsigned long virt_addr, unsigned int len)
539 {
540         while (len != 0) {
541                 len -= PAGE_SIZE;
542                 srmmu_unmapioaddr(virt_addr);
543                 virt_addr += PAGE_SIZE;
544         }
545         flush_tlb_all();
546 }
547
548 /* tsunami.S */
549 extern void tsunami_flush_cache_all(void);
550 extern void tsunami_flush_cache_mm(struct mm_struct *mm);
551 extern void tsunami_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
552 extern void tsunami_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
553 extern void tsunami_flush_page_to_ram(unsigned long page);
554 extern void tsunami_flush_page_for_dma(unsigned long page);
555 extern void tsunami_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
556 extern void tsunami_flush_tlb_all(void);
557 extern void tsunami_flush_tlb_mm(struct mm_struct *mm);
558 extern void tsunami_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
559 extern void tsunami_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
560 extern void tsunami_setup_blockops(void);
561
562 /* swift.S */
563 extern void swift_flush_cache_all(void);
564 extern void swift_flush_cache_mm(struct mm_struct *mm);
565 extern void swift_flush_cache_range(struct vm_area_struct *vma,
566                                     unsigned long start, unsigned long end);
567 extern void swift_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
568 extern void swift_flush_page_to_ram(unsigned long page);
569 extern void swift_flush_page_for_dma(unsigned long page);
570 extern void swift_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
571 extern void swift_flush_tlb_all(void);
572 extern void swift_flush_tlb_mm(struct mm_struct *mm);
573 extern void swift_flush_tlb_range(struct vm_area_struct *vma,
574                                   unsigned long start, unsigned long end);
575 extern void swift_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
576
577 #if 0  /* P3: deadwood to debug precise flushes on Swift. */
578 void swift_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
579 {
580         int cctx, ctx1;
581
582         page &= PAGE_MASK;
583         if ((ctx1 = vma->vm_mm->context) != -1) {
584                 cctx = srmmu_get_context();
585 /* Is context # ever different from current context? P3 */
586                 if (cctx != ctx1) {
587                         printk("flush ctx %02x curr %02x\n", ctx1, cctx);
588                         srmmu_set_context(ctx1);
589                         swift_flush_page(page);
590                         __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
591                                         "r" (page), "i" (ASI_M_FLUSH_PROBE));
592                         srmmu_set_context(cctx);
593                 } else {
594                          /* Rm. prot. bits from virt. c. */
595                         /* swift_flush_cache_all(); */
596                         /* swift_flush_cache_page(vma, page); */
597                         swift_flush_page(page);
598
599                         __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
600                                 "r" (page), "i" (ASI_M_FLUSH_PROBE));
601                         /* same as above: srmmu_flush_tlb_page() */
602                 }
603         }
604 }
605 #endif
606
607 /*
608  * The following are all MBUS based SRMMU modules, and therefore could
609  * be found in a multiprocessor configuration.  On the whole, these
610  * chips seems to be much more touchy about DVMA and page tables
611  * with respect to cache coherency.
612  */
613
614 /* viking.S */
615 extern void viking_flush_cache_all(void);
616 extern void viking_flush_cache_mm(struct mm_struct *mm);
617 extern void viking_flush_cache_range(struct vm_area_struct *vma, unsigned long start,
618                                      unsigned long end);
619 extern void viking_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
620 extern void viking_flush_page_to_ram(unsigned long page);
621 extern void viking_flush_page_for_dma(unsigned long page);
622 extern void viking_flush_sig_insns(struct mm_struct *mm, unsigned long addr);
623 extern void viking_flush_page(unsigned long page);
624 extern void viking_mxcc_flush_page(unsigned long page);
625 extern void viking_flush_tlb_all(void);
626 extern void viking_flush_tlb_mm(struct mm_struct *mm);
627 extern void viking_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
628                                    unsigned long end);
629 extern void viking_flush_tlb_page(struct vm_area_struct *vma,
630                                   unsigned long page);
631 extern void sun4dsmp_flush_tlb_all(void);
632 extern void sun4dsmp_flush_tlb_mm(struct mm_struct *mm);
633 extern void sun4dsmp_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
634                                    unsigned long end);
635 extern void sun4dsmp_flush_tlb_page(struct vm_area_struct *vma,
636                                   unsigned long page);
637
638 /* hypersparc.S */
639 extern void hypersparc_flush_cache_all(void);
640 extern void hypersparc_flush_cache_mm(struct mm_struct *mm);
641 extern void hypersparc_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
642 extern void hypersparc_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
643 extern void hypersparc_flush_page_to_ram(unsigned long page);
644 extern void hypersparc_flush_page_for_dma(unsigned long page);
645 extern void hypersparc_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
646 extern void hypersparc_flush_tlb_all(void);
647 extern void hypersparc_flush_tlb_mm(struct mm_struct *mm);
648 extern void hypersparc_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
649 extern void hypersparc_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
650 extern void hypersparc_setup_blockops(void);
651
652 /*
653  * NOTE: All of this startup code assumes the low 16mb (approx.) of
654  *       kernel mappings are done with one single contiguous chunk of
655  *       ram.  On small ram machines (classics mainly) we only get
656  *       around 8mb mapped for us.
657  */
658
659 static void __init early_pgtable_allocfail(char *type)
660 {
661         prom_printf("inherit_prom_mappings: Cannot alloc kernel %s.\n", type);
662         prom_halt();
663 }
664
665 static void __init srmmu_early_allocate_ptable_skeleton(unsigned long start,
666                                                         unsigned long end)
667 {
668         pgd_t *pgdp;
669         pmd_t *pmdp;
670         pte_t *ptep;
671
672         while (start < end) {
673                 pgdp = pgd_offset_k(start);
674                 if (pgd_none(*(pgd_t *)__nocache_fix(pgdp))) {
675                         pmdp = __srmmu_get_nocache(
676                             SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
677                         if (pmdp == NULL)
678                                 early_pgtable_allocfail("pmd");
679                         memset(__nocache_fix(pmdp), 0, SRMMU_PMD_TABLE_SIZE);
680                         pgd_set(__nocache_fix(pgdp), pmdp);
681                 }
682                 pmdp = pmd_offset(__nocache_fix(pgdp), start);
683                 if (srmmu_pmd_none(*(pmd_t *)__nocache_fix(pmdp))) {
684                         ptep = __srmmu_get_nocache(PTE_SIZE, PTE_SIZE);
685                         if (ptep == NULL)
686                                 early_pgtable_allocfail("pte");
687                         memset(__nocache_fix(ptep), 0, PTE_SIZE);
688                         pmd_set(__nocache_fix(pmdp), ptep);
689                 }
690                 if (start > (0xffffffffUL - PMD_SIZE))
691                         break;
692                 start = (start + PMD_SIZE) & PMD_MASK;
693         }
694 }
695
696 static void __init srmmu_allocate_ptable_skeleton(unsigned long start,
697                                                   unsigned long end)
698 {
699         pgd_t *pgdp;
700         pmd_t *pmdp;
701         pte_t *ptep;
702
703         while (start < end) {
704                 pgdp = pgd_offset_k(start);
705                 if (pgd_none(*pgdp)) {
706                         pmdp = __srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
707                         if (pmdp == NULL)
708                                 early_pgtable_allocfail("pmd");
709                         memset(pmdp, 0, SRMMU_PMD_TABLE_SIZE);
710                         pgd_set(pgdp, pmdp);
711                 }
712                 pmdp = pmd_offset(pgdp, start);
713                 if (srmmu_pmd_none(*pmdp)) {
714                         ptep = __srmmu_get_nocache(PTE_SIZE,
715                                                              PTE_SIZE);
716                         if (ptep == NULL)
717                                 early_pgtable_allocfail("pte");
718                         memset(ptep, 0, PTE_SIZE);
719                         pmd_set(pmdp, ptep);
720                 }
721                 if (start > (0xffffffffUL - PMD_SIZE))
722                         break;
723                 start = (start + PMD_SIZE) & PMD_MASK;
724         }
725 }
726
727 /* These flush types are not available on all chips... */
728 static inline unsigned long srmmu_probe(unsigned long vaddr)
729 {
730         unsigned long retval;
731
732         if (sparc_cpu_model != sparc_leon) {
733
734                 vaddr &= PAGE_MASK;
735                 __asm__ __volatile__("lda [%1] %2, %0\n\t" :
736                                      "=r" (retval) :
737                                      "r" (vaddr | 0x400), "i" (ASI_M_FLUSH_PROBE));
738         } else {
739                 retval = leon_swprobe(vaddr, NULL);
740         }
741         return retval;
742 }
743
744 /*
745  * This is much cleaner than poking around physical address space
746  * looking at the prom's page table directly which is what most
747  * other OS's do.  Yuck... this is much better.
748  */
749 static void __init srmmu_inherit_prom_mappings(unsigned long start,
750                                                unsigned long end)
751 {
752         unsigned long probed;
753         unsigned long addr;
754         pgd_t *pgdp;
755         pmd_t *pmdp;
756         pte_t *ptep;
757         int what; /* 0 = normal-pte, 1 = pmd-level pte, 2 = pgd-level pte */
758
759         while (start <= end) {
760                 if (start == 0)
761                         break; /* probably wrap around */
762                 if (start == 0xfef00000)
763                         start = KADB_DEBUGGER_BEGVM;
764                 probed = srmmu_probe(start);
765                 if (!probed) {
766                         /* continue probing until we find an entry */
767                         start += PAGE_SIZE;
768                         continue;
769                 }
770
771                 /* A red snapper, see what it really is. */
772                 what = 0;
773                 addr = start - PAGE_SIZE;
774
775                 if (!(start & ~(SRMMU_REAL_PMD_MASK))) {
776                         if (srmmu_probe(addr + SRMMU_REAL_PMD_SIZE) == probed)
777                                 what = 1;
778                 }
779
780                 if (!(start & ~(SRMMU_PGDIR_MASK))) {
781                         if (srmmu_probe(addr + SRMMU_PGDIR_SIZE) == probed)
782                                 what = 2;
783                 }
784
785                 pgdp = pgd_offset_k(start);
786                 if (what == 2) {
787                         *(pgd_t *)__nocache_fix(pgdp) = __pgd(probed);
788                         start += SRMMU_PGDIR_SIZE;
789                         continue;
790                 }
791                 if (pgd_none(*(pgd_t *)__nocache_fix(pgdp))) {
792                         pmdp = __srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE,
793                                                    SRMMU_PMD_TABLE_SIZE);
794                         if (pmdp == NULL)
795                                 early_pgtable_allocfail("pmd");
796                         memset(__nocache_fix(pmdp), 0, SRMMU_PMD_TABLE_SIZE);
797                         pgd_set(__nocache_fix(pgdp), pmdp);
798                 }
799                 pmdp = pmd_offset(__nocache_fix(pgdp), start);
800                 if (srmmu_pmd_none(*(pmd_t *)__nocache_fix(pmdp))) {
801                         ptep = __srmmu_get_nocache(PTE_SIZE, PTE_SIZE);
802                         if (ptep == NULL)
803                                 early_pgtable_allocfail("pte");
804                         memset(__nocache_fix(ptep), 0, PTE_SIZE);
805                         pmd_set(__nocache_fix(pmdp), ptep);
806                 }
807                 if (what == 1) {
808                         /* We bend the rule where all 16 PTPs in a pmd_t point
809                          * inside the same PTE page, and we leak a perfectly
810                          * good hardware PTE piece. Alternatives seem worse.
811                          */
812                         unsigned int x; /* Index of HW PMD in soft cluster */
813                         unsigned long *val;
814                         x = (start >> PMD_SHIFT) & 15;
815                         val = &pmdp->pmdv[x];
816                         *(unsigned long *)__nocache_fix(val) = probed;
817                         start += SRMMU_REAL_PMD_SIZE;
818                         continue;
819                 }
820                 ptep = pte_offset_kernel(__nocache_fix(pmdp), start);
821                 *(pte_t *)__nocache_fix(ptep) = __pte(probed);
822                 start += PAGE_SIZE;
823         }
824 }
825
826 #define KERNEL_PTE(page_shifted) ((page_shifted)|SRMMU_CACHE|SRMMU_PRIV|SRMMU_VALID)
827
828 /* Create a third-level SRMMU 16MB page mapping. */
829 static void __init do_large_mapping(unsigned long vaddr, unsigned long phys_base)
830 {
831         pgd_t *pgdp = pgd_offset_k(vaddr);
832         unsigned long big_pte;
833
834         big_pte = KERNEL_PTE(phys_base >> 4);
835         *(pgd_t *)__nocache_fix(pgdp) = __pgd(big_pte);
836 }
837
838 /* Map sp_bank entry SP_ENTRY, starting at virtual address VBASE. */
839 static unsigned long __init map_spbank(unsigned long vbase, int sp_entry)
840 {
841         unsigned long pstart = (sp_banks[sp_entry].base_addr & SRMMU_PGDIR_MASK);
842         unsigned long vstart = (vbase & SRMMU_PGDIR_MASK);
843         unsigned long vend = SRMMU_PGDIR_ALIGN(vbase + sp_banks[sp_entry].num_bytes);
844         /* Map "low" memory only */
845         const unsigned long min_vaddr = PAGE_OFFSET;
846         const unsigned long max_vaddr = PAGE_OFFSET + SRMMU_MAXMEM;
847
848         if (vstart < min_vaddr || vstart >= max_vaddr)
849                 return vstart;
850
851         if (vend > max_vaddr || vend < min_vaddr)
852                 vend = max_vaddr;
853
854         while (vstart < vend) {
855                 do_large_mapping(vstart, pstart);
856                 vstart += SRMMU_PGDIR_SIZE; pstart += SRMMU_PGDIR_SIZE;
857         }
858         return vstart;
859 }
860
861 static void __init map_kernel(void)
862 {
863         int i;
864
865         if (phys_base > 0) {
866                 do_large_mapping(PAGE_OFFSET, phys_base);
867         }
868
869         for (i = 0; sp_banks[i].num_bytes != 0; i++) {
870                 map_spbank((unsigned long)__va(sp_banks[i].base_addr), i);
871         }
872 }
873
874 void (*poke_srmmu)(void) = NULL;
875
876 void __init srmmu_paging_init(void)
877 {
878         int i;
879         phandle cpunode;
880         char node_str[128];
881         pgd_t *pgd;
882         pmd_t *pmd;
883         pte_t *pte;
884         unsigned long pages_avail;
885
886         init_mm.context = (unsigned long) NO_CONTEXT;
887         sparc_iomap.start = SUN4M_IOBASE_VADDR; /* 16MB of IOSPACE on all sun4m's. */
888
889         if (sparc_cpu_model == sun4d)
890                 num_contexts = 65536; /* We know it is Viking */
891         else {
892                 /* Find the number of contexts on the srmmu. */
893                 cpunode = prom_getchild(prom_root_node);
894                 num_contexts = 0;
895                 while (cpunode != 0) {
896                         prom_getstring(cpunode, "device_type", node_str, sizeof(node_str));
897                         if (!strcmp(node_str, "cpu")) {
898                                 num_contexts = prom_getintdefault(cpunode, "mmu-nctx", 0x8);
899                                 break;
900                         }
901                         cpunode = prom_getsibling(cpunode);
902                 }
903         }
904
905         if (!num_contexts) {
906                 prom_printf("Something wrong, can't find cpu node in paging_init.\n");
907                 prom_halt();
908         }
909
910         pages_avail = 0;
911         last_valid_pfn = bootmem_init(&pages_avail);
912
913         srmmu_nocache_calcsize();
914         srmmu_nocache_init();
915         srmmu_inherit_prom_mappings(0xfe400000, (LINUX_OPPROM_ENDVM - PAGE_SIZE));
916         map_kernel();
917
918         /* ctx table has to be physically aligned to its size */
919         srmmu_context_table = __srmmu_get_nocache(num_contexts * sizeof(ctxd_t), num_contexts * sizeof(ctxd_t));
920         srmmu_ctx_table_phys = (ctxd_t *)__nocache_pa(srmmu_context_table);
921
922         for (i = 0; i < num_contexts; i++)
923                 srmmu_ctxd_set((ctxd_t *)__nocache_fix(&srmmu_context_table[i]), srmmu_swapper_pg_dir);
924
925         flush_cache_all();
926         srmmu_set_ctable_ptr((unsigned long)srmmu_ctx_table_phys);
927 #ifdef CONFIG_SMP
928         /* Stop from hanging here... */
929         local_ops->tlb_all();
930 #else
931         flush_tlb_all();
932 #endif
933         poke_srmmu();
934
935         srmmu_allocate_ptable_skeleton(sparc_iomap.start, IOBASE_END);
936         srmmu_allocate_ptable_skeleton(DVMA_VADDR, DVMA_END);
937
938         srmmu_allocate_ptable_skeleton(
939                 __fix_to_virt(__end_of_fixed_addresses - 1), FIXADDR_TOP);
940         srmmu_allocate_ptable_skeleton(PKMAP_BASE, PKMAP_END);
941
942         pgd = pgd_offset_k(PKMAP_BASE);
943         pmd = pmd_offset(pgd, PKMAP_BASE);
944         pte = pte_offset_kernel(pmd, PKMAP_BASE);
945         pkmap_page_table = pte;
946
947         flush_cache_all();
948         flush_tlb_all();
949
950         sparc_context_init(num_contexts);
951
952         kmap_init();
953
954         {
955                 unsigned long zones_size[MAX_NR_ZONES];
956                 unsigned long zholes_size[MAX_NR_ZONES];
957                 unsigned long npages;
958                 int znum;
959
960                 for (znum = 0; znum < MAX_NR_ZONES; znum++)
961                         zones_size[znum] = zholes_size[znum] = 0;
962
963                 npages = max_low_pfn - pfn_base;
964
965                 zones_size[ZONE_DMA] = npages;
966                 zholes_size[ZONE_DMA] = npages - pages_avail;
967
968                 npages = highend_pfn - max_low_pfn;
969                 zones_size[ZONE_HIGHMEM] = npages;
970                 zholes_size[ZONE_HIGHMEM] = npages - calc_highpages();
971
972                 free_area_init_node(0, zones_size, pfn_base, zholes_size);
973         }
974 }
975
976 void mmu_info(struct seq_file *m)
977 {
978         seq_printf(m,
979                    "MMU type\t: %s\n"
980                    "contexts\t: %d\n"
981                    "nocache total\t: %ld\n"
982                    "nocache used\t: %d\n",
983                    srmmu_name,
984                    num_contexts,
985                    srmmu_nocache_size,
986                    srmmu_nocache_map.used << SRMMU_NOCACHE_BITMAP_SHIFT);
987 }
988
989 int init_new_context(struct task_struct *tsk, struct mm_struct *mm)
990 {
991         mm->context = NO_CONTEXT;
992         return 0;
993 }
994
995 void destroy_context(struct mm_struct *mm)
996 {
997         unsigned long flags;
998
999         if (mm->context != NO_CONTEXT) {
1000                 flush_cache_mm(mm);
1001                 srmmu_ctxd_set(&srmmu_context_table[mm->context], srmmu_swapper_pg_dir);
1002                 flush_tlb_mm(mm);
1003                 spin_lock_irqsave(&srmmu_context_spinlock, flags);
1004                 free_context(mm->context);
1005                 spin_unlock_irqrestore(&srmmu_context_spinlock, flags);
1006                 mm->context = NO_CONTEXT;
1007         }
1008 }
1009
1010 /* Init various srmmu chip types. */
1011 static void __init srmmu_is_bad(void)
1012 {
1013         prom_printf("Could not determine SRMMU chip type.\n");
1014         prom_halt();
1015 }
1016
1017 static void __init init_vac_layout(void)
1018 {
1019         phandle nd;
1020         int cache_lines;
1021         char node_str[128];
1022 #ifdef CONFIG_SMP
1023         int cpu = 0;
1024         unsigned long max_size = 0;
1025         unsigned long min_line_size = 0x10000000;
1026 #endif
1027
1028         nd = prom_getchild(prom_root_node);
1029         while ((nd = prom_getsibling(nd)) != 0) {
1030                 prom_getstring(nd, "device_type", node_str, sizeof(node_str));
1031                 if (!strcmp(node_str, "cpu")) {
1032                         vac_line_size = prom_getint(nd, "cache-line-size");
1033                         if (vac_line_size == -1) {
1034                                 prom_printf("can't determine cache-line-size, halting.\n");
1035                                 prom_halt();
1036                         }
1037                         cache_lines = prom_getint(nd, "cache-nlines");
1038                         if (cache_lines == -1) {
1039                                 prom_printf("can't determine cache-nlines, halting.\n");
1040                                 prom_halt();
1041                         }
1042
1043                         vac_cache_size = cache_lines * vac_line_size;
1044 #ifdef CONFIG_SMP
1045                         if (vac_cache_size > max_size)
1046                                 max_size = vac_cache_size;
1047                         if (vac_line_size < min_line_size)
1048                                 min_line_size = vac_line_size;
1049                         //FIXME: cpus not contiguous!!
1050                         cpu++;
1051                         if (cpu >= nr_cpu_ids || !cpu_online(cpu))
1052                                 break;
1053 #else
1054                         break;
1055 #endif
1056                 }
1057         }
1058         if (nd == 0) {
1059                 prom_printf("No CPU nodes found, halting.\n");
1060                 prom_halt();
1061         }
1062 #ifdef CONFIG_SMP
1063         vac_cache_size = max_size;
1064         vac_line_size = min_line_size;
1065 #endif
1066         printk("SRMMU: Using VAC size of %d bytes, line size %d bytes.\n",
1067                (int)vac_cache_size, (int)vac_line_size);
1068 }
1069
1070 static void poke_hypersparc(void)
1071 {
1072         volatile unsigned long clear;
1073         unsigned long mreg = srmmu_get_mmureg();
1074
1075         hyper_flush_unconditional_combined();
1076
1077         mreg &= ~(HYPERSPARC_CWENABLE);
1078         mreg |= (HYPERSPARC_CENABLE | HYPERSPARC_WBENABLE);
1079         mreg |= (HYPERSPARC_CMODE);
1080
1081         srmmu_set_mmureg(mreg);
1082
1083 #if 0 /* XXX I think this is bad news... -DaveM */
1084         hyper_clear_all_tags();
1085 #endif
1086
1087         put_ross_icr(HYPERSPARC_ICCR_FTD | HYPERSPARC_ICCR_ICE);
1088         hyper_flush_whole_icache();
1089         clear = srmmu_get_faddr();
1090         clear = srmmu_get_fstatus();
1091 }
1092
1093 static const struct sparc32_cachetlb_ops hypersparc_ops = {
1094         .cache_all      = hypersparc_flush_cache_all,
1095         .cache_mm       = hypersparc_flush_cache_mm,
1096         .cache_page     = hypersparc_flush_cache_page,
1097         .cache_range    = hypersparc_flush_cache_range,
1098         .tlb_all        = hypersparc_flush_tlb_all,
1099         .tlb_mm         = hypersparc_flush_tlb_mm,
1100         .tlb_page       = hypersparc_flush_tlb_page,
1101         .tlb_range      = hypersparc_flush_tlb_range,
1102         .page_to_ram    = hypersparc_flush_page_to_ram,
1103         .sig_insns      = hypersparc_flush_sig_insns,
1104         .page_for_dma   = hypersparc_flush_page_for_dma,
1105 };
1106
1107 static void __init init_hypersparc(void)
1108 {
1109         srmmu_name = "ROSS HyperSparc";
1110         srmmu_modtype = HyperSparc;
1111
1112         init_vac_layout();
1113
1114         is_hypersparc = 1;
1115         sparc32_cachetlb_ops = &hypersparc_ops;
1116
1117         poke_srmmu = poke_hypersparc;
1118
1119         hypersparc_setup_blockops();
1120 }
1121
1122 static void poke_swift(void)
1123 {
1124         unsigned long mreg;
1125
1126         /* Clear any crap from the cache or else... */
1127         swift_flush_cache_all();
1128
1129         /* Enable I & D caches */
1130         mreg = srmmu_get_mmureg();
1131         mreg |= (SWIFT_IE | SWIFT_DE);
1132         /*
1133          * The Swift branch folding logic is completely broken.  At
1134          * trap time, if things are just right, if can mistakenly
1135          * think that a trap is coming from kernel mode when in fact
1136          * it is coming from user mode (it mis-executes the branch in
1137          * the trap code).  So you see things like crashme completely
1138          * hosing your machine which is completely unacceptable.  Turn
1139          * this shit off... nice job Fujitsu.
1140          */
1141         mreg &= ~(SWIFT_BF);
1142         srmmu_set_mmureg(mreg);
1143 }
1144
1145 static const struct sparc32_cachetlb_ops swift_ops = {
1146         .cache_all      = swift_flush_cache_all,
1147         .cache_mm       = swift_flush_cache_mm,
1148         .cache_page     = swift_flush_cache_page,
1149         .cache_range    = swift_flush_cache_range,
1150         .tlb_all        = swift_flush_tlb_all,
1151         .tlb_mm         = swift_flush_tlb_mm,
1152         .tlb_page       = swift_flush_tlb_page,
1153         .tlb_range      = swift_flush_tlb_range,
1154         .page_to_ram    = swift_flush_page_to_ram,
1155         .sig_insns      = swift_flush_sig_insns,
1156         .page_for_dma   = swift_flush_page_for_dma,
1157 };
1158
1159 #define SWIFT_MASKID_ADDR  0x10003018
1160 static void __init init_swift(void)
1161 {
1162         unsigned long swift_rev;
1163
1164         __asm__ __volatile__("lda [%1] %2, %0\n\t"
1165                              "srl %0, 0x18, %0\n\t" :
1166                              "=r" (swift_rev) :
1167                              "r" (SWIFT_MASKID_ADDR), "i" (ASI_M_BYPASS));
1168         srmmu_name = "Fujitsu Swift";
1169         switch (swift_rev) {
1170         case 0x11:
1171         case 0x20:
1172         case 0x23:
1173         case 0x30:
1174                 srmmu_modtype = Swift_lots_o_bugs;
1175                 hwbug_bitmask |= (HWBUG_KERN_ACCBROKEN | HWBUG_KERN_CBITBROKEN);
1176                 /*
1177                  * Gee george, I wonder why Sun is so hush hush about
1178                  * this hardware bug... really braindamage stuff going
1179                  * on here.  However I think we can find a way to avoid
1180                  * all of the workaround overhead under Linux.  Basically,
1181                  * any page fault can cause kernel pages to become user
1182                  * accessible (the mmu gets confused and clears some of
1183                  * the ACC bits in kernel ptes).  Aha, sounds pretty
1184                  * horrible eh?  But wait, after extensive testing it appears
1185                  * that if you use pgd_t level large kernel pte's (like the
1186                  * 4MB pages on the Pentium) the bug does not get tripped
1187                  * at all.  This avoids almost all of the major overhead.
1188                  * Welcome to a world where your vendor tells you to,
1189                  * "apply this kernel patch" instead of "sorry for the
1190                  * broken hardware, send it back and we'll give you
1191                  * properly functioning parts"
1192                  */
1193                 break;
1194         case 0x25:
1195         case 0x31:
1196                 srmmu_modtype = Swift_bad_c;
1197                 hwbug_bitmask |= HWBUG_KERN_CBITBROKEN;
1198                 /*
1199                  * You see Sun allude to this hardware bug but never
1200                  * admit things directly, they'll say things like,
1201                  * "the Swift chip cache problems" or similar.
1202                  */
1203                 break;
1204         default:
1205                 srmmu_modtype = Swift_ok;
1206                 break;
1207         }
1208
1209         sparc32_cachetlb_ops = &swift_ops;
1210         flush_page_for_dma_global = 0;
1211
1212         /*
1213          * Are you now convinced that the Swift is one of the
1214          * biggest VLSI abortions of all time?  Bravo Fujitsu!
1215          * Fujitsu, the !#?!%$'d up processor people.  I bet if
1216          * you examined the microcode of the Swift you'd find
1217          * XXX's all over the place.
1218          */
1219         poke_srmmu = poke_swift;
1220 }
1221
1222 static void turbosparc_flush_cache_all(void)
1223 {
1224         flush_user_windows();
1225         turbosparc_idflash_clear();
1226 }
1227
1228 static void turbosparc_flush_cache_mm(struct mm_struct *mm)
1229 {
1230         FLUSH_BEGIN(mm)
1231         flush_user_windows();
1232         turbosparc_idflash_clear();
1233         FLUSH_END
1234 }
1235
1236 static void turbosparc_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
1237 {
1238         FLUSH_BEGIN(vma->vm_mm)
1239         flush_user_windows();
1240         turbosparc_idflash_clear();
1241         FLUSH_END
1242 }
1243
1244 static void turbosparc_flush_cache_page(struct vm_area_struct *vma, unsigned long page)
1245 {
1246         FLUSH_BEGIN(vma->vm_mm)
1247         flush_user_windows();
1248         if (vma->vm_flags & VM_EXEC)
1249                 turbosparc_flush_icache();
1250         turbosparc_flush_dcache();
1251         FLUSH_END
1252 }
1253
1254 /* TurboSparc is copy-back, if we turn it on, but this does not work. */
1255 static void turbosparc_flush_page_to_ram(unsigned long page)
1256 {
1257 #ifdef TURBOSPARC_WRITEBACK
1258         volatile unsigned long clear;
1259
1260         if (srmmu_probe(page))
1261                 turbosparc_flush_page_cache(page);
1262         clear = srmmu_get_fstatus();
1263 #endif
1264 }
1265
1266 static void turbosparc_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr)
1267 {
1268 }
1269
1270 static void turbosparc_flush_page_for_dma(unsigned long page)
1271 {
1272         turbosparc_flush_dcache();
1273 }
1274
1275 static void turbosparc_flush_tlb_all(void)
1276 {
1277         srmmu_flush_whole_tlb();
1278 }
1279
1280 static void turbosparc_flush_tlb_mm(struct mm_struct *mm)
1281 {
1282         FLUSH_BEGIN(mm)
1283         srmmu_flush_whole_tlb();
1284         FLUSH_END
1285 }
1286
1287 static void turbosparc_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
1288 {
1289         FLUSH_BEGIN(vma->vm_mm)
1290         srmmu_flush_whole_tlb();
1291         FLUSH_END
1292 }
1293
1294 static void turbosparc_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
1295 {
1296         FLUSH_BEGIN(vma->vm_mm)
1297         srmmu_flush_whole_tlb();
1298         FLUSH_END
1299 }
1300
1301
1302 static void poke_turbosparc(void)
1303 {
1304         unsigned long mreg = srmmu_get_mmureg();
1305         unsigned long ccreg;
1306
1307         /* Clear any crap from the cache or else... */
1308         turbosparc_flush_cache_all();
1309         /* Temporarily disable I & D caches */
1310         mreg &= ~(TURBOSPARC_ICENABLE | TURBOSPARC_DCENABLE);
1311         mreg &= ~(TURBOSPARC_PCENABLE);         /* Don't check parity */
1312         srmmu_set_mmureg(mreg);
1313
1314         ccreg = turbosparc_get_ccreg();
1315
1316 #ifdef TURBOSPARC_WRITEBACK
1317         ccreg |= (TURBOSPARC_SNENABLE);         /* Do DVMA snooping in Dcache */
1318         ccreg &= ~(TURBOSPARC_uS2 | TURBOSPARC_WTENABLE);
1319                         /* Write-back D-cache, emulate VLSI
1320                          * abortion number three, not number one */
1321 #else
1322         /* For now let's play safe, optimize later */
1323         ccreg |= (TURBOSPARC_SNENABLE | TURBOSPARC_WTENABLE);
1324                         /* Do DVMA snooping in Dcache, Write-thru D-cache */
1325         ccreg &= ~(TURBOSPARC_uS2);
1326                         /* Emulate VLSI abortion number three, not number one */
1327 #endif
1328
1329         switch (ccreg & 7) {
1330         case 0: /* No SE cache */
1331         case 7: /* Test mode */
1332                 break;
1333         default:
1334                 ccreg |= (TURBOSPARC_SCENABLE);
1335         }
1336         turbosparc_set_ccreg(ccreg);
1337
1338         mreg |= (TURBOSPARC_ICENABLE | TURBOSPARC_DCENABLE); /* I & D caches on */
1339         mreg |= (TURBOSPARC_ICSNOOP);           /* Icache snooping on */
1340         srmmu_set_mmureg(mreg);
1341 }
1342
1343 static const struct sparc32_cachetlb_ops turbosparc_ops = {
1344         .cache_all      = turbosparc_flush_cache_all,
1345         .cache_mm       = turbosparc_flush_cache_mm,
1346         .cache_page     = turbosparc_flush_cache_page,
1347         .cache_range    = turbosparc_flush_cache_range,
1348         .tlb_all        = turbosparc_flush_tlb_all,
1349         .tlb_mm         = turbosparc_flush_tlb_mm,
1350         .tlb_page       = turbosparc_flush_tlb_page,
1351         .tlb_range      = turbosparc_flush_tlb_range,
1352         .page_to_ram    = turbosparc_flush_page_to_ram,
1353         .sig_insns      = turbosparc_flush_sig_insns,
1354         .page_for_dma   = turbosparc_flush_page_for_dma,
1355 };
1356
1357 static void __init init_turbosparc(void)
1358 {
1359         srmmu_name = "Fujitsu TurboSparc";
1360         srmmu_modtype = TurboSparc;
1361         sparc32_cachetlb_ops = &turbosparc_ops;
1362         poke_srmmu = poke_turbosparc;
1363 }
1364
1365 static void poke_tsunami(void)
1366 {
1367         unsigned long mreg = srmmu_get_mmureg();
1368
1369         tsunami_flush_icache();
1370         tsunami_flush_dcache();
1371         mreg &= ~TSUNAMI_ITD;
1372         mreg |= (TSUNAMI_IENAB | TSUNAMI_DENAB);
1373         srmmu_set_mmureg(mreg);
1374 }
1375
1376 static const struct sparc32_cachetlb_ops tsunami_ops = {
1377         .cache_all      = tsunami_flush_cache_all,
1378         .cache_mm       = tsunami_flush_cache_mm,
1379         .cache_page     = tsunami_flush_cache_page,
1380         .cache_range    = tsunami_flush_cache_range,
1381         .tlb_all        = tsunami_flush_tlb_all,
1382         .tlb_mm         = tsunami_flush_tlb_mm,
1383         .tlb_page       = tsunami_flush_tlb_page,
1384         .tlb_range      = tsunami_flush_tlb_range,
1385         .page_to_ram    = tsunami_flush_page_to_ram,
1386         .sig_insns      = tsunami_flush_sig_insns,
1387         .page_for_dma   = tsunami_flush_page_for_dma,
1388 };
1389
1390 static void __init init_tsunami(void)
1391 {
1392         /*
1393          * Tsunami's pretty sane, Sun and TI actually got it
1394          * somewhat right this time.  Fujitsu should have
1395          * taken some lessons from them.
1396          */
1397
1398         srmmu_name = "TI Tsunami";
1399         srmmu_modtype = Tsunami;
1400         sparc32_cachetlb_ops = &tsunami_ops;
1401         poke_srmmu = poke_tsunami;
1402
1403         tsunami_setup_blockops();
1404 }
1405
1406 static void poke_viking(void)
1407 {
1408         unsigned long mreg = srmmu_get_mmureg();
1409         static int smp_catch;
1410
1411         if (viking_mxcc_present) {
1412                 unsigned long mxcc_control = mxcc_get_creg();
1413
1414                 mxcc_control |= (MXCC_CTL_ECE | MXCC_CTL_PRE | MXCC_CTL_MCE);
1415                 mxcc_control &= ~(MXCC_CTL_RRC);
1416                 mxcc_set_creg(mxcc_control);
1417
1418                 /*
1419                  * We don't need memory parity checks.
1420                  * XXX This is a mess, have to dig out later. ecd.
1421                 viking_mxcc_turn_off_parity(&mreg, &mxcc_control);
1422                  */
1423
1424                 /* We do cache ptables on MXCC. */
1425                 mreg |= VIKING_TCENABLE;
1426         } else {
1427                 unsigned long bpreg;
1428
1429                 mreg &= ~(VIKING_TCENABLE);
1430                 if (smp_catch++) {
1431                         /* Must disable mixed-cmd mode here for other cpu's. */
1432                         bpreg = viking_get_bpreg();
1433                         bpreg &= ~(VIKING_ACTION_MIX);
1434                         viking_set_bpreg(bpreg);
1435
1436                         /* Just in case PROM does something funny. */
1437                         msi_set_sync();
1438                 }
1439         }
1440
1441         mreg |= VIKING_SPENABLE;
1442         mreg |= (VIKING_ICENABLE | VIKING_DCENABLE);
1443         mreg |= VIKING_SBENABLE;
1444         mreg &= ~(VIKING_ACENABLE);
1445         srmmu_set_mmureg(mreg);
1446 }
1447
1448 static struct sparc32_cachetlb_ops viking_ops = {
1449         .cache_all      = viking_flush_cache_all,
1450         .cache_mm       = viking_flush_cache_mm,
1451         .cache_page     = viking_flush_cache_page,
1452         .cache_range    = viking_flush_cache_range,
1453         .tlb_all        = viking_flush_tlb_all,
1454         .tlb_mm         = viking_flush_tlb_mm,
1455         .tlb_page       = viking_flush_tlb_page,
1456         .tlb_range      = viking_flush_tlb_range,
1457         .page_to_ram    = viking_flush_page_to_ram,
1458         .sig_insns      = viking_flush_sig_insns,
1459         .page_for_dma   = viking_flush_page_for_dma,
1460 };
1461
1462 #ifdef CONFIG_SMP
1463 /* On sun4d the cpu broadcasts local TLB flushes, so we can just
1464  * perform the local TLB flush and all the other cpus will see it.
1465  * But, unfortunately, there is a bug in the sun4d XBUS backplane
1466  * that requires that we add some synchronization to these flushes.
1467  *
1468  * The bug is that the fifo which keeps track of all the pending TLB
1469  * broadcasts in the system is an entry or two too small, so if we
1470  * have too many going at once we'll overflow that fifo and lose a TLB
1471  * flush resulting in corruption.
1472  *
1473  * Our workaround is to take a global spinlock around the TLB flushes,
1474  * which guarentees we won't ever have too many pending.  It's a big
1475  * hammer, but a semaphore like system to make sure we only have N TLB
1476  * flushes going at once will require SMP locking anyways so there's
1477  * no real value in trying any harder than this.
1478  */
1479 static struct sparc32_cachetlb_ops viking_sun4d_smp_ops = {
1480         .cache_all      = viking_flush_cache_all,
1481         .cache_mm       = viking_flush_cache_mm,
1482         .cache_page     = viking_flush_cache_page,
1483         .cache_range    = viking_flush_cache_range,
1484         .tlb_all        = sun4dsmp_flush_tlb_all,
1485         .tlb_mm         = sun4dsmp_flush_tlb_mm,
1486         .tlb_page       = sun4dsmp_flush_tlb_page,
1487         .tlb_range      = sun4dsmp_flush_tlb_range,
1488         .page_to_ram    = viking_flush_page_to_ram,
1489         .sig_insns      = viking_flush_sig_insns,
1490         .page_for_dma   = viking_flush_page_for_dma,
1491 };
1492 #endif
1493
1494 static void __init init_viking(void)
1495 {
1496         unsigned long mreg = srmmu_get_mmureg();
1497
1498         /* Ahhh, the viking.  SRMMU VLSI abortion number two... */
1499         if (mreg & VIKING_MMODE) {
1500                 srmmu_name = "TI Viking";
1501                 viking_mxcc_present = 0;
1502                 msi_set_sync();
1503
1504                 /*
1505                  * We need this to make sure old viking takes no hits
1506                  * on it's cache for dma snoops to workaround the
1507                  * "load from non-cacheable memory" interrupt bug.
1508                  * This is only necessary because of the new way in
1509                  * which we use the IOMMU.
1510                  */
1511                 viking_ops.page_for_dma = viking_flush_page;
1512 #ifdef CONFIG_SMP
1513                 viking_sun4d_smp_ops.page_for_dma = viking_flush_page;
1514 #endif
1515                 flush_page_for_dma_global = 0;
1516         } else {
1517                 srmmu_name = "TI Viking/MXCC";
1518                 viking_mxcc_present = 1;
1519                 srmmu_cache_pagetables = 1;
1520         }
1521
1522         sparc32_cachetlb_ops = (const struct sparc32_cachetlb_ops *)
1523                 &viking_ops;
1524 #ifdef CONFIG_SMP
1525         if (sparc_cpu_model == sun4d)
1526                 sparc32_cachetlb_ops = (const struct sparc32_cachetlb_ops *)
1527                         &viking_sun4d_smp_ops;
1528 #endif
1529
1530         poke_srmmu = poke_viking;
1531 }
1532
1533 /* Probe for the srmmu chip version. */
1534 static void __init get_srmmu_type(void)
1535 {
1536         unsigned long mreg, psr;
1537         unsigned long mod_typ, mod_rev, psr_typ, psr_vers;
1538
1539         srmmu_modtype = SRMMU_INVAL_MOD;
1540         hwbug_bitmask = 0;
1541
1542         mreg = srmmu_get_mmureg(); psr = get_psr();
1543         mod_typ = (mreg & 0xf0000000) >> 28;
1544         mod_rev = (mreg & 0x0f000000) >> 24;
1545         psr_typ = (psr >> 28) & 0xf;
1546         psr_vers = (psr >> 24) & 0xf;
1547
1548         /* First, check for sparc-leon. */
1549         if (sparc_cpu_model == sparc_leon) {
1550                 init_leon();
1551                 return;
1552         }
1553
1554         /* Second, check for HyperSparc or Cypress. */
1555         if (mod_typ == 1) {
1556                 switch (mod_rev) {
1557                 case 7:
1558                         /* UP or MP Hypersparc */
1559                         init_hypersparc();
1560                         break;
1561                 case 0:
1562                 case 2:
1563                 case 10:
1564                 case 11:
1565                 case 12:
1566                 case 13:
1567                 case 14:
1568                 case 15:
1569                 default:
1570                         prom_printf("Sparc-Linux Cypress support does not longer exit.\n");
1571                         prom_halt();
1572                         break;
1573                 }
1574                 return;
1575         }
1576
1577         /* Now Fujitsu TurboSparc. It might happen that it is
1578          * in Swift emulation mode, so we will check later...
1579          */
1580         if (psr_typ == 0 && psr_vers == 5) {
1581                 init_turbosparc();
1582                 return;
1583         }
1584
1585         /* Next check for Fujitsu Swift. */
1586         if (psr_typ == 0 && psr_vers == 4) {
1587                 phandle cpunode;
1588                 char node_str[128];
1589
1590                 /* Look if it is not a TurboSparc emulating Swift... */
1591                 cpunode = prom_getchild(prom_root_node);
1592                 while ((cpunode = prom_getsibling(cpunode)) != 0) {
1593                         prom_getstring(cpunode, "device_type", node_str, sizeof(node_str));
1594                         if (!strcmp(node_str, "cpu")) {
1595                                 if (!prom_getintdefault(cpunode, "psr-implementation", 1) &&
1596                                     prom_getintdefault(cpunode, "psr-version", 1) == 5) {
1597                                         init_turbosparc();
1598                                         return;
1599                                 }
1600                                 break;
1601                         }
1602                 }
1603
1604                 init_swift();
1605                 return;
1606         }
1607
1608         /* Now the Viking family of srmmu. */
1609         if (psr_typ == 4 &&
1610            ((psr_vers == 0) ||
1611             ((psr_vers == 1) && (mod_typ == 0) && (mod_rev == 0)))) {
1612                 init_viking();
1613                 return;
1614         }
1615
1616         /* Finally the Tsunami. */
1617         if (psr_typ == 4 && psr_vers == 1 && (mod_typ || mod_rev)) {
1618                 init_tsunami();
1619                 return;
1620         }
1621
1622         /* Oh well */
1623         srmmu_is_bad();
1624 }
1625
1626 #ifdef CONFIG_SMP
1627 /* Local cross-calls. */
1628 static void smp_flush_page_for_dma(unsigned long page)
1629 {
1630         xc1((smpfunc_t) local_ops->page_for_dma, page);
1631         local_ops->page_for_dma(page);
1632 }
1633
1634 static void smp_flush_cache_all(void)
1635 {
1636         xc0((smpfunc_t) local_ops->cache_all);
1637         local_ops->cache_all();
1638 }
1639
1640 static void smp_flush_tlb_all(void)
1641 {
1642         xc0((smpfunc_t) local_ops->tlb_all);
1643         local_ops->tlb_all();
1644 }
1645
1646 static void smp_flush_cache_mm(struct mm_struct *mm)
1647 {
1648         if (mm->context != NO_CONTEXT) {
1649                 cpumask_t cpu_mask;
1650                 cpumask_copy(&cpu_mask, mm_cpumask(mm));
1651                 cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
1652                 if (!cpumask_empty(&cpu_mask))
1653                         xc1((smpfunc_t) local_ops->cache_mm, (unsigned long) mm);
1654                 local_ops->cache_mm(mm);
1655         }
1656 }
1657
1658 static void smp_flush_tlb_mm(struct mm_struct *mm)
1659 {
1660         if (mm->context != NO_CONTEXT) {
1661                 cpumask_t cpu_mask;
1662                 cpumask_copy(&cpu_mask, mm_cpumask(mm));
1663                 cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
1664                 if (!cpumask_empty(&cpu_mask)) {
1665                         xc1((smpfunc_t) local_ops->tlb_mm, (unsigned long) mm);
1666                         if (atomic_read(&mm->mm_users) == 1 && current->active_mm == mm)
1667                                 cpumask_copy(mm_cpumask(mm),
1668                                              cpumask_of(smp_processor_id()));
1669                 }
1670                 local_ops->tlb_mm(mm);
1671         }
1672 }
1673
1674 static void smp_flush_cache_range(struct vm_area_struct *vma,
1675                                   unsigned long start,
1676                                   unsigned long end)
1677 {
1678         struct mm_struct *mm = vma->vm_mm;
1679
1680         if (mm->context != NO_CONTEXT) {
1681                 cpumask_t cpu_mask;
1682                 cpumask_copy(&cpu_mask, mm_cpumask(mm));
1683                 cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
1684                 if (!cpumask_empty(&cpu_mask))
1685                         xc3((smpfunc_t) local_ops->cache_range,
1686                             (unsigned long) vma, start, end);
1687                 local_ops->cache_range(vma, start, end);
1688         }
1689 }
1690
1691 static void smp_flush_tlb_range(struct vm_area_struct *vma,
1692                                 unsigned long start,
1693                                 unsigned long end)
1694 {
1695         struct mm_struct *mm = vma->vm_mm;
1696
1697         if (mm->context != NO_CONTEXT) {
1698                 cpumask_t cpu_mask;
1699                 cpumask_copy(&cpu_mask, mm_cpumask(mm));
1700                 cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
1701                 if (!cpumask_empty(&cpu_mask))
1702                         xc3((smpfunc_t) local_ops->tlb_range,
1703                             (unsigned long) vma, start, end);
1704                 local_ops->tlb_range(vma, start, end);
1705         }
1706 }
1707
1708 static void smp_flush_cache_page(struct vm_area_struct *vma, unsigned long page)
1709 {
1710         struct mm_struct *mm = vma->vm_mm;
1711
1712         if (mm->context != NO_CONTEXT) {
1713                 cpumask_t cpu_mask;
1714                 cpumask_copy(&cpu_mask, mm_cpumask(mm));
1715                 cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
1716                 if (!cpumask_empty(&cpu_mask))
1717                         xc2((smpfunc_t) local_ops->cache_page,
1718                             (unsigned long) vma, page);
1719                 local_ops->cache_page(vma, page);
1720         }
1721 }
1722
1723 static void smp_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
1724 {
1725         struct mm_struct *mm = vma->vm_mm;
1726
1727         if (mm->context != NO_CONTEXT) {
1728                 cpumask_t cpu_mask;
1729                 cpumask_copy(&cpu_mask, mm_cpumask(mm));
1730                 cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
1731                 if (!cpumask_empty(&cpu_mask))
1732                         xc2((smpfunc_t) local_ops->tlb_page,
1733                             (unsigned long) vma, page);
1734                 local_ops->tlb_page(vma, page);
1735         }
1736 }
1737
1738 static void smp_flush_page_to_ram(unsigned long page)
1739 {
1740         /* Current theory is that those who call this are the one's
1741          * who have just dirtied their cache with the pages contents
1742          * in kernel space, therefore we only run this on local cpu.
1743          *
1744          * XXX This experiment failed, research further... -DaveM
1745          */
1746 #if 1
1747         xc1((smpfunc_t) local_ops->page_to_ram, page);
1748 #endif
1749         local_ops->page_to_ram(page);
1750 }
1751
1752 static void smp_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr)
1753 {
1754         cpumask_t cpu_mask;
1755         cpumask_copy(&cpu_mask, mm_cpumask(mm));
1756         cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
1757         if (!cpumask_empty(&cpu_mask))
1758                 xc2((smpfunc_t) local_ops->sig_insns,
1759                     (unsigned long) mm, insn_addr);
1760         local_ops->sig_insns(mm, insn_addr);
1761 }
1762
1763 static struct sparc32_cachetlb_ops smp_cachetlb_ops = {
1764         .cache_all      = smp_flush_cache_all,
1765         .cache_mm       = smp_flush_cache_mm,
1766         .cache_page     = smp_flush_cache_page,
1767         .cache_range    = smp_flush_cache_range,
1768         .tlb_all        = smp_flush_tlb_all,
1769         .tlb_mm         = smp_flush_tlb_mm,
1770         .tlb_page       = smp_flush_tlb_page,
1771         .tlb_range      = smp_flush_tlb_range,
1772         .page_to_ram    = smp_flush_page_to_ram,
1773         .sig_insns      = smp_flush_sig_insns,
1774         .page_for_dma   = smp_flush_page_for_dma,
1775 };
1776 #endif
1777
1778 /* Load up routines and constants for sun4m and sun4d mmu */
1779 void __init load_mmu(void)
1780 {
1781         /* Functions */
1782         get_srmmu_type();
1783
1784 #ifdef CONFIG_SMP
1785         /* El switcheroo... */
1786         local_ops = sparc32_cachetlb_ops;
1787
1788         if (sparc_cpu_model == sun4d || sparc_cpu_model == sparc_leon) {
1789                 smp_cachetlb_ops.tlb_all = local_ops->tlb_all;
1790                 smp_cachetlb_ops.tlb_mm = local_ops->tlb_mm;
1791                 smp_cachetlb_ops.tlb_range = local_ops->tlb_range;
1792                 smp_cachetlb_ops.tlb_page = local_ops->tlb_page;
1793         }
1794
1795         if (poke_srmmu == poke_viking) {
1796                 /* Avoid unnecessary cross calls. */
1797                 smp_cachetlb_ops.cache_all = local_ops->cache_all;
1798                 smp_cachetlb_ops.cache_mm = local_ops->cache_mm;
1799                 smp_cachetlb_ops.cache_range = local_ops->cache_range;
1800                 smp_cachetlb_ops.cache_page = local_ops->cache_page;
1801
1802                 smp_cachetlb_ops.page_to_ram = local_ops->page_to_ram;
1803                 smp_cachetlb_ops.sig_insns = local_ops->sig_insns;
1804                 smp_cachetlb_ops.page_for_dma = local_ops->page_for_dma;
1805         }
1806
1807         /* It really is const after this point. */
1808         sparc32_cachetlb_ops = (const struct sparc32_cachetlb_ops *)
1809                 &smp_cachetlb_ops;
1810 #endif
1811
1812         if (sparc_cpu_model == sun4d)
1813                 ld_mmu_iounit();
1814         else
1815                 ld_mmu_iommu();
1816 #ifdef CONFIG_SMP
1817         if (sparc_cpu_model == sun4d)
1818                 sun4d_init_smp();
1819         else if (sparc_cpu_model == sparc_leon)
1820                 leon_init_smp();
1821         else
1822                 sun4m_init_smp();
1823 #endif
1824 }