1 // SPDX-License-Identifier: GPL-2.0
3 * iommu.c: IOMMU specific routines for memory management.
5 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
6 * Copyright (C) 1995,2002 Pete Zaitcev (zaitcev@yahoo.com)
7 * Copyright (C) 1996 Eddie C. Dost (ecd@skynet.be)
8 * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
11 #include <linux/kernel.h>
12 #include <linux/init.h>
14 #include <linux/slab.h>
15 #include <linux/dma-map-ops.h>
17 #include <linux/of_platform.h>
18 #include <linux/platform_device.h>
23 #include <asm/cacheflush.h>
24 #include <asm/tlbflush.h>
25 #include <asm/bitext.h>
26 #include <asm/iommu.h>
32 * This can be sized dynamically, but we will do this
33 * only when we have a guidance about actual I/O pressures.
35 #define IOMMU_RNGE IOMMU_RNGE_256MB
36 #define IOMMU_START 0xF0000000
37 #define IOMMU_WINSIZE (256*1024*1024U)
38 #define IOMMU_NPTES (IOMMU_WINSIZE/PAGE_SIZE) /* 64K PTEs, 256KB */
39 #define IOMMU_ORDER 6 /* 4096 * (1<<6) */
41 static int viking_flush;
43 extern void viking_flush_page(unsigned long page);
44 extern void viking_mxcc_flush_page(unsigned long page);
47 * Values precomputed according to CPU type.
49 static unsigned int ioperm_noc; /* Consistent mapping iopte flags */
50 static pgprot_t dvma_prot; /* Consistent mapping pte flags */
52 #define IOPERM (IOPTE_CACHE | IOPTE_WRITE | IOPTE_VALID)
53 #define MKIOPTE(pfn, perm) (((((pfn)<<8) & IOPTE_PAGE) | (perm)) & ~IOPTE_WAZ)
55 static const struct dma_map_ops sbus_iommu_dma_gflush_ops;
56 static const struct dma_map_ops sbus_iommu_dma_pflush_ops;
58 static void __init sbus_iommu_init(struct platform_device *op)
60 struct iommu_struct *iommu;
61 unsigned int impl, vers;
62 unsigned long *bitmap;
63 unsigned long control;
67 iommu = kmalloc(sizeof(struct iommu_struct), GFP_KERNEL);
69 prom_printf("Unable to allocate iommu structure\n");
73 iommu->regs = of_ioremap(&op->resource[0], 0, PAGE_SIZE * 3,
76 prom_printf("Cannot map IOMMU registers\n");
80 control = sbus_readl(&iommu->regs->control);
81 impl = (control & IOMMU_CTRL_IMPL) >> 28;
82 vers = (control & IOMMU_CTRL_VERS) >> 24;
83 control &= ~(IOMMU_CTRL_RNGE);
84 control |= (IOMMU_RNGE_256MB | IOMMU_CTRL_ENAB);
85 sbus_writel(control, &iommu->regs->control);
87 iommu_invalidate(iommu->regs);
88 iommu->start = IOMMU_START;
89 iommu->end = 0xffffffff;
91 /* Allocate IOMMU page table */
92 /* Stupid alignment constraints give me a headache.
93 We need 256K or 512K or 1M or 2M area aligned to
94 its size and current gfp will fortunately give
96 tmp = __get_free_pages(GFP_KERNEL, IOMMU_ORDER);
98 prom_printf("Unable to allocate iommu table [0x%lx]\n",
99 IOMMU_NPTES * sizeof(iopte_t));
102 iommu->page_table = (iopte_t *)tmp;
104 /* Initialize new table. */
105 memset(iommu->page_table, 0, IOMMU_NPTES*sizeof(iopte_t));
109 base = __pa((unsigned long)iommu->page_table) >> 4;
110 sbus_writel(base, &iommu->regs->base);
111 iommu_invalidate(iommu->regs);
113 bitmap = kmalloc(IOMMU_NPTES>>3, GFP_KERNEL);
115 prom_printf("Unable to allocate iommu bitmap [%d]\n",
116 (int)(IOMMU_NPTES>>3));
119 bit_map_init(&iommu->usemap, bitmap, IOMMU_NPTES);
120 /* To be coherent on HyperSparc, the page color of DVMA
121 * and physical addresses must match.
123 if (srmmu_modtype == HyperSparc)
124 iommu->usemap.num_colors = vac_cache_size >> PAGE_SHIFT;
126 iommu->usemap.num_colors = 1;
128 printk(KERN_INFO "IOMMU: impl %d vers %d table 0x%p[%d B] map [%d b]\n",
129 impl, vers, iommu->page_table,
130 (int)(IOMMU_NPTES*sizeof(iopte_t)), (int)IOMMU_NPTES);
132 op->dev.archdata.iommu = iommu;
134 if (flush_page_for_dma_global)
135 op->dev.dma_ops = &sbus_iommu_dma_gflush_ops;
137 op->dev.dma_ops = &sbus_iommu_dma_pflush_ops;
140 static int __init iommu_init(void)
142 struct device_node *dp;
144 for_each_node_by_name(dp, "iommu") {
145 struct platform_device *op = of_find_device_by_node(dp);
148 of_propagate_archdata(op);
154 subsys_initcall(iommu_init);
156 /* Flush the iotlb entries to ram. */
157 /* This could be better if we didn't have to flush whole pages. */
158 static void iommu_flush_iotlb(iopte_t *iopte, unsigned int niopte)
163 start = (unsigned long)iopte;
164 end = PAGE_ALIGN(start + niopte*sizeof(iopte_t));
166 if (viking_mxcc_present) {
168 viking_mxcc_flush_page(start);
171 } else if (viking_flush) {
173 viking_flush_page(start);
178 __flush_page_to_ram(start);
184 static dma_addr_t __sbus_iommu_map_page(struct device *dev, struct page *page,
185 unsigned long offset, size_t len, bool per_page_flush)
187 struct iommu_struct *iommu = dev->archdata.iommu;
188 phys_addr_t paddr = page_to_phys(page) + offset;
189 unsigned long off = paddr & ~PAGE_MASK;
190 unsigned long npages = (off + len + PAGE_SIZE - 1) >> PAGE_SHIFT;
191 unsigned long pfn = __phys_to_pfn(paddr);
192 unsigned int busa, busa0;
193 iopte_t *iopte, *iopte0;
196 /* XXX So what is maxphys for us and how do drivers know it? */
197 if (!len || len > 256 * 1024)
198 return DMA_MAPPING_ERROR;
201 * We expect unmapped highmem pages to be not in the cache.
202 * XXX Is this a good assumption?
203 * XXX What if someone else unmaps it here and races us?
205 if (per_page_flush && !PageHighMem(page)) {
206 unsigned long vaddr, p;
208 vaddr = (unsigned long)page_address(page) + offset;
209 for (p = vaddr & PAGE_MASK; p < vaddr + len; p += PAGE_SIZE)
210 flush_page_for_dma(p);
213 /* page color = pfn of page */
214 ioptex = bit_map_string_get(&iommu->usemap, npages, pfn);
217 busa0 = iommu->start + (ioptex << PAGE_SHIFT);
218 iopte0 = &iommu->page_table[ioptex];
222 for (i = 0; i < npages; i++) {
223 iopte_val(*iopte) = MKIOPTE(pfn, IOPERM);
224 iommu_invalidate_page(iommu->regs, busa);
230 iommu_flush_iotlb(iopte0, npages);
234 static dma_addr_t sbus_iommu_map_page_gflush(struct device *dev,
235 struct page *page, unsigned long offset, size_t len,
236 enum dma_data_direction dir, unsigned long attrs)
238 flush_page_for_dma(0);
239 return __sbus_iommu_map_page(dev, page, offset, len, false);
242 static dma_addr_t sbus_iommu_map_page_pflush(struct device *dev,
243 struct page *page, unsigned long offset, size_t len,
244 enum dma_data_direction dir, unsigned long attrs)
246 return __sbus_iommu_map_page(dev, page, offset, len, true);
249 static int __sbus_iommu_map_sg(struct device *dev, struct scatterlist *sgl,
250 int nents, enum dma_data_direction dir, unsigned long attrs,
253 struct scatterlist *sg;
256 for_each_sg(sgl, sg, nents, j) {
257 sg->dma_address =__sbus_iommu_map_page(dev, sg_page(sg),
258 sg->offset, sg->length, per_page_flush);
259 if (sg->dma_address == DMA_MAPPING_ERROR)
261 sg->dma_length = sg->length;
267 static int sbus_iommu_map_sg_gflush(struct device *dev, struct scatterlist *sgl,
268 int nents, enum dma_data_direction dir, unsigned long attrs)
270 flush_page_for_dma(0);
271 return __sbus_iommu_map_sg(dev, sgl, nents, dir, attrs, false);
274 static int sbus_iommu_map_sg_pflush(struct device *dev, struct scatterlist *sgl,
275 int nents, enum dma_data_direction dir, unsigned long attrs)
277 return __sbus_iommu_map_sg(dev, sgl, nents, dir, attrs, true);
280 static void sbus_iommu_unmap_page(struct device *dev, dma_addr_t dma_addr,
281 size_t len, enum dma_data_direction dir, unsigned long attrs)
283 struct iommu_struct *iommu = dev->archdata.iommu;
284 unsigned int busa = dma_addr & PAGE_MASK;
285 unsigned long off = dma_addr & ~PAGE_MASK;
286 unsigned int npages = (off + len + PAGE_SIZE-1) >> PAGE_SHIFT;
287 unsigned int ioptex = (busa - iommu->start) >> PAGE_SHIFT;
290 BUG_ON(busa < iommu->start);
291 for (i = 0; i < npages; i++) {
292 iopte_val(iommu->page_table[ioptex + i]) = 0;
293 iommu_invalidate_page(iommu->regs, busa);
296 bit_map_clear(&iommu->usemap, ioptex, npages);
299 static void sbus_iommu_unmap_sg(struct device *dev, struct scatterlist *sgl,
300 int nents, enum dma_data_direction dir, unsigned long attrs)
302 struct scatterlist *sg;
305 for_each_sg(sgl, sg, nents, i) {
306 sbus_iommu_unmap_page(dev, sg->dma_address, sg->length, dir,
308 sg->dma_address = 0x21212121;
313 static void *sbus_iommu_alloc(struct device *dev, size_t len,
314 dma_addr_t *dma_handle, gfp_t gfp, unsigned long attrs)
316 struct iommu_struct *iommu = dev->archdata.iommu;
317 unsigned long va, addr, page, end, ret;
318 iopte_t *iopte = iommu->page_table;
322 /* XXX So what is maxphys for us and how do drivers know it? */
323 if (!len || len > 256 * 1024)
326 len = PAGE_ALIGN(len);
327 va = __get_free_pages(gfp | __GFP_ZERO, get_order(len));
331 addr = ret = sparc_dma_alloc_resource(dev, len);
335 BUG_ON((va & ~PAGE_MASK) != 0);
336 BUG_ON((addr & ~PAGE_MASK) != 0);
337 BUG_ON((len & ~PAGE_MASK) != 0);
339 /* page color = physical address */
340 ioptex = bit_map_string_get(&iommu->usemap, len >> PAGE_SHIFT,
354 if (viking_mxcc_present)
355 viking_mxcc_flush_page(page);
356 else if (viking_flush)
357 viking_flush_page(page);
359 __flush_page_to_ram(page);
361 pmdp = pmd_off_k(addr);
362 ptep = pte_offset_kernel(pmdp, addr);
364 set_pte(ptep, mk_pte(virt_to_page(page), dvma_prot));
366 iopte_val(*iopte++) =
367 MKIOPTE(page_to_pfn(virt_to_page(page)), ioperm_noc);
371 /* P3: why do we need this?
373 * DAVEM: Because there are several aspects, none of which
374 * are handled by a single interface. Some cpus are
375 * completely not I/O DMA coherent, and some have
376 * virtually indexed caches. The driver DMA flushing
377 * methods handle the former case, but here during
378 * IOMMU page table modifications, and usage of non-cacheable
379 * cpu mappings of pages potentially in the cpu caches, we have
380 * to handle the latter case as well.
383 iommu_flush_iotlb(first, len >> PAGE_SHIFT);
385 iommu_invalidate(iommu->regs);
387 *dma_handle = iommu->start + (ioptex << PAGE_SHIFT);
391 free_pages(va, get_order(len));
395 static void sbus_iommu_free(struct device *dev, size_t len, void *cpu_addr,
396 dma_addr_t busa, unsigned long attrs)
398 struct iommu_struct *iommu = dev->archdata.iommu;
399 iopte_t *iopte = iommu->page_table;
400 struct page *page = virt_to_page(cpu_addr);
401 int ioptex = (busa - iommu->start) >> PAGE_SHIFT;
404 if (!sparc_dma_free_resource(cpu_addr, len))
407 BUG_ON((busa & ~PAGE_MASK) != 0);
408 BUG_ON((len & ~PAGE_MASK) != 0);
413 iopte_val(*iopte++) = 0;
417 iommu_invalidate(iommu->regs);
418 bit_map_clear(&iommu->usemap, ioptex, len >> PAGE_SHIFT);
420 __free_pages(page, get_order(len));
424 static const struct dma_map_ops sbus_iommu_dma_gflush_ops = {
426 .alloc = sbus_iommu_alloc,
427 .free = sbus_iommu_free,
429 .map_page = sbus_iommu_map_page_gflush,
430 .unmap_page = sbus_iommu_unmap_page,
431 .map_sg = sbus_iommu_map_sg_gflush,
432 .unmap_sg = sbus_iommu_unmap_sg,
435 static const struct dma_map_ops sbus_iommu_dma_pflush_ops = {
437 .alloc = sbus_iommu_alloc,
438 .free = sbus_iommu_free,
440 .map_page = sbus_iommu_map_page_pflush,
441 .unmap_page = sbus_iommu_unmap_page,
442 .map_sg = sbus_iommu_map_sg_pflush,
443 .unmap_sg = sbus_iommu_unmap_sg,
446 void __init ld_mmu_iommu(void)
448 if (viking_mxcc_present || srmmu_modtype == HyperSparc) {
449 dvma_prot = __pgprot(SRMMU_CACHE | SRMMU_ET_PTE | SRMMU_PRIV);
450 ioperm_noc = IOPTE_CACHE | IOPTE_WRITE | IOPTE_VALID;
452 dvma_prot = __pgprot(SRMMU_ET_PTE | SRMMU_PRIV);
453 ioperm_noc = IOPTE_WRITE | IOPTE_VALID;