1 // SPDX-License-Identifier: GPL-2.0
3 * arch/sparc64/mm/init.c
5 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
6 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
9 #include <linux/extable.h>
10 #include <linux/kernel.h>
11 #include <linux/sched.h>
12 #include <linux/string.h>
13 #include <linux/init.h>
14 #include <linux/memblock.h>
16 #include <linux/hugetlb.h>
17 #include <linux/initrd.h>
18 #include <linux/swap.h>
19 #include <linux/pagemap.h>
20 #include <linux/poison.h>
22 #include <linux/seq_file.h>
23 #include <linux/kprobes.h>
24 #include <linux/cache.h>
25 #include <linux/sort.h>
26 #include <linux/ioport.h>
27 #include <linux/percpu.h>
28 #include <linux/mmzone.h>
29 #include <linux/gfp.h>
30 #include <linux/bootmem_info.h>
34 #include <asm/pgalloc.h>
35 #include <asm/oplib.h>
36 #include <asm/iommu.h>
38 #include <linux/uaccess.h>
39 #include <asm/mmu_context.h>
40 #include <asm/tlbflush.h>
42 #include <asm/starfire.h>
44 #include <asm/spitfire.h>
45 #include <asm/sections.h>
47 #include <asm/hypervisor.h>
49 #include <asm/mdesc.h>
50 #include <asm/cpudata.h>
51 #include <asm/setup.h>
56 unsigned long kern_linear_pte_xor[4] __read_mostly;
57 static unsigned long page_cache4v_flag;
59 /* A bitmap, two bits for every 256MB of physical memory. These two
60 * bits determine what page size we use for kernel linear
61 * translations. They form an index into kern_linear_pte_xor[]. The
62 * value in the indexed slot is XOR'd with the TLB miss virtual
63 * address to form the resulting TTE. The mapping is:
70 * All sun4v chips support 256MB pages. Only SPARC-T4 and later
71 * support 2GB pages, and hopefully future cpus will support the 16GB
72 * pages as well. For slots 2 and 3, we encode a 256MB TTE xor there
73 * if these larger page sizes are not supported by the cpu.
75 * It would be nice to determine this from the machine description
76 * 'cpu' properties, but we need to have this table setup before the
77 * MDESC is initialized.
80 #ifndef CONFIG_DEBUG_PAGEALLOC
81 /* A special kernel TSB for 4MB, 256MB, 2GB and 16GB linear mappings.
82 * Space is allocated for this right after the trap table in
83 * arch/sparc64/kernel/head.S
85 extern struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES];
87 extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
89 static unsigned long cpu_pgsz_mask;
91 #define MAX_BANKS 1024
93 static struct linux_prom64_registers pavail[MAX_BANKS];
94 static int pavail_ents;
96 u64 numa_latency[MAX_NUMNODES][MAX_NUMNODES];
98 static int cmp_p64(const void *a, const void *b)
100 const struct linux_prom64_registers *x = a, *y = b;
102 if (x->phys_addr > y->phys_addr)
104 if (x->phys_addr < y->phys_addr)
109 static void __init read_obp_memory(const char *property,
110 struct linux_prom64_registers *regs,
113 phandle node = prom_finddevice("/memory");
114 int prop_size = prom_getproplen(node, property);
117 ents = prop_size / sizeof(struct linux_prom64_registers);
118 if (ents > MAX_BANKS) {
119 prom_printf("The machine has more %s property entries than "
120 "this kernel can support (%d).\n",
121 property, MAX_BANKS);
125 ret = prom_getproperty(node, property, (char *) regs, prop_size);
127 prom_printf("Couldn't get %s property from /memory.\n",
132 /* Sanitize what we got from the firmware, by page aligning
135 for (i = 0; i < ents; i++) {
136 unsigned long base, size;
138 base = regs[i].phys_addr;
139 size = regs[i].reg_size;
142 if (base & ~PAGE_MASK) {
143 unsigned long new_base = PAGE_ALIGN(base);
145 size -= new_base - base;
146 if ((long) size < 0L)
151 /* If it is empty, simply get rid of it.
152 * This simplifies the logic of the other
153 * functions that process these arrays.
155 memmove(®s[i], ®s[i + 1],
156 (ents - i - 1) * sizeof(regs[0]));
161 regs[i].phys_addr = base;
162 regs[i].reg_size = size;
167 sort(regs, ents, sizeof(struct linux_prom64_registers),
171 /* Kernel physical address base and size in bytes. */
172 unsigned long kern_base __read_mostly;
173 unsigned long kern_size __read_mostly;
175 /* Initial ramdisk setup */
176 extern unsigned long sparc_ramdisk_image64;
177 extern unsigned int sparc_ramdisk_image;
178 extern unsigned int sparc_ramdisk_size;
180 struct page *mem_map_zero __read_mostly;
181 EXPORT_SYMBOL(mem_map_zero);
183 unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
185 unsigned long sparc64_kern_pri_context __read_mostly;
186 unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
187 unsigned long sparc64_kern_sec_context __read_mostly;
189 int num_kernel_image_mappings;
191 #ifdef CONFIG_DEBUG_DCFLUSH
192 atomic_t dcpage_flushes = ATOMIC_INIT(0);
194 atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
198 inline void flush_dcache_folio_impl(struct folio *folio)
200 unsigned int i, nr = folio_nr_pages(folio);
202 BUG_ON(tlb_type == hypervisor);
203 #ifdef CONFIG_DEBUG_DCFLUSH
204 atomic_inc(&dcpage_flushes);
207 #ifdef DCACHE_ALIASING_POSSIBLE
208 for (i = 0; i < nr; i++)
209 __flush_dcache_page(folio_address(folio) + i * PAGE_SIZE,
210 ((tlb_type == spitfire) &&
211 folio_flush_mapping(folio) != NULL));
213 if (folio_flush_mapping(folio) != NULL &&
214 tlb_type == spitfire) {
215 for (i = 0; i < nr; i++)
216 __flush_icache_page((pfn + i) * PAGE_SIZE);
221 #define PG_dcache_dirty PG_arch_1
222 #define PG_dcache_cpu_shift 32UL
223 #define PG_dcache_cpu_mask \
224 ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL)
226 #define dcache_dirty_cpu(folio) \
227 (((folio)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
229 static inline void set_dcache_dirty(struct folio *folio, int this_cpu)
231 unsigned long mask = this_cpu;
232 unsigned long non_cpu_bits;
234 non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
235 mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
237 __asm__ __volatile__("1:\n\t"
239 "and %%g7, %1, %%g1\n\t"
240 "or %%g1, %0, %%g1\n\t"
241 "casx [%2], %%g7, %%g1\n\t"
243 "bne,pn %%xcc, 1b\n\t"
246 : "r" (mask), "r" (non_cpu_bits), "r" (&folio->flags)
250 static inline void clear_dcache_dirty_cpu(struct folio *folio, unsigned long cpu)
252 unsigned long mask = (1UL << PG_dcache_dirty);
254 __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
257 "srlx %%g7, %4, %%g1\n\t"
258 "and %%g1, %3, %%g1\n\t"
260 "bne,pn %%icc, 2f\n\t"
261 " andn %%g7, %1, %%g1\n\t"
262 "casx [%2], %%g7, %%g1\n\t"
264 "bne,pn %%xcc, 1b\n\t"
268 : "r" (cpu), "r" (mask), "r" (&folio->flags),
269 "i" (PG_dcache_cpu_mask),
270 "i" (PG_dcache_cpu_shift)
274 static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
276 unsigned long tsb_addr = (unsigned long) ent;
278 if (tlb_type == cheetah_plus || tlb_type == hypervisor)
279 tsb_addr = __pa(tsb_addr);
281 __tsb_insert(tsb_addr, tag, pte);
284 unsigned long _PAGE_ALL_SZ_BITS __read_mostly;
286 static void flush_dcache(unsigned long pfn)
290 page = pfn_to_page(pfn);
292 struct folio *folio = page_folio(page);
293 unsigned long pg_flags;
295 pg_flags = folio->flags;
296 if (pg_flags & (1UL << PG_dcache_dirty)) {
297 int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
299 int this_cpu = get_cpu();
301 /* This is just to optimize away some function calls
305 flush_dcache_folio_impl(folio);
307 smp_flush_dcache_folio_impl(folio, cpu);
309 clear_dcache_dirty_cpu(folio, cpu);
316 /* mm->context.lock must be held */
317 static void __update_mmu_tsb_insert(struct mm_struct *mm, unsigned long tsb_index,
318 unsigned long tsb_hash_shift, unsigned long address,
321 struct tsb *tsb = mm->context.tsb_block[tsb_index].tsb;
327 tsb += ((address >> tsb_hash_shift) &
328 (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL));
329 tag = (address >> 22UL);
330 tsb_insert(tsb, tag, tte);
333 #ifdef CONFIG_HUGETLB_PAGE
334 static int __init hugetlbpage_init(void)
336 hugetlb_add_hstate(HPAGE_64K_SHIFT - PAGE_SHIFT);
337 hugetlb_add_hstate(HPAGE_SHIFT - PAGE_SHIFT);
338 hugetlb_add_hstate(HPAGE_256MB_SHIFT - PAGE_SHIFT);
339 hugetlb_add_hstate(HPAGE_2GB_SHIFT - PAGE_SHIFT);
344 arch_initcall(hugetlbpage_init);
346 static void __init pud_huge_patch(void)
348 struct pud_huge_patch_entry *p;
351 p = &__pud_huge_patch;
353 *(unsigned int *)addr = p->insn;
355 __asm__ __volatile__("flush %0" : : "r" (addr));
358 bool __init arch_hugetlb_valid_size(unsigned long size)
360 unsigned int hugepage_shift = ilog2(size);
361 unsigned short hv_pgsz_idx;
362 unsigned int hv_pgsz_mask;
364 switch (hugepage_shift) {
365 case HPAGE_16GB_SHIFT:
366 hv_pgsz_mask = HV_PGSZ_MASK_16GB;
367 hv_pgsz_idx = HV_PGSZ_IDX_16GB;
370 case HPAGE_2GB_SHIFT:
371 hv_pgsz_mask = HV_PGSZ_MASK_2GB;
372 hv_pgsz_idx = HV_PGSZ_IDX_2GB;
374 case HPAGE_256MB_SHIFT:
375 hv_pgsz_mask = HV_PGSZ_MASK_256MB;
376 hv_pgsz_idx = HV_PGSZ_IDX_256MB;
379 hv_pgsz_mask = HV_PGSZ_MASK_4MB;
380 hv_pgsz_idx = HV_PGSZ_IDX_4MB;
382 case HPAGE_64K_SHIFT:
383 hv_pgsz_mask = HV_PGSZ_MASK_64K;
384 hv_pgsz_idx = HV_PGSZ_IDX_64K;
390 if ((hv_pgsz_mask & cpu_pgsz_mask) == 0U)
395 #endif /* CONFIG_HUGETLB_PAGE */
397 void update_mmu_cache_range(struct vm_fault *vmf, struct vm_area_struct *vma,
398 unsigned long address, pte_t *ptep, unsigned int nr)
400 struct mm_struct *mm;
406 if (tlb_type != hypervisor) {
407 unsigned long pfn = pte_pfn(pte);
415 /* Don't insert a non-valid PTE into the TSB, we'll deadlock. */
416 if (!pte_accessible(mm, pte))
419 spin_lock_irqsave(&mm->context.lock, flags);
422 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
423 if (mm->context.hugetlb_pte_count || mm->context.thp_pte_count) {
424 unsigned long hugepage_size = PAGE_SIZE;
426 if (is_vm_hugetlb_page(vma))
427 hugepage_size = huge_page_size(hstate_vma(vma));
429 if (hugepage_size >= PUD_SIZE) {
430 unsigned long mask = 0x1ffc00000UL;
432 /* Transfer bits [32:22] from address to resolve
435 pte_val(pte) &= ~mask;
436 pte_val(pte) |= (address & mask);
437 } else if (hugepage_size >= PMD_SIZE) {
438 /* We are fabricating 8MB pages using 4MB
441 pte_val(pte) |= (address & (1UL << REAL_HPAGE_SHIFT));
444 if (hugepage_size >= PMD_SIZE) {
445 __update_mmu_tsb_insert(mm, MM_TSB_HUGE,
446 REAL_HPAGE_SHIFT, address, pte_val(pte));
452 for (i = 0; i < nr; i++) {
453 __update_mmu_tsb_insert(mm, MM_TSB_BASE, PAGE_SHIFT,
454 address, pte_val(pte));
455 address += PAGE_SIZE;
456 pte_val(pte) += PAGE_SIZE;
460 spin_unlock_irqrestore(&mm->context.lock, flags);
463 void flush_dcache_folio(struct folio *folio)
465 unsigned long pfn = folio_pfn(folio);
466 struct address_space *mapping;
469 if (tlb_type == hypervisor)
472 /* Do not bother with the expensive D-cache flush if it
473 * is merely the zero page. The 'bigcore' testcase in GDB
474 * causes this case to run millions of times.
476 if (is_zero_pfn(pfn))
479 this_cpu = get_cpu();
481 mapping = folio_flush_mapping(folio);
482 if (mapping && !mapping_mapped(mapping)) {
483 bool dirty = test_bit(PG_dcache_dirty, &folio->flags);
485 int dirty_cpu = dcache_dirty_cpu(folio);
487 if (dirty_cpu == this_cpu)
489 smp_flush_dcache_folio_impl(folio, dirty_cpu);
491 set_dcache_dirty(folio, this_cpu);
493 /* We could delay the flush for the !page_mapping
494 * case too. But that case is for exec env/arg
495 * pages and those are %99 certainly going to get
496 * faulted into the tlb (and thus flushed) anyways.
498 flush_dcache_folio_impl(folio);
504 EXPORT_SYMBOL(flush_dcache_folio);
506 void __kprobes flush_icache_range(unsigned long start, unsigned long end)
508 /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
509 if (tlb_type == spitfire) {
512 /* This code only runs on Spitfire cpus so this is
513 * why we can assume _PAGE_PADDR_4U.
515 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE) {
516 unsigned long paddr, mask = _PAGE_PADDR_4U;
518 if (kaddr >= PAGE_OFFSET)
519 paddr = kaddr & mask;
521 pte_t *ptep = virt_to_kpte(kaddr);
523 paddr = pte_val(*ptep) & mask;
525 __flush_icache_page(paddr);
529 EXPORT_SYMBOL(flush_icache_range);
531 void mmu_info(struct seq_file *m)
533 static const char *pgsz_strings[] = {
534 "8K", "64K", "512K", "4MB", "32MB",
535 "256MB", "2GB", "16GB",
539 if (tlb_type == cheetah)
540 seq_printf(m, "MMU Type\t: Cheetah\n");
541 else if (tlb_type == cheetah_plus)
542 seq_printf(m, "MMU Type\t: Cheetah+\n");
543 else if (tlb_type == spitfire)
544 seq_printf(m, "MMU Type\t: Spitfire\n");
545 else if (tlb_type == hypervisor)
546 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
548 seq_printf(m, "MMU Type\t: ???\n");
550 seq_printf(m, "MMU PGSZs\t: ");
552 for (i = 0; i < ARRAY_SIZE(pgsz_strings); i++) {
553 if (cpu_pgsz_mask & (1UL << i)) {
554 seq_printf(m, "%s%s",
555 printed ? "," : "", pgsz_strings[i]);
561 #ifdef CONFIG_DEBUG_DCFLUSH
562 seq_printf(m, "DCPageFlushes\t: %d\n",
563 atomic_read(&dcpage_flushes));
565 seq_printf(m, "DCPageFlushesXC\t: %d\n",
566 atomic_read(&dcpage_flushes_xcall));
567 #endif /* CONFIG_SMP */
568 #endif /* CONFIG_DEBUG_DCFLUSH */
571 struct linux_prom_translation prom_trans[512] __read_mostly;
572 unsigned int prom_trans_ents __read_mostly;
574 unsigned long kern_locked_tte_data;
576 /* The obp translations are saved based on 8k pagesize, since obp can
577 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
578 * HI_OBP_ADDRESS range are handled in ktlb.S.
580 static inline int in_obp_range(unsigned long vaddr)
582 return (vaddr >= LOW_OBP_ADDRESS &&
583 vaddr < HI_OBP_ADDRESS);
586 static int cmp_ptrans(const void *a, const void *b)
588 const struct linux_prom_translation *x = a, *y = b;
590 if (x->virt > y->virt)
592 if (x->virt < y->virt)
597 /* Read OBP translations property into 'prom_trans[]'. */
598 static void __init read_obp_translations(void)
600 int n, node, ents, first, last, i;
602 node = prom_finddevice("/virtual-memory");
603 n = prom_getproplen(node, "translations");
604 if (unlikely(n == 0 || n == -1)) {
605 prom_printf("prom_mappings: Couldn't get size.\n");
608 if (unlikely(n > sizeof(prom_trans))) {
609 prom_printf("prom_mappings: Size %d is too big.\n", n);
613 if ((n = prom_getproperty(node, "translations",
614 (char *)&prom_trans[0],
615 sizeof(prom_trans))) == -1) {
616 prom_printf("prom_mappings: Couldn't get property.\n");
620 n = n / sizeof(struct linux_prom_translation);
624 sort(prom_trans, ents, sizeof(struct linux_prom_translation),
627 /* Now kick out all the non-OBP entries. */
628 for (i = 0; i < ents; i++) {
629 if (in_obp_range(prom_trans[i].virt))
633 for (; i < ents; i++) {
634 if (!in_obp_range(prom_trans[i].virt))
639 for (i = 0; i < (last - first); i++) {
640 struct linux_prom_translation *src = &prom_trans[i + first];
641 struct linux_prom_translation *dest = &prom_trans[i];
645 for (; i < ents; i++) {
646 struct linux_prom_translation *dest = &prom_trans[i];
647 dest->virt = dest->size = dest->data = 0x0UL;
650 prom_trans_ents = last - first;
652 if (tlb_type == spitfire) {
653 /* Clear diag TTE bits. */
654 for (i = 0; i < prom_trans_ents; i++)
655 prom_trans[i].data &= ~0x0003fe0000000000UL;
658 /* Force execute bit on. */
659 for (i = 0; i < prom_trans_ents; i++)
660 prom_trans[i].data |= (tlb_type == hypervisor ?
661 _PAGE_EXEC_4V : _PAGE_EXEC_4U);
664 static void __init hypervisor_tlb_lock(unsigned long vaddr,
668 unsigned long ret = sun4v_mmu_map_perm_addr(vaddr, 0, pte, mmu);
671 prom_printf("hypervisor_tlb_lock[%lx:%x:%lx:%lx]: "
672 "errors with %lx\n", vaddr, 0, pte, mmu, ret);
677 static unsigned long kern_large_tte(unsigned long paddr);
679 static void __init remap_kernel(void)
681 unsigned long phys_page, tte_vaddr, tte_data;
682 int i, tlb_ent = sparc64_highest_locked_tlbent();
684 tte_vaddr = (unsigned long) KERNBASE;
685 phys_page = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB;
686 tte_data = kern_large_tte(phys_page);
688 kern_locked_tte_data = tte_data;
690 /* Now lock us into the TLBs via Hypervisor or OBP. */
691 if (tlb_type == hypervisor) {
692 for (i = 0; i < num_kernel_image_mappings; i++) {
693 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
694 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
695 tte_vaddr += 0x400000;
696 tte_data += 0x400000;
699 for (i = 0; i < num_kernel_image_mappings; i++) {
700 prom_dtlb_load(tlb_ent - i, tte_data, tte_vaddr);
701 prom_itlb_load(tlb_ent - i, tte_data, tte_vaddr);
702 tte_vaddr += 0x400000;
703 tte_data += 0x400000;
705 sparc64_highest_unlocked_tlb_ent = tlb_ent - i;
707 if (tlb_type == cheetah_plus) {
708 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
709 CTX_CHEETAH_PLUS_NUC);
710 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
711 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
716 static void __init inherit_prom_mappings(void)
718 /* Now fixup OBP's idea about where we really are mapped. */
719 printk("Remapping the kernel... ");
724 void prom_world(int enter)
727 * No need to change the address space any more, just flush
728 * the register windows
730 __asm__ __volatile__("flushw");
733 void __flush_dcache_range(unsigned long start, unsigned long end)
737 if (tlb_type == spitfire) {
740 for (va = start; va < end; va += 32) {
741 spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
745 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
748 for (va = start; va < end; va += 32)
749 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
753 "i" (ASI_DCACHE_INVALIDATE));
756 EXPORT_SYMBOL(__flush_dcache_range);
758 /* get_new_mmu_context() uses "cache + 1". */
759 DEFINE_SPINLOCK(ctx_alloc_lock);
760 unsigned long tlb_context_cache = CTX_FIRST_VERSION;
761 #define MAX_CTX_NR (1UL << CTX_NR_BITS)
762 #define CTX_BMAP_SLOTS BITS_TO_LONGS(MAX_CTX_NR)
763 DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR);
764 DEFINE_PER_CPU(struct mm_struct *, per_cpu_secondary_mm) = {0};
766 static void mmu_context_wrap(void)
768 unsigned long old_ver = tlb_context_cache & CTX_VERSION_MASK;
769 unsigned long new_ver, new_ctx, old_ctx;
770 struct mm_struct *mm;
773 bitmap_zero(mmu_context_bmap, 1 << CTX_NR_BITS);
775 /* Reserve kernel context */
776 set_bit(0, mmu_context_bmap);
778 new_ver = (tlb_context_cache & CTX_VERSION_MASK) + CTX_FIRST_VERSION;
779 if (unlikely(new_ver == 0))
780 new_ver = CTX_FIRST_VERSION;
781 tlb_context_cache = new_ver;
784 * Make sure that any new mm that are added into per_cpu_secondary_mm,
785 * are going to go through get_new_mmu_context() path.
790 * Updated versions to current on those CPUs that had valid secondary
793 for_each_online_cpu(cpu) {
795 * If a new mm is stored after we took this mm from the array,
796 * it will go into get_new_mmu_context() path, because we
797 * already bumped the version in tlb_context_cache.
799 mm = per_cpu(per_cpu_secondary_mm, cpu);
801 if (unlikely(!mm || mm == &init_mm))
804 old_ctx = mm->context.sparc64_ctx_val;
805 if (likely((old_ctx & CTX_VERSION_MASK) == old_ver)) {
806 new_ctx = (old_ctx & ~CTX_VERSION_MASK) | new_ver;
807 set_bit(new_ctx & CTX_NR_MASK, mmu_context_bmap);
808 mm->context.sparc64_ctx_val = new_ctx;
813 /* Caller does TLB context flushing on local CPU if necessary.
814 * The caller also ensures that CTX_VALID(mm->context) is false.
816 * We must be careful about boundary cases so that we never
817 * let the user have CTX 0 (nucleus) or we ever use a CTX
818 * version of zero (and thus NO_CONTEXT would not be caught
819 * by version mis-match tests in mmu_context.h).
821 * Always invoked with interrupts disabled.
823 void get_new_mmu_context(struct mm_struct *mm)
825 unsigned long ctx, new_ctx;
826 unsigned long orig_pgsz_bits;
828 spin_lock(&ctx_alloc_lock);
830 /* wrap might have happened, test again if our context became valid */
831 if (unlikely(CTX_VALID(mm->context)))
833 orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
834 ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
835 new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
836 if (new_ctx >= (1 << CTX_NR_BITS)) {
837 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
838 if (new_ctx >= ctx) {
843 if (mm->context.sparc64_ctx_val)
844 cpumask_clear(mm_cpumask(mm));
845 mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
846 new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
847 tlb_context_cache = new_ctx;
848 mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
850 spin_unlock(&ctx_alloc_lock);
853 static int numa_enabled = 1;
854 static int numa_debug;
856 static int __init early_numa(char *p)
861 if (strstr(p, "off"))
864 if (strstr(p, "debug"))
869 early_param("numa", early_numa);
871 #define numadbg(f, a...) \
872 do { if (numa_debug) \
873 printk(KERN_INFO f, ## a); \
876 static void __init find_ramdisk(unsigned long phys_base)
878 #ifdef CONFIG_BLK_DEV_INITRD
879 if (sparc_ramdisk_image || sparc_ramdisk_image64) {
880 unsigned long ramdisk_image;
882 /* Older versions of the bootloader only supported a
883 * 32-bit physical address for the ramdisk image
884 * location, stored at sparc_ramdisk_image. Newer
885 * SILO versions set sparc_ramdisk_image to zero and
886 * provide a full 64-bit physical address at
887 * sparc_ramdisk_image64.
889 ramdisk_image = sparc_ramdisk_image;
891 ramdisk_image = sparc_ramdisk_image64;
893 /* Another bootloader quirk. The bootloader normalizes
894 * the physical address to KERNBASE, so we have to
895 * factor that back out and add in the lowest valid
896 * physical page address to get the true physical address.
898 ramdisk_image -= KERNBASE;
899 ramdisk_image += phys_base;
901 numadbg("Found ramdisk at physical address 0x%lx, size %u\n",
902 ramdisk_image, sparc_ramdisk_size);
904 initrd_start = ramdisk_image;
905 initrd_end = ramdisk_image + sparc_ramdisk_size;
907 memblock_reserve(initrd_start, sparc_ramdisk_size);
909 initrd_start += PAGE_OFFSET;
910 initrd_end += PAGE_OFFSET;
915 struct node_mem_mask {
919 static struct node_mem_mask node_masks[MAX_NUMNODES];
920 static int num_node_masks;
924 struct mdesc_mlgroup {
931 static struct mdesc_mlgroup *mlgroups;
932 static int num_mlgroups;
934 int numa_cpu_lookup_table[NR_CPUS];
935 cpumask_t numa_cpumask_lookup_table[MAX_NUMNODES];
937 struct mdesc_mblock {
940 u64 offset; /* RA-to-PA */
942 static struct mdesc_mblock *mblocks;
943 static int num_mblocks;
945 static struct mdesc_mblock * __init addr_to_mblock(unsigned long addr)
947 struct mdesc_mblock *m = NULL;
950 for (i = 0; i < num_mblocks; i++) {
953 if (addr >= m->base &&
954 addr < (m->base + m->size)) {
962 static u64 __init memblock_nid_range_sun4u(u64 start, u64 end, int *nid)
964 int prev_nid, new_nid;
966 prev_nid = NUMA_NO_NODE;
967 for ( ; start < end; start += PAGE_SIZE) {
968 for (new_nid = 0; new_nid < num_node_masks; new_nid++) {
969 struct node_mem_mask *p = &node_masks[new_nid];
971 if ((start & p->mask) == p->match) {
972 if (prev_nid == NUMA_NO_NODE)
978 if (new_nid == num_node_masks) {
980 WARN_ONCE(1, "addr[%Lx] doesn't match a NUMA node rule. Some memory will be owned by node 0.",
985 if (prev_nid != new_nid)
990 return start > end ? end : start;
993 static u64 __init memblock_nid_range(u64 start, u64 end, int *nid)
995 u64 ret_end, pa_start, m_mask, m_match, m_end;
996 struct mdesc_mblock *mblock;
999 if (tlb_type != hypervisor)
1000 return memblock_nid_range_sun4u(start, end, nid);
1002 mblock = addr_to_mblock(start);
1004 WARN_ONCE(1, "memblock_nid_range: Can't find mblock addr[%Lx]",
1012 pa_start = start + mblock->offset;
1016 for (_nid = 0; _nid < num_node_masks; _nid++) {
1017 struct node_mem_mask *const m = &node_masks[_nid];
1019 if ((pa_start & m->mask) == m->match) {
1026 if (num_node_masks == _nid) {
1027 /* We could not find NUMA group, so default to 0, but lets
1028 * search for latency group, so we could calculate the correct
1029 * end address that we return
1033 for (i = 0; i < num_mlgroups; i++) {
1034 struct mdesc_mlgroup *const m = &mlgroups[i];
1036 if ((pa_start & m->mask) == m->match) {
1043 if (i == num_mlgroups) {
1044 WARN_ONCE(1, "memblock_nid_range: Can't find latency group addr[%Lx]",
1053 * Each latency group has match and mask, and each memory block has an
1054 * offset. An address belongs to a latency group if its address matches
1055 * the following formula: ((addr + offset) & mask) == match
1056 * It is, however, slow to check every single page if it matches a
1057 * particular latency group. As optimization we calculate end value by
1058 * using bit arithmetics.
1060 m_end = m_match + (1ul << __ffs(m_mask)) - mblock->offset;
1061 m_end += pa_start & ~((1ul << fls64(m_mask)) - 1);
1062 ret_end = m_end > end ? end : m_end;
1070 /* This must be invoked after performing all of the necessary
1071 * memblock_set_node() calls for 'nid'. We need to be able to get
1072 * correct data from get_pfn_range_for_nid().
1074 static void __init allocate_node_data(int nid)
1076 struct pglist_data *p;
1077 unsigned long start_pfn, end_pfn;
1080 NODE_DATA(nid) = memblock_alloc_node(sizeof(struct pglist_data),
1081 SMP_CACHE_BYTES, nid);
1082 if (!NODE_DATA(nid)) {
1083 prom_printf("Cannot allocate pglist_data for nid[%d]\n", nid);
1087 NODE_DATA(nid)->node_id = nid;
1092 get_pfn_range_for_nid(nid, &start_pfn, &end_pfn);
1093 p->node_start_pfn = start_pfn;
1094 p->node_spanned_pages = end_pfn - start_pfn;
1097 static void init_node_masks_nonnuma(void)
1103 numadbg("Initializing tables for non-numa.\n");
1105 node_masks[0].mask = 0;
1106 node_masks[0].match = 0;
1110 for (i = 0; i < NR_CPUS; i++)
1111 numa_cpu_lookup_table[i] = 0;
1113 cpumask_setall(&numa_cpumask_lookup_table[0]);
1118 struct pglist_data *node_data[MAX_NUMNODES];
1120 EXPORT_SYMBOL(numa_cpu_lookup_table);
1121 EXPORT_SYMBOL(numa_cpumask_lookup_table);
1122 EXPORT_SYMBOL(node_data);
1124 static int scan_pio_for_cfg_handle(struct mdesc_handle *md, u64 pio,
1129 mdesc_for_each_arc(arc, md, pio, MDESC_ARC_TYPE_FWD) {
1130 u64 target = mdesc_arc_target(md, arc);
1133 val = mdesc_get_property(md, target,
1134 "cfg-handle", NULL);
1135 if (val && *val == cfg_handle)
1141 static int scan_arcs_for_cfg_handle(struct mdesc_handle *md, u64 grp,
1144 u64 arc, candidate, best_latency = ~(u64)0;
1146 candidate = MDESC_NODE_NULL;
1147 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1148 u64 target = mdesc_arc_target(md, arc);
1149 const char *name = mdesc_node_name(md, target);
1152 if (strcmp(name, "pio-latency-group"))
1155 val = mdesc_get_property(md, target, "latency", NULL);
1159 if (*val < best_latency) {
1161 best_latency = *val;
1165 if (candidate == MDESC_NODE_NULL)
1168 return scan_pio_for_cfg_handle(md, candidate, cfg_handle);
1171 int of_node_to_nid(struct device_node *dp)
1173 const struct linux_prom64_registers *regs;
1174 struct mdesc_handle *md;
1179 /* This is the right thing to do on currently supported
1180 * SUN4U NUMA platforms as well, as the PCI controller does
1181 * not sit behind any particular memory controller.
1186 regs = of_get_property(dp, "reg", NULL);
1190 cfg_handle = (regs->phys_addr >> 32UL) & 0x0fffffff;
1196 mdesc_for_each_node_by_name(md, grp, "group") {
1197 if (!scan_arcs_for_cfg_handle(md, grp, cfg_handle)) {
1209 static void __init add_node_ranges(void)
1211 phys_addr_t start, end;
1212 unsigned long prev_max;
1216 prev_max = memblock.memory.max;
1218 for_each_mem_range(i, &start, &end) {
1219 while (start < end) {
1220 unsigned long this_end;
1223 this_end = memblock_nid_range(start, end, &nid);
1225 numadbg("Setting memblock NUMA node nid[%d] "
1226 "start[%llx] end[%lx]\n",
1227 nid, start, this_end);
1229 memblock_set_node(start, this_end - start,
1230 &memblock.memory, nid);
1231 if (memblock.memory.max != prev_max)
1232 goto memblock_resized;
1238 static int __init grab_mlgroups(struct mdesc_handle *md)
1240 unsigned long paddr;
1244 mdesc_for_each_node_by_name(md, node, "memory-latency-group")
1249 paddr = memblock_phys_alloc(count * sizeof(struct mdesc_mlgroup),
1254 mlgroups = __va(paddr);
1255 num_mlgroups = count;
1258 mdesc_for_each_node_by_name(md, node, "memory-latency-group") {
1259 struct mdesc_mlgroup *m = &mlgroups[count++];
1264 val = mdesc_get_property(md, node, "latency", NULL);
1266 val = mdesc_get_property(md, node, "address-match", NULL);
1268 val = mdesc_get_property(md, node, "address-mask", NULL);
1271 numadbg("MLGROUP[%d]: node[%llx] latency[%llx] "
1272 "match[%llx] mask[%llx]\n",
1273 count - 1, m->node, m->latency, m->match, m->mask);
1279 static int __init grab_mblocks(struct mdesc_handle *md)
1281 unsigned long paddr;
1285 mdesc_for_each_node_by_name(md, node, "mblock")
1290 paddr = memblock_phys_alloc(count * sizeof(struct mdesc_mblock),
1295 mblocks = __va(paddr);
1296 num_mblocks = count;
1299 mdesc_for_each_node_by_name(md, node, "mblock") {
1300 struct mdesc_mblock *m = &mblocks[count++];
1303 val = mdesc_get_property(md, node, "base", NULL);
1305 val = mdesc_get_property(md, node, "size", NULL);
1307 val = mdesc_get_property(md, node,
1308 "address-congruence-offset", NULL);
1310 /* The address-congruence-offset property is optional.
1311 * Explicity zero it be identifty this.
1318 numadbg("MBLOCK[%d]: base[%llx] size[%llx] offset[%llx]\n",
1319 count - 1, m->base, m->size, m->offset);
1325 static void __init numa_parse_mdesc_group_cpus(struct mdesc_handle *md,
1326 u64 grp, cpumask_t *mask)
1330 cpumask_clear(mask);
1332 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_BACK) {
1333 u64 target = mdesc_arc_target(md, arc);
1334 const char *name = mdesc_node_name(md, target);
1337 if (strcmp(name, "cpu"))
1339 id = mdesc_get_property(md, target, "id", NULL);
1340 if (*id < nr_cpu_ids)
1341 cpumask_set_cpu(*id, mask);
1345 static struct mdesc_mlgroup * __init find_mlgroup(u64 node)
1349 for (i = 0; i < num_mlgroups; i++) {
1350 struct mdesc_mlgroup *m = &mlgroups[i];
1351 if (m->node == node)
1357 int __node_distance(int from, int to)
1359 if ((from >= MAX_NUMNODES) || (to >= MAX_NUMNODES)) {
1360 pr_warn("Returning default NUMA distance value for %d->%d\n",
1362 return (from == to) ? LOCAL_DISTANCE : REMOTE_DISTANCE;
1364 return numa_latency[from][to];
1366 EXPORT_SYMBOL(__node_distance);
1368 static int __init find_best_numa_node_for_mlgroup(struct mdesc_mlgroup *grp)
1372 for (i = 0; i < MAX_NUMNODES; i++) {
1373 struct node_mem_mask *n = &node_masks[i];
1375 if ((grp->mask == n->mask) && (grp->match == n->match))
1381 static void __init find_numa_latencies_for_group(struct mdesc_handle *md,
1386 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1388 u64 target = mdesc_arc_target(md, arc);
1389 struct mdesc_mlgroup *m = find_mlgroup(target);
1393 tnode = find_best_numa_node_for_mlgroup(m);
1394 if (tnode == MAX_NUMNODES)
1396 numa_latency[index][tnode] = m->latency;
1400 static int __init numa_attach_mlgroup(struct mdesc_handle *md, u64 grp,
1403 struct mdesc_mlgroup *candidate = NULL;
1404 u64 arc, best_latency = ~(u64)0;
1405 struct node_mem_mask *n;
1407 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1408 u64 target = mdesc_arc_target(md, arc);
1409 struct mdesc_mlgroup *m = find_mlgroup(target);
1412 if (m->latency < best_latency) {
1414 best_latency = m->latency;
1420 if (num_node_masks != index) {
1421 printk(KERN_ERR "Inconsistent NUMA state, "
1422 "index[%d] != num_node_masks[%d]\n",
1423 index, num_node_masks);
1427 n = &node_masks[num_node_masks++];
1429 n->mask = candidate->mask;
1430 n->match = candidate->match;
1432 numadbg("NUMA NODE[%d]: mask[%lx] match[%lx] (latency[%llx])\n",
1433 index, n->mask, n->match, candidate->latency);
1438 static int __init numa_parse_mdesc_group(struct mdesc_handle *md, u64 grp,
1444 numa_parse_mdesc_group_cpus(md, grp, &mask);
1446 for_each_cpu(cpu, &mask)
1447 numa_cpu_lookup_table[cpu] = index;
1448 cpumask_copy(&numa_cpumask_lookup_table[index], &mask);
1451 printk(KERN_INFO "NUMA GROUP[%d]: cpus [ ", index);
1452 for_each_cpu(cpu, &mask)
1457 return numa_attach_mlgroup(md, grp, index);
1460 static int __init numa_parse_mdesc(void)
1462 struct mdesc_handle *md = mdesc_grab();
1463 int i, j, err, count;
1466 node = mdesc_node_by_name(md, MDESC_NODE_NULL, "latency-groups");
1467 if (node == MDESC_NODE_NULL) {
1472 err = grab_mblocks(md);
1476 err = grab_mlgroups(md);
1481 mdesc_for_each_node_by_name(md, node, "group") {
1482 err = numa_parse_mdesc_group(md, node, count);
1489 mdesc_for_each_node_by_name(md, node, "group") {
1490 find_numa_latencies_for_group(md, node, count);
1494 /* Normalize numa latency matrix according to ACPI SLIT spec. */
1495 for (i = 0; i < MAX_NUMNODES; i++) {
1496 u64 self_latency = numa_latency[i][i];
1498 for (j = 0; j < MAX_NUMNODES; j++) {
1499 numa_latency[i][j] =
1500 (numa_latency[i][j] * LOCAL_DISTANCE) /
1507 for (i = 0; i < num_node_masks; i++) {
1508 allocate_node_data(i);
1518 static int __init numa_parse_jbus(void)
1520 unsigned long cpu, index;
1522 /* NUMA node id is encoded in bits 36 and higher, and there is
1523 * a 1-to-1 mapping from CPU ID to NUMA node ID.
1526 for_each_present_cpu(cpu) {
1527 numa_cpu_lookup_table[cpu] = index;
1528 cpumask_copy(&numa_cpumask_lookup_table[index], cpumask_of(cpu));
1529 node_masks[index].mask = ~((1UL << 36UL) - 1UL);
1530 node_masks[index].match = cpu << 36UL;
1534 num_node_masks = index;
1538 for (index = 0; index < num_node_masks; index++) {
1539 allocate_node_data(index);
1540 node_set_online(index);
1546 static int __init numa_parse_sun4u(void)
1548 if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1551 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
1552 if ((ver >> 32UL) == __JALAPENO_ID ||
1553 (ver >> 32UL) == __SERRANO_ID)
1554 return numa_parse_jbus();
1559 static int __init bootmem_init_numa(void)
1564 numadbg("bootmem_init_numa()\n");
1566 /* Some sane defaults for numa latency values */
1567 for (i = 0; i < MAX_NUMNODES; i++) {
1568 for (j = 0; j < MAX_NUMNODES; j++)
1569 numa_latency[i][j] = (i == j) ?
1570 LOCAL_DISTANCE : REMOTE_DISTANCE;
1574 if (tlb_type == hypervisor)
1575 err = numa_parse_mdesc();
1577 err = numa_parse_sun4u();
1584 static int bootmem_init_numa(void)
1591 static void __init bootmem_init_nonnuma(void)
1593 unsigned long top_of_ram = memblock_end_of_DRAM();
1594 unsigned long total_ram = memblock_phys_mem_size();
1596 numadbg("bootmem_init_nonnuma()\n");
1598 printk(KERN_INFO "Top of RAM: 0x%lx, Total RAM: 0x%lx\n",
1599 top_of_ram, total_ram);
1600 printk(KERN_INFO "Memory hole size: %ldMB\n",
1601 (top_of_ram - total_ram) >> 20);
1603 init_node_masks_nonnuma();
1604 memblock_set_node(0, PHYS_ADDR_MAX, &memblock.memory, 0);
1605 allocate_node_data(0);
1609 static unsigned long __init bootmem_init(unsigned long phys_base)
1611 unsigned long end_pfn;
1613 end_pfn = memblock_end_of_DRAM() >> PAGE_SHIFT;
1614 max_pfn = max_low_pfn = end_pfn;
1615 min_low_pfn = (phys_base >> PAGE_SHIFT);
1617 if (bootmem_init_numa() < 0)
1618 bootmem_init_nonnuma();
1620 /* Dump memblock with node info. */
1621 memblock_dump_all();
1623 /* XXX cpu notifier XXX */
1630 static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
1631 static int pall_ents __initdata;
1633 static unsigned long max_phys_bits = 40;
1635 bool kern_addr_valid(unsigned long addr)
1643 if ((long)addr < 0L) {
1644 unsigned long pa = __pa(addr);
1646 if ((pa >> max_phys_bits) != 0UL)
1649 return pfn_valid(pa >> PAGE_SHIFT);
1652 if (addr >= (unsigned long) KERNBASE &&
1653 addr < (unsigned long)&_end)
1656 pgd = pgd_offset_k(addr);
1660 p4d = p4d_offset(pgd, addr);
1664 pud = pud_offset(p4d, addr);
1668 if (pud_large(*pud))
1669 return pfn_valid(pud_pfn(*pud));
1671 pmd = pmd_offset(pud, addr);
1675 if (pmd_large(*pmd))
1676 return pfn_valid(pmd_pfn(*pmd));
1678 pte = pte_offset_kernel(pmd, addr);
1682 return pfn_valid(pte_pfn(*pte));
1685 static unsigned long __ref kernel_map_hugepud(unsigned long vstart,
1689 const unsigned long mask16gb = (1UL << 34) - 1UL;
1690 u64 pte_val = vstart;
1692 /* Each PUD is 8GB */
1693 if ((vstart & mask16gb) ||
1694 (vend - vstart <= mask16gb)) {
1695 pte_val ^= kern_linear_pte_xor[2];
1696 pud_val(*pud) = pte_val | _PAGE_PUD_HUGE;
1698 return vstart + PUD_SIZE;
1701 pte_val ^= kern_linear_pte_xor[3];
1702 pte_val |= _PAGE_PUD_HUGE;
1704 vend = vstart + mask16gb + 1UL;
1705 while (vstart < vend) {
1706 pud_val(*pud) = pte_val;
1708 pte_val += PUD_SIZE;
1715 static bool kernel_can_map_hugepud(unsigned long vstart, unsigned long vend,
1718 if (guard && !(vstart & ~PUD_MASK) && (vend - vstart) >= PUD_SIZE)
1724 static unsigned long __ref kernel_map_hugepmd(unsigned long vstart,
1728 const unsigned long mask256mb = (1UL << 28) - 1UL;
1729 const unsigned long mask2gb = (1UL << 31) - 1UL;
1730 u64 pte_val = vstart;
1732 /* Each PMD is 8MB */
1733 if ((vstart & mask256mb) ||
1734 (vend - vstart <= mask256mb)) {
1735 pte_val ^= kern_linear_pte_xor[0];
1736 pmd_val(*pmd) = pte_val | _PAGE_PMD_HUGE;
1738 return vstart + PMD_SIZE;
1741 if ((vstart & mask2gb) ||
1742 (vend - vstart <= mask2gb)) {
1743 pte_val ^= kern_linear_pte_xor[1];
1744 pte_val |= _PAGE_PMD_HUGE;
1745 vend = vstart + mask256mb + 1UL;
1747 pte_val ^= kern_linear_pte_xor[2];
1748 pte_val |= _PAGE_PMD_HUGE;
1749 vend = vstart + mask2gb + 1UL;
1752 while (vstart < vend) {
1753 pmd_val(*pmd) = pte_val;
1755 pte_val += PMD_SIZE;
1763 static bool kernel_can_map_hugepmd(unsigned long vstart, unsigned long vend,
1766 if (guard && !(vstart & ~PMD_MASK) && (vend - vstart) >= PMD_SIZE)
1772 static unsigned long __ref kernel_map_range(unsigned long pstart,
1773 unsigned long pend, pgprot_t prot,
1776 unsigned long vstart = PAGE_OFFSET + pstart;
1777 unsigned long vend = PAGE_OFFSET + pend;
1778 unsigned long alloc_bytes = 0UL;
1780 if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
1781 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
1786 while (vstart < vend) {
1787 unsigned long this_end, paddr = __pa(vstart);
1788 pgd_t *pgd = pgd_offset_k(vstart);
1794 if (pgd_none(*pgd)) {
1797 new = memblock_alloc_from(PAGE_SIZE, PAGE_SIZE,
1801 alloc_bytes += PAGE_SIZE;
1802 pgd_populate(&init_mm, pgd, new);
1805 p4d = p4d_offset(pgd, vstart);
1806 if (p4d_none(*p4d)) {
1809 new = memblock_alloc_from(PAGE_SIZE, PAGE_SIZE,
1813 alloc_bytes += PAGE_SIZE;
1814 p4d_populate(&init_mm, p4d, new);
1817 pud = pud_offset(p4d, vstart);
1818 if (pud_none(*pud)) {
1821 if (kernel_can_map_hugepud(vstart, vend, use_huge)) {
1822 vstart = kernel_map_hugepud(vstart, vend, pud);
1825 new = memblock_alloc_from(PAGE_SIZE, PAGE_SIZE,
1829 alloc_bytes += PAGE_SIZE;
1830 pud_populate(&init_mm, pud, new);
1833 pmd = pmd_offset(pud, vstart);
1834 if (pmd_none(*pmd)) {
1837 if (kernel_can_map_hugepmd(vstart, vend, use_huge)) {
1838 vstart = kernel_map_hugepmd(vstart, vend, pmd);
1841 new = memblock_alloc_from(PAGE_SIZE, PAGE_SIZE,
1845 alloc_bytes += PAGE_SIZE;
1846 pmd_populate_kernel(&init_mm, pmd, new);
1849 pte = pte_offset_kernel(pmd, vstart);
1850 this_end = (vstart + PMD_SIZE) & PMD_MASK;
1851 if (this_end > vend)
1854 while (vstart < this_end) {
1855 pte_val(*pte) = (paddr | pgprot_val(prot));
1857 vstart += PAGE_SIZE;
1866 panic("%s: Failed to allocate %lu bytes align=%lx from=%lx\n",
1867 __func__, PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1871 static void __init flush_all_kernel_tsbs(void)
1875 for (i = 0; i < KERNEL_TSB_NENTRIES; i++) {
1876 struct tsb *ent = &swapper_tsb[i];
1878 ent->tag = (1UL << TSB_TAG_INVALID_BIT);
1880 #ifndef CONFIG_DEBUG_PAGEALLOC
1881 for (i = 0; i < KERNEL_TSB4M_NENTRIES; i++) {
1882 struct tsb *ent = &swapper_4m_tsb[i];
1884 ent->tag = (1UL << TSB_TAG_INVALID_BIT);
1889 extern unsigned int kvmap_linear_patch[1];
1891 static void __init kernel_physical_mapping_init(void)
1893 unsigned long i, mem_alloced = 0UL;
1894 bool use_huge = true;
1896 #ifdef CONFIG_DEBUG_PAGEALLOC
1899 for (i = 0; i < pall_ents; i++) {
1900 unsigned long phys_start, phys_end;
1902 phys_start = pall[i].phys_addr;
1903 phys_end = phys_start + pall[i].reg_size;
1905 mem_alloced += kernel_map_range(phys_start, phys_end,
1906 PAGE_KERNEL, use_huge);
1909 printk("Allocated %ld bytes for kernel page tables.\n",
1912 kvmap_linear_patch[0] = 0x01000000; /* nop */
1913 flushi(&kvmap_linear_patch[0]);
1915 flush_all_kernel_tsbs();
1920 #ifdef CONFIG_DEBUG_PAGEALLOC
1921 void __kernel_map_pages(struct page *page, int numpages, int enable)
1923 unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1924 unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1926 kernel_map_range(phys_start, phys_end,
1927 (enable ? PAGE_KERNEL : __pgprot(0)), false);
1929 flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1930 PAGE_OFFSET + phys_end);
1932 /* we should perform an IPI and flush all tlbs,
1933 * but that can deadlock->flush only current cpu.
1935 __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1936 PAGE_OFFSET + phys_end);
1940 unsigned long __init find_ecache_flush_span(unsigned long size)
1944 for (i = 0; i < pavail_ents; i++) {
1945 if (pavail[i].reg_size >= size)
1946 return pavail[i].phys_addr;
1952 unsigned long PAGE_OFFSET;
1953 EXPORT_SYMBOL(PAGE_OFFSET);
1955 unsigned long VMALLOC_END = 0x0000010000000000UL;
1956 EXPORT_SYMBOL(VMALLOC_END);
1958 unsigned long sparc64_va_hole_top = 0xfffff80000000000UL;
1959 unsigned long sparc64_va_hole_bottom = 0x0000080000000000UL;
1961 static void __init setup_page_offset(void)
1963 if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1964 /* Cheetah/Panther support a full 64-bit virtual
1965 * address, so we can use all that our page tables
1968 sparc64_va_hole_top = 0xfff0000000000000UL;
1969 sparc64_va_hole_bottom = 0x0010000000000000UL;
1972 } else if (tlb_type == hypervisor) {
1973 switch (sun4v_chip_type) {
1974 case SUN4V_CHIP_NIAGARA1:
1975 case SUN4V_CHIP_NIAGARA2:
1976 /* T1 and T2 support 48-bit virtual addresses. */
1977 sparc64_va_hole_top = 0xffff800000000000UL;
1978 sparc64_va_hole_bottom = 0x0000800000000000UL;
1982 case SUN4V_CHIP_NIAGARA3:
1983 /* T3 supports 48-bit virtual addresses. */
1984 sparc64_va_hole_top = 0xffff800000000000UL;
1985 sparc64_va_hole_bottom = 0x0000800000000000UL;
1989 case SUN4V_CHIP_NIAGARA4:
1990 case SUN4V_CHIP_NIAGARA5:
1991 case SUN4V_CHIP_SPARC64X:
1992 case SUN4V_CHIP_SPARC_M6:
1993 /* T4 and later support 52-bit virtual addresses. */
1994 sparc64_va_hole_top = 0xfff8000000000000UL;
1995 sparc64_va_hole_bottom = 0x0008000000000000UL;
1998 case SUN4V_CHIP_SPARC_M7:
1999 case SUN4V_CHIP_SPARC_SN:
2000 /* M7 and later support 52-bit virtual addresses. */
2001 sparc64_va_hole_top = 0xfff8000000000000UL;
2002 sparc64_va_hole_bottom = 0x0008000000000000UL;
2005 case SUN4V_CHIP_SPARC_M8:
2007 /* M8 and later support 54-bit virtual addresses.
2008 * However, restricting M8 and above VA bits to 53
2009 * as 4-level page table cannot support more than
2012 sparc64_va_hole_top = 0xfff0000000000000UL;
2013 sparc64_va_hole_bottom = 0x0010000000000000UL;
2019 if (max_phys_bits > MAX_PHYS_ADDRESS_BITS) {
2020 prom_printf("MAX_PHYS_ADDRESS_BITS is too small, need %lu\n",
2025 PAGE_OFFSET = sparc64_va_hole_top;
2026 VMALLOC_END = ((sparc64_va_hole_bottom >> 1) +
2027 (sparc64_va_hole_bottom >> 2));
2029 pr_info("MM: PAGE_OFFSET is 0x%016lx (max_phys_bits == %lu)\n",
2030 PAGE_OFFSET, max_phys_bits);
2031 pr_info("MM: VMALLOC [0x%016lx --> 0x%016lx]\n",
2032 VMALLOC_START, VMALLOC_END);
2033 pr_info("MM: VMEMMAP [0x%016lx --> 0x%016lx]\n",
2034 VMEMMAP_BASE, VMEMMAP_BASE << 1);
2037 static void __init tsb_phys_patch(void)
2039 struct tsb_ldquad_phys_patch_entry *pquad;
2040 struct tsb_phys_patch_entry *p;
2042 pquad = &__tsb_ldquad_phys_patch;
2043 while (pquad < &__tsb_ldquad_phys_patch_end) {
2044 unsigned long addr = pquad->addr;
2046 if (tlb_type == hypervisor)
2047 *(unsigned int *) addr = pquad->sun4v_insn;
2049 *(unsigned int *) addr = pquad->sun4u_insn;
2051 __asm__ __volatile__("flush %0"
2058 p = &__tsb_phys_patch;
2059 while (p < &__tsb_phys_patch_end) {
2060 unsigned long addr = p->addr;
2062 *(unsigned int *) addr = p->insn;
2064 __asm__ __volatile__("flush %0"
2072 /* Don't mark as init, we give this to the Hypervisor. */
2073 #ifndef CONFIG_DEBUG_PAGEALLOC
2074 #define NUM_KTSB_DESCR 2
2076 #define NUM_KTSB_DESCR 1
2078 static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR];
2080 /* The swapper TSBs are loaded with a base sequence of:
2082 * sethi %uhi(SYMBOL), REG1
2083 * sethi %hi(SYMBOL), REG2
2084 * or REG1, %ulo(SYMBOL), REG1
2085 * or REG2, %lo(SYMBOL), REG2
2086 * sllx REG1, 32, REG1
2087 * or REG1, REG2, REG1
2089 * When we use physical addressing for the TSB accesses, we patch the
2090 * first four instructions in the above sequence.
2093 static void patch_one_ktsb_phys(unsigned int *start, unsigned int *end, unsigned long pa)
2095 unsigned long high_bits, low_bits;
2097 high_bits = (pa >> 32) & 0xffffffff;
2098 low_bits = (pa >> 0) & 0xffffffff;
2100 while (start < end) {
2101 unsigned int *ia = (unsigned int *)(unsigned long)*start;
2103 ia[0] = (ia[0] & ~0x3fffff) | (high_bits >> 10);
2104 __asm__ __volatile__("flush %0" : : "r" (ia));
2106 ia[1] = (ia[1] & ~0x3fffff) | (low_bits >> 10);
2107 __asm__ __volatile__("flush %0" : : "r" (ia + 1));
2109 ia[2] = (ia[2] & ~0x1fff) | (high_bits & 0x3ff);
2110 __asm__ __volatile__("flush %0" : : "r" (ia + 2));
2112 ia[3] = (ia[3] & ~0x1fff) | (low_bits & 0x3ff);
2113 __asm__ __volatile__("flush %0" : : "r" (ia + 3));
2119 static void ktsb_phys_patch(void)
2121 extern unsigned int __swapper_tsb_phys_patch;
2122 extern unsigned int __swapper_tsb_phys_patch_end;
2123 unsigned long ktsb_pa;
2125 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
2126 patch_one_ktsb_phys(&__swapper_tsb_phys_patch,
2127 &__swapper_tsb_phys_patch_end, ktsb_pa);
2128 #ifndef CONFIG_DEBUG_PAGEALLOC
2130 extern unsigned int __swapper_4m_tsb_phys_patch;
2131 extern unsigned int __swapper_4m_tsb_phys_patch_end;
2132 ktsb_pa = (kern_base +
2133 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
2134 patch_one_ktsb_phys(&__swapper_4m_tsb_phys_patch,
2135 &__swapper_4m_tsb_phys_patch_end, ktsb_pa);
2140 static void __init sun4v_ktsb_init(void)
2142 unsigned long ktsb_pa;
2144 /* First KTSB for PAGE_SIZE mappings. */
2145 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
2147 switch (PAGE_SIZE) {
2150 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
2151 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
2155 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
2156 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
2160 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
2161 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
2164 case 4 * 1024 * 1024:
2165 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
2166 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
2170 ktsb_descr[0].assoc = 1;
2171 ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
2172 ktsb_descr[0].ctx_idx = 0;
2173 ktsb_descr[0].tsb_base = ktsb_pa;
2174 ktsb_descr[0].resv = 0;
2176 #ifndef CONFIG_DEBUG_PAGEALLOC
2177 /* Second KTSB for 4MB/256MB/2GB/16GB mappings. */
2178 ktsb_pa = (kern_base +
2179 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
2181 ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB;
2182 ktsb_descr[1].pgsz_mask = ((HV_PGSZ_MASK_4MB |
2183 HV_PGSZ_MASK_256MB |
2185 HV_PGSZ_MASK_16GB) &
2187 ktsb_descr[1].assoc = 1;
2188 ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES;
2189 ktsb_descr[1].ctx_idx = 0;
2190 ktsb_descr[1].tsb_base = ktsb_pa;
2191 ktsb_descr[1].resv = 0;
2195 void sun4v_ktsb_register(void)
2197 unsigned long pa, ret;
2199 pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);
2201 ret = sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR, pa);
2203 prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: "
2204 "errors with %lx\n", pa, ret);
2209 static void __init sun4u_linear_pte_xor_finalize(void)
2211 #ifndef CONFIG_DEBUG_PAGEALLOC
2212 /* This is where we would add Panther support for
2213 * 32MB and 256MB pages.
2218 static void __init sun4v_linear_pte_xor_finalize(void)
2220 unsigned long pagecv_flag;
2222 /* Bit 9 of TTE is no longer CV bit on M7 processor and it instead
2223 * enables MCD error. Do not set bit 9 on M7 processor.
2225 switch (sun4v_chip_type) {
2226 case SUN4V_CHIP_SPARC_M7:
2227 case SUN4V_CHIP_SPARC_M8:
2228 case SUN4V_CHIP_SPARC_SN:
2232 pagecv_flag = _PAGE_CV_4V;
2235 #ifndef CONFIG_DEBUG_PAGEALLOC
2236 if (cpu_pgsz_mask & HV_PGSZ_MASK_256MB) {
2237 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^
2239 kern_linear_pte_xor[1] |= (_PAGE_CP_4V | pagecv_flag |
2240 _PAGE_P_4V | _PAGE_W_4V);
2242 kern_linear_pte_xor[1] = kern_linear_pte_xor[0];
2245 if (cpu_pgsz_mask & HV_PGSZ_MASK_2GB) {
2246 kern_linear_pte_xor[2] = (_PAGE_VALID | _PAGE_SZ2GB_4V) ^
2248 kern_linear_pte_xor[2] |= (_PAGE_CP_4V | pagecv_flag |
2249 _PAGE_P_4V | _PAGE_W_4V);
2251 kern_linear_pte_xor[2] = kern_linear_pte_xor[1];
2254 if (cpu_pgsz_mask & HV_PGSZ_MASK_16GB) {
2255 kern_linear_pte_xor[3] = (_PAGE_VALID | _PAGE_SZ16GB_4V) ^
2257 kern_linear_pte_xor[3] |= (_PAGE_CP_4V | pagecv_flag |
2258 _PAGE_P_4V | _PAGE_W_4V);
2260 kern_linear_pte_xor[3] = kern_linear_pte_xor[2];
2265 /* paging_init() sets up the page tables */
2267 static unsigned long last_valid_pfn;
2269 static void sun4u_pgprot_init(void);
2270 static void sun4v_pgprot_init(void);
2272 #define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U)
2273 #define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V)
2274 #define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
2275 #define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
2276 #define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
2277 #define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
2279 /* We need to exclude reserved regions. This exclusion will include
2280 * vmlinux and initrd. To be more precise the initrd size could be used to
2281 * compute a new lower limit because it is freed later during initialization.
2283 static void __init reduce_memory(phys_addr_t limit_ram)
2285 limit_ram += memblock_reserved_size();
2286 memblock_enforce_memory_limit(limit_ram);
2289 void __init paging_init(void)
2291 unsigned long end_pfn, shift, phys_base;
2292 unsigned long real_end, i;
2294 setup_page_offset();
2296 /* These build time checkes make sure that the dcache_dirty_cpu()
2297 * folio->flags usage will work.
2299 * When a page gets marked as dcache-dirty, we store the
2300 * cpu number starting at bit 32 in the folio->flags. Also,
2301 * functions like clear_dcache_dirty_cpu use the cpu mask
2302 * in 13-bit signed-immediate instruction fields.
2306 * Page flags must not reach into upper 32 bits that are used
2307 * for the cpu number
2309 BUILD_BUG_ON(NR_PAGEFLAGS > 32);
2312 * The bit fields placed in the high range must not reach below
2313 * the 32 bit boundary. Otherwise we cannot place the cpu field
2314 * at the 32 bit boundary.
2316 BUILD_BUG_ON(SECTIONS_WIDTH + NODES_WIDTH + ZONES_WIDTH +
2317 ilog2(roundup_pow_of_two(NR_CPUS)) > 32);
2319 BUILD_BUG_ON(NR_CPUS > 4096);
2321 kern_base = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB;
2322 kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
2324 /* Invalidate both kernel TSBs. */
2325 memset(swapper_tsb, 0x40, sizeof(swapper_tsb));
2326 #ifndef CONFIG_DEBUG_PAGEALLOC
2327 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
2330 /* TTE.cv bit on sparc v9 occupies the same position as TTE.mcde
2331 * bit on M7 processor. This is a conflicting usage of the same
2332 * bit. Enabling TTE.cv on M7 would turn on Memory Corruption
2333 * Detection error on all pages and this will lead to problems
2334 * later. Kernel does not run with MCD enabled and hence rest
2335 * of the required steps to fully configure memory corruption
2336 * detection are not taken. We need to ensure TTE.mcde is not
2337 * set on M7 processor. Compute the value of cacheability
2338 * flag for use later taking this into consideration.
2340 switch (sun4v_chip_type) {
2341 case SUN4V_CHIP_SPARC_M7:
2342 case SUN4V_CHIP_SPARC_M8:
2343 case SUN4V_CHIP_SPARC_SN:
2344 page_cache4v_flag = _PAGE_CP_4V;
2347 page_cache4v_flag = _PAGE_CACHE_4V;
2351 if (tlb_type == hypervisor)
2352 sun4v_pgprot_init();
2354 sun4u_pgprot_init();
2356 if (tlb_type == cheetah_plus ||
2357 tlb_type == hypervisor) {
2362 if (tlb_type == hypervisor)
2363 sun4v_patch_tlb_handlers();
2365 /* Find available physical memory...
2367 * Read it twice in order to work around a bug in openfirmware.
2368 * The call to grab this table itself can cause openfirmware to
2369 * allocate memory, which in turn can take away some space from
2370 * the list of available memory. Reading it twice makes sure
2371 * we really do get the final value.
2373 read_obp_translations();
2374 read_obp_memory("reg", &pall[0], &pall_ents);
2375 read_obp_memory("available", &pavail[0], &pavail_ents);
2376 read_obp_memory("available", &pavail[0], &pavail_ents);
2378 phys_base = 0xffffffffffffffffUL;
2379 for (i = 0; i < pavail_ents; i++) {
2380 phys_base = min(phys_base, pavail[i].phys_addr);
2381 memblock_add(pavail[i].phys_addr, pavail[i].reg_size);
2384 memblock_reserve(kern_base, kern_size);
2386 find_ramdisk(phys_base);
2388 if (cmdline_memory_size)
2389 reduce_memory(cmdline_memory_size);
2391 memblock_allow_resize();
2392 memblock_dump_all();
2394 set_bit(0, mmu_context_bmap);
2396 shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
2398 real_end = (unsigned long)_end;
2399 num_kernel_image_mappings = DIV_ROUND_UP(real_end - KERNBASE, 1 << ILOG2_4MB);
2400 printk("Kernel: Using %d locked TLB entries for main kernel image.\n",
2401 num_kernel_image_mappings);
2403 /* Set kernel pgd to upper alias so physical page computations
2406 init_mm.pgd += ((shift) / (sizeof(pgd_t)));
2408 memset(swapper_pg_dir, 0, sizeof(swapper_pg_dir));
2410 inherit_prom_mappings();
2412 /* Ok, we can use our TLB miss and window trap handlers safely. */
2417 prom_build_devicetree();
2418 of_populate_present_mask();
2420 of_fill_in_cpu_data();
2423 if (tlb_type == hypervisor) {
2425 mdesc_populate_present_mask(cpu_all_mask);
2427 mdesc_fill_in_cpu_data(cpu_all_mask);
2429 mdesc_get_page_sizes(cpu_all_mask, &cpu_pgsz_mask);
2431 sun4v_linear_pte_xor_finalize();
2434 sun4v_ktsb_register();
2436 unsigned long impl, ver;
2438 cpu_pgsz_mask = (HV_PGSZ_MASK_8K | HV_PGSZ_MASK_64K |
2439 HV_PGSZ_MASK_512K | HV_PGSZ_MASK_4MB);
2441 __asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver));
2442 impl = ((ver >> 32) & 0xffff);
2443 if (impl == PANTHER_IMPL)
2444 cpu_pgsz_mask |= (HV_PGSZ_MASK_32MB |
2445 HV_PGSZ_MASK_256MB);
2447 sun4u_linear_pte_xor_finalize();
2450 /* Flush the TLBs and the 4M TSB so that the updated linear
2451 * pte XOR settings are realized for all mappings.
2454 #ifndef CONFIG_DEBUG_PAGEALLOC
2455 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
2459 /* Setup bootmem... */
2460 last_valid_pfn = end_pfn = bootmem_init(phys_base);
2462 kernel_physical_mapping_init();
2465 unsigned long max_zone_pfns[MAX_NR_ZONES];
2467 memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
2469 max_zone_pfns[ZONE_NORMAL] = end_pfn;
2471 free_area_init(max_zone_pfns);
2474 printk("Booting Linux...\n");
2477 int page_in_phys_avail(unsigned long paddr)
2483 for (i = 0; i < pavail_ents; i++) {
2484 unsigned long start, end;
2486 start = pavail[i].phys_addr;
2487 end = start + pavail[i].reg_size;
2489 if (paddr >= start && paddr < end)
2492 if (paddr >= kern_base && paddr < (kern_base + kern_size))
2494 #ifdef CONFIG_BLK_DEV_INITRD
2495 if (paddr >= __pa(initrd_start) &&
2496 paddr < __pa(PAGE_ALIGN(initrd_end)))
2503 static void __init register_page_bootmem_info(void)
2508 for_each_online_node(i)
2509 if (NODE_DATA(i)->node_spanned_pages)
2510 register_page_bootmem_info_node(NODE_DATA(i));
2513 void __init mem_init(void)
2515 high_memory = __va(last_valid_pfn << PAGE_SHIFT);
2517 memblock_free_all();
2520 * Must be done after boot memory is put on freelist, because here we
2521 * might set fields in deferred struct pages that have not yet been
2522 * initialized, and memblock_free_all() initializes all the reserved
2523 * deferred pages for us.
2525 register_page_bootmem_info();
2528 * Set up the zero page, mark it reserved, so that page count
2529 * is not manipulated when freeing the page from user ptes.
2531 mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
2532 if (mem_map_zero == NULL) {
2533 prom_printf("paging_init: Cannot alloc zero page.\n");
2536 mark_page_reserved(mem_map_zero);
2539 if (tlb_type == cheetah || tlb_type == cheetah_plus)
2540 cheetah_ecache_flush_init();
2543 void free_initmem(void)
2545 unsigned long addr, initend;
2548 /* If the physical memory maps were trimmed by kernel command
2549 * line options, don't even try freeing this initmem stuff up.
2550 * The kernel image could have been in the trimmed out region
2551 * and if so the freeing below will free invalid page structs.
2553 if (cmdline_memory_size)
2557 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
2559 addr = PAGE_ALIGN((unsigned long)(__init_begin));
2560 initend = (unsigned long)(__init_end) & PAGE_MASK;
2561 for (; addr < initend; addr += PAGE_SIZE) {
2565 ((unsigned long) __va(kern_base)) -
2566 ((unsigned long) KERNBASE));
2567 memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
2570 free_reserved_page(virt_to_page(page));
2574 pgprot_t PAGE_KERNEL __read_mostly;
2575 EXPORT_SYMBOL(PAGE_KERNEL);
2577 pgprot_t PAGE_KERNEL_LOCKED __read_mostly;
2578 pgprot_t PAGE_COPY __read_mostly;
2580 pgprot_t PAGE_SHARED __read_mostly;
2581 EXPORT_SYMBOL(PAGE_SHARED);
2583 unsigned long pg_iobits __read_mostly;
2585 unsigned long _PAGE_IE __read_mostly;
2586 EXPORT_SYMBOL(_PAGE_IE);
2588 unsigned long _PAGE_E __read_mostly;
2589 EXPORT_SYMBOL(_PAGE_E);
2591 unsigned long _PAGE_CACHE __read_mostly;
2592 EXPORT_SYMBOL(_PAGE_CACHE);
2594 #ifdef CONFIG_SPARSEMEM_VMEMMAP
2595 int __meminit vmemmap_populate(unsigned long vstart, unsigned long vend,
2596 int node, struct vmem_altmap *altmap)
2598 unsigned long pte_base;
2600 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2601 _PAGE_CP_4U | _PAGE_CV_4U |
2602 _PAGE_P_4U | _PAGE_W_4U);
2603 if (tlb_type == hypervisor)
2604 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2605 page_cache4v_flag | _PAGE_P_4V | _PAGE_W_4V);
2607 pte_base |= _PAGE_PMD_HUGE;
2609 vstart = vstart & PMD_MASK;
2610 vend = ALIGN(vend, PMD_SIZE);
2611 for (; vstart < vend; vstart += PMD_SIZE) {
2612 pgd_t *pgd = vmemmap_pgd_populate(vstart, node);
2621 p4d = vmemmap_p4d_populate(pgd, vstart, node);
2625 pud = vmemmap_pud_populate(p4d, vstart, node);
2629 pmd = pmd_offset(pud, vstart);
2630 pte = pmd_val(*pmd);
2631 if (!(pte & _PAGE_VALID)) {
2632 void *block = vmemmap_alloc_block(PMD_SIZE, node);
2637 pmd_val(*pmd) = pte_base | __pa(block);
2644 void vmemmap_free(unsigned long start, unsigned long end,
2645 struct vmem_altmap *altmap)
2648 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
2650 /* These are actually filled in at boot time by sun4{u,v}_pgprot_init() */
2651 static pgprot_t protection_map[16] __ro_after_init;
2653 static void prot_init_common(unsigned long page_none,
2654 unsigned long page_shared,
2655 unsigned long page_copy,
2656 unsigned long page_readonly,
2657 unsigned long page_exec_bit)
2659 PAGE_COPY = __pgprot(page_copy);
2660 PAGE_SHARED = __pgprot(page_shared);
2662 protection_map[0x0] = __pgprot(page_none);
2663 protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit);
2664 protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit);
2665 protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit);
2666 protection_map[0x4] = __pgprot(page_readonly);
2667 protection_map[0x5] = __pgprot(page_readonly);
2668 protection_map[0x6] = __pgprot(page_copy);
2669 protection_map[0x7] = __pgprot(page_copy);
2670 protection_map[0x8] = __pgprot(page_none);
2671 protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit);
2672 protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit);
2673 protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit);
2674 protection_map[0xc] = __pgprot(page_readonly);
2675 protection_map[0xd] = __pgprot(page_readonly);
2676 protection_map[0xe] = __pgprot(page_shared);
2677 protection_map[0xf] = __pgprot(page_shared);
2680 static void __init sun4u_pgprot_init(void)
2682 unsigned long page_none, page_shared, page_copy, page_readonly;
2683 unsigned long page_exec_bit;
2686 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2687 _PAGE_CACHE_4U | _PAGE_P_4U |
2688 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2690 PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2691 _PAGE_CACHE_4U | _PAGE_P_4U |
2692 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2693 _PAGE_EXEC_4U | _PAGE_L_4U);
2695 _PAGE_IE = _PAGE_IE_4U;
2696 _PAGE_E = _PAGE_E_4U;
2697 _PAGE_CACHE = _PAGE_CACHE_4U;
2699 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U |
2700 __ACCESS_BITS_4U | _PAGE_E_4U);
2702 #ifdef CONFIG_DEBUG_PAGEALLOC
2703 kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET;
2705 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
2708 kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U |
2709 _PAGE_P_4U | _PAGE_W_4U);
2711 for (i = 1; i < 4; i++)
2712 kern_linear_pte_xor[i] = kern_linear_pte_xor[0];
2714 _PAGE_ALL_SZ_BITS = (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
2715 _PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
2716 _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);
2719 page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U;
2720 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2721 __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U);
2722 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2723 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2724 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2725 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2727 page_exec_bit = _PAGE_EXEC_4U;
2729 prot_init_common(page_none, page_shared, page_copy, page_readonly,
2733 static void __init sun4v_pgprot_init(void)
2735 unsigned long page_none, page_shared, page_copy, page_readonly;
2736 unsigned long page_exec_bit;
2739 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
2740 page_cache4v_flag | _PAGE_P_4V |
2741 __ACCESS_BITS_4V | __DIRTY_BITS_4V |
2743 PAGE_KERNEL_LOCKED = PAGE_KERNEL;
2745 _PAGE_IE = _PAGE_IE_4V;
2746 _PAGE_E = _PAGE_E_4V;
2747 _PAGE_CACHE = page_cache4v_flag;
2749 #ifdef CONFIG_DEBUG_PAGEALLOC
2750 kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET;
2752 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
2755 kern_linear_pte_xor[0] |= (page_cache4v_flag | _PAGE_P_4V |
2758 for (i = 1; i < 4; i++)
2759 kern_linear_pte_xor[i] = kern_linear_pte_xor[0];
2761 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
2762 __ACCESS_BITS_4V | _PAGE_E_4V);
2764 _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
2765 _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
2766 _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
2767 _PAGE_SZ64K_4V | _PAGE_SZ8K_4V);
2769 page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | page_cache4v_flag;
2770 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag |
2771 __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V);
2772 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag |
2773 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2774 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag |
2775 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2777 page_exec_bit = _PAGE_EXEC_4V;
2779 prot_init_common(page_none, page_shared, page_copy, page_readonly,
2783 unsigned long pte_sz_bits(unsigned long sz)
2785 if (tlb_type == hypervisor) {
2789 return _PAGE_SZ8K_4V;
2791 return _PAGE_SZ64K_4V;
2793 return _PAGE_SZ512K_4V;
2794 case 4 * 1024 * 1024:
2795 return _PAGE_SZ4MB_4V;
2801 return _PAGE_SZ8K_4U;
2803 return _PAGE_SZ64K_4U;
2805 return _PAGE_SZ512K_4U;
2806 case 4 * 1024 * 1024:
2807 return _PAGE_SZ4MB_4U;
2812 pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size)
2816 pte_val(pte) = page | pgprot_val(pgprot_noncached(prot));
2817 pte_val(pte) |= (((unsigned long)space) << 32);
2818 pte_val(pte) |= pte_sz_bits(page_size);
2823 static unsigned long kern_large_tte(unsigned long paddr)
2827 val = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2828 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U |
2829 _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U);
2830 if (tlb_type == hypervisor)
2831 val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2832 page_cache4v_flag | _PAGE_P_4V |
2833 _PAGE_EXEC_4V | _PAGE_W_4V);
2838 /* If not locked, zap it. */
2839 void __flush_tlb_all(void)
2841 unsigned long pstate;
2844 __asm__ __volatile__("flushw\n\t"
2845 "rdpr %%pstate, %0\n\t"
2846 "wrpr %0, %1, %%pstate"
2849 if (tlb_type == hypervisor) {
2850 sun4v_mmu_demap_all();
2851 } else if (tlb_type == spitfire) {
2852 for (i = 0; i < 64; i++) {
2853 /* Spitfire Errata #32 workaround */
2854 /* NOTE: Always runs on spitfire, so no
2855 * cheetah+ page size encodings.
2857 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
2861 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2863 if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) {
2864 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2867 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
2868 spitfire_put_dtlb_data(i, 0x0UL);
2871 /* Spitfire Errata #32 workaround */
2872 /* NOTE: Always runs on spitfire, so no
2873 * cheetah+ page size encodings.
2875 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
2879 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2881 if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) {
2882 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2885 : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
2886 spitfire_put_itlb_data(i, 0x0UL);
2889 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
2890 cheetah_flush_dtlb_all();
2891 cheetah_flush_itlb_all();
2893 __asm__ __volatile__("wrpr %0, 0, %%pstate"
2897 pte_t *pte_alloc_one_kernel(struct mm_struct *mm)
2899 struct page *page = alloc_page(GFP_KERNEL | __GFP_ZERO);
2903 pte = (pte_t *) page_address(page);
2908 pgtable_t pte_alloc_one(struct mm_struct *mm)
2910 struct ptdesc *ptdesc = pagetable_alloc(GFP_KERNEL | __GFP_ZERO, 0);
2914 if (!pagetable_pte_ctor(ptdesc)) {
2915 pagetable_free(ptdesc);
2918 return ptdesc_address(ptdesc);
2921 void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
2923 free_page((unsigned long)pte);
2926 static void __pte_free(pgtable_t pte)
2928 struct ptdesc *ptdesc = virt_to_ptdesc(pte);
2930 pagetable_pte_dtor(ptdesc);
2931 pagetable_free(ptdesc);
2934 void pte_free(struct mm_struct *mm, pgtable_t pte)
2939 void pgtable_free(void *table, bool is_page)
2944 kmem_cache_free(pgtable_cache, table);
2947 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
2948 static void pte_free_now(struct rcu_head *head)
2952 page = container_of(head, struct page, rcu_head);
2953 __pte_free((pgtable_t)page_address(page));
2956 void pte_free_defer(struct mm_struct *mm, pgtable_t pgtable)
2960 page = virt_to_page(pgtable);
2961 call_rcu(&page->rcu_head, pte_free_now);
2964 void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr,
2967 unsigned long pte, flags;
2968 struct mm_struct *mm;
2971 if (!pmd_large(entry) || !pmd_young(entry))
2974 pte = pmd_val(entry);
2976 /* Don't insert a non-valid PMD into the TSB, we'll deadlock. */
2977 if (!(pte & _PAGE_VALID))
2980 /* We are fabricating 8MB pages using 4MB real hw pages. */
2981 pte |= (addr & (1UL << REAL_HPAGE_SHIFT));
2985 spin_lock_irqsave(&mm->context.lock, flags);
2987 if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL)
2988 __update_mmu_tsb_insert(mm, MM_TSB_HUGE, REAL_HPAGE_SHIFT,
2991 spin_unlock_irqrestore(&mm->context.lock, flags);
2993 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
2995 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
2996 static void context_reload(void *__data)
2998 struct mm_struct *mm = __data;
3000 if (mm == current->mm)
3001 load_secondary_context(mm);
3004 void hugetlb_setup(struct pt_regs *regs)
3006 struct mm_struct *mm = current->mm;
3007 struct tsb_config *tp;
3009 if (faulthandler_disabled() || !mm) {
3010 const struct exception_table_entry *entry;
3012 entry = search_exception_tables(regs->tpc);
3014 regs->tpc = entry->fixup;
3015 regs->tnpc = regs->tpc + 4;
3018 pr_alert("Unexpected HugeTLB setup in atomic context.\n");
3019 die_if_kernel("HugeTSB in atomic", regs);
3022 tp = &mm->context.tsb_block[MM_TSB_HUGE];
3023 if (likely(tp->tsb == NULL))
3024 tsb_grow(mm, MM_TSB_HUGE, 0);
3026 tsb_context_switch(mm);
3029 /* On UltraSPARC-III+ and later, configure the second half of
3030 * the Data-TLB for huge pages.
3032 if (tlb_type == cheetah_plus) {
3033 bool need_context_reload = false;
3036 spin_lock_irq(&ctx_alloc_lock);
3037 ctx = mm->context.sparc64_ctx_val;
3038 ctx &= ~CTX_PGSZ_MASK;
3039 ctx |= CTX_PGSZ_BASE << CTX_PGSZ0_SHIFT;
3040 ctx |= CTX_PGSZ_HUGE << CTX_PGSZ1_SHIFT;
3042 if (ctx != mm->context.sparc64_ctx_val) {
3043 /* When changing the page size fields, we
3044 * must perform a context flush so that no
3045 * stale entries match. This flush must
3046 * occur with the original context register
3049 do_flush_tlb_mm(mm);
3051 /* Reload the context register of all processors
3052 * also executing in this address space.
3054 mm->context.sparc64_ctx_val = ctx;
3055 need_context_reload = true;
3057 spin_unlock_irq(&ctx_alloc_lock);
3059 if (need_context_reload)
3060 on_each_cpu(context_reload, mm, 0);
3065 static struct resource code_resource = {
3066 .name = "Kernel code",
3067 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM
3070 static struct resource data_resource = {
3071 .name = "Kernel data",
3072 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM
3075 static struct resource bss_resource = {
3076 .name = "Kernel bss",
3077 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM
3080 static inline resource_size_t compute_kern_paddr(void *addr)
3082 return (resource_size_t) (addr - KERNBASE + kern_base);
3085 static void __init kernel_lds_init(void)
3087 code_resource.start = compute_kern_paddr(_text);
3088 code_resource.end = compute_kern_paddr(_etext - 1);
3089 data_resource.start = compute_kern_paddr(_etext);
3090 data_resource.end = compute_kern_paddr(_edata - 1);
3091 bss_resource.start = compute_kern_paddr(__bss_start);
3092 bss_resource.end = compute_kern_paddr(_end - 1);
3095 static int __init report_memory(void)
3098 struct resource *res;
3102 for (i = 0; i < pavail_ents; i++) {
3103 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
3106 pr_warn("Failed to allocate source.\n");
3110 res->name = "System RAM";
3111 res->start = pavail[i].phys_addr;
3112 res->end = pavail[i].phys_addr + pavail[i].reg_size - 1;
3113 res->flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM;
3115 if (insert_resource(&iomem_resource, res) < 0) {
3116 pr_warn("Resource insertion failed.\n");
3120 insert_resource(res, &code_resource);
3121 insert_resource(res, &data_resource);
3122 insert_resource(res, &bss_resource);
3127 arch_initcall(report_memory);
3130 #define do_flush_tlb_kernel_range smp_flush_tlb_kernel_range
3132 #define do_flush_tlb_kernel_range __flush_tlb_kernel_range
3135 void flush_tlb_kernel_range(unsigned long start, unsigned long end)
3137 if (start < HI_OBP_ADDRESS && end > LOW_OBP_ADDRESS) {
3138 if (start < LOW_OBP_ADDRESS) {
3139 flush_tsb_kernel_range(start, LOW_OBP_ADDRESS);
3140 do_flush_tlb_kernel_range(start, LOW_OBP_ADDRESS);
3142 if (end > HI_OBP_ADDRESS) {
3143 flush_tsb_kernel_range(HI_OBP_ADDRESS, end);
3144 do_flush_tlb_kernel_range(HI_OBP_ADDRESS, end);
3147 flush_tsb_kernel_range(start, end);
3148 do_flush_tlb_kernel_range(start, end);
3152 void copy_user_highpage(struct page *to, struct page *from,
3153 unsigned long vaddr, struct vm_area_struct *vma)
3157 vfrom = kmap_atomic(from);
3158 vto = kmap_atomic(to);
3159 copy_user_page(vto, vfrom, vaddr, to);
3161 kunmap_atomic(vfrom);
3163 /* If this page has ADI enabled, copy over any ADI tags
3166 if (vma->vm_flags & VM_SPARC_ADI) {
3167 unsigned long pfrom, pto, i, adi_tag;
3169 pfrom = page_to_phys(from);
3170 pto = page_to_phys(to);
3172 for (i = pfrom; i < (pfrom + PAGE_SIZE); i += adi_blksize()) {
3173 asm volatile("ldxa [%1] %2, %0\n\t"
3175 : "r" (i), "i" (ASI_MCD_REAL));
3176 asm volatile("stxa %0, [%1] %2\n\t"
3178 : "r" (adi_tag), "r" (pto),
3179 "i" (ASI_MCD_REAL));
3180 pto += adi_blksize();
3182 asm volatile("membar #Sync\n\t");
3185 EXPORT_SYMBOL(copy_user_highpage);
3187 void copy_highpage(struct page *to, struct page *from)
3191 vfrom = kmap_atomic(from);
3192 vto = kmap_atomic(to);
3193 copy_page(vto, vfrom);
3195 kunmap_atomic(vfrom);
3197 /* If this platform is ADI enabled, copy any ADI tags
3200 if (adi_capable()) {
3201 unsigned long pfrom, pto, i, adi_tag;
3203 pfrom = page_to_phys(from);
3204 pto = page_to_phys(to);
3206 for (i = pfrom; i < (pfrom + PAGE_SIZE); i += adi_blksize()) {
3207 asm volatile("ldxa [%1] %2, %0\n\t"
3209 : "r" (i), "i" (ASI_MCD_REAL));
3210 asm volatile("stxa %0, [%1] %2\n\t"
3212 : "r" (adi_tag), "r" (pto),
3213 "i" (ASI_MCD_REAL));
3214 pto += adi_blksize();
3216 asm volatile("membar #Sync\n\t");
3219 EXPORT_SYMBOL(copy_highpage);
3221 pgprot_t vm_get_page_prot(unsigned long vm_flags)
3223 unsigned long prot = pgprot_val(protection_map[vm_flags &
3224 (VM_READ|VM_WRITE|VM_EXEC|VM_SHARED)]);
3226 if (vm_flags & VM_SPARC_ADI)
3227 prot |= _PAGE_MCD_4V;
3229 return __pgprot(prot);
3231 EXPORT_SYMBOL(vm_get_page_prot);