1 // SPDX-License-Identifier: GPL-2.0
3 * arch/sparc64/mm/init.c
5 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
6 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
9 #include <linux/extable.h>
10 #include <linux/kernel.h>
11 #include <linux/sched.h>
12 #include <linux/string.h>
13 #include <linux/init.h>
14 #include <linux/memblock.h>
16 #include <linux/hugetlb.h>
17 #include <linux/initrd.h>
18 #include <linux/swap.h>
19 #include <linux/pagemap.h>
20 #include <linux/poison.h>
22 #include <linux/seq_file.h>
23 #include <linux/kprobes.h>
24 #include <linux/cache.h>
25 #include <linux/sort.h>
26 #include <linux/ioport.h>
27 #include <linux/percpu.h>
28 #include <linux/mmzone.h>
29 #include <linux/gfp.h>
30 #include <linux/bootmem_info.h>
34 #include <asm/pgalloc.h>
35 #include <asm/oplib.h>
36 #include <asm/iommu.h>
38 #include <linux/uaccess.h>
39 #include <asm/mmu_context.h>
40 #include <asm/tlbflush.h>
42 #include <asm/starfire.h>
44 #include <asm/spitfire.h>
45 #include <asm/sections.h>
47 #include <asm/hypervisor.h>
49 #include <asm/mdesc.h>
50 #include <asm/cpudata.h>
51 #include <asm/setup.h>
56 unsigned long kern_linear_pte_xor[4] __read_mostly;
57 static unsigned long page_cache4v_flag;
59 /* A bitmap, two bits for every 256MB of physical memory. These two
60 * bits determine what page size we use for kernel linear
61 * translations. They form an index into kern_linear_pte_xor[]. The
62 * value in the indexed slot is XOR'd with the TLB miss virtual
63 * address to form the resulting TTE. The mapping is:
70 * All sun4v chips support 256MB pages. Only SPARC-T4 and later
71 * support 2GB pages, and hopefully future cpus will support the 16GB
72 * pages as well. For slots 2 and 3, we encode a 256MB TTE xor there
73 * if these larger page sizes are not supported by the cpu.
75 * It would be nice to determine this from the machine description
76 * 'cpu' properties, but we need to have this table setup before the
77 * MDESC is initialized.
80 #ifndef CONFIG_DEBUG_PAGEALLOC
81 /* A special kernel TSB for 4MB, 256MB, 2GB and 16GB linear mappings.
82 * Space is allocated for this right after the trap table in
83 * arch/sparc64/kernel/head.S
85 extern struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES];
87 extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
89 static unsigned long cpu_pgsz_mask;
91 #define MAX_BANKS 1024
93 static struct linux_prom64_registers pavail[MAX_BANKS];
94 static int pavail_ents;
96 u64 numa_latency[MAX_NUMNODES][MAX_NUMNODES];
98 static int cmp_p64(const void *a, const void *b)
100 const struct linux_prom64_registers *x = a, *y = b;
102 if (x->phys_addr > y->phys_addr)
104 if (x->phys_addr < y->phys_addr)
109 static void __init read_obp_memory(const char *property,
110 struct linux_prom64_registers *regs,
113 phandle node = prom_finddevice("/memory");
114 int prop_size = prom_getproplen(node, property);
117 ents = prop_size / sizeof(struct linux_prom64_registers);
118 if (ents > MAX_BANKS) {
119 prom_printf("The machine has more %s property entries than "
120 "this kernel can support (%d).\n",
121 property, MAX_BANKS);
125 ret = prom_getproperty(node, property, (char *) regs, prop_size);
127 prom_printf("Couldn't get %s property from /memory.\n",
132 /* Sanitize what we got from the firmware, by page aligning
135 for (i = 0; i < ents; i++) {
136 unsigned long base, size;
138 base = regs[i].phys_addr;
139 size = regs[i].reg_size;
142 if (base & ~PAGE_MASK) {
143 unsigned long new_base = PAGE_ALIGN(base);
145 size -= new_base - base;
146 if ((long) size < 0L)
151 /* If it is empty, simply get rid of it.
152 * This simplifies the logic of the other
153 * functions that process these arrays.
155 memmove(®s[i], ®s[i + 1],
156 (ents - i - 1) * sizeof(regs[0]));
161 regs[i].phys_addr = base;
162 regs[i].reg_size = size;
167 sort(regs, ents, sizeof(struct linux_prom64_registers),
171 /* Kernel physical address base and size in bytes. */
172 unsigned long kern_base __read_mostly;
173 unsigned long kern_size __read_mostly;
175 /* Initial ramdisk setup */
176 extern unsigned long sparc_ramdisk_image64;
177 extern unsigned int sparc_ramdisk_image;
178 extern unsigned int sparc_ramdisk_size;
180 struct page *mem_map_zero __read_mostly;
181 EXPORT_SYMBOL(mem_map_zero);
183 unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
185 unsigned long sparc64_kern_pri_context __read_mostly;
186 unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
187 unsigned long sparc64_kern_sec_context __read_mostly;
189 int num_kernel_image_mappings;
191 #ifdef CONFIG_DEBUG_DCFLUSH
192 atomic_t dcpage_flushes = ATOMIC_INIT(0);
194 atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
198 inline void flush_dcache_page_impl(struct page *page)
200 BUG_ON(tlb_type == hypervisor);
201 #ifdef CONFIG_DEBUG_DCFLUSH
202 atomic_inc(&dcpage_flushes);
205 #ifdef DCACHE_ALIASING_POSSIBLE
206 __flush_dcache_page(page_address(page),
207 ((tlb_type == spitfire) &&
208 page_mapping_file(page) != NULL));
210 if (page_mapping_file(page) != NULL &&
211 tlb_type == spitfire)
212 __flush_icache_page(__pa(page_address(page)));
216 #define PG_dcache_dirty PG_arch_1
217 #define PG_dcache_cpu_shift 32UL
218 #define PG_dcache_cpu_mask \
219 ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL)
221 #define dcache_dirty_cpu(page) \
222 (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
224 static inline void set_dcache_dirty(struct page *page, int this_cpu)
226 unsigned long mask = this_cpu;
227 unsigned long non_cpu_bits;
229 non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
230 mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
232 __asm__ __volatile__("1:\n\t"
234 "and %%g7, %1, %%g1\n\t"
235 "or %%g1, %0, %%g1\n\t"
236 "casx [%2], %%g7, %%g1\n\t"
238 "bne,pn %%xcc, 1b\n\t"
241 : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
245 static inline void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
247 unsigned long mask = (1UL << PG_dcache_dirty);
249 __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
252 "srlx %%g7, %4, %%g1\n\t"
253 "and %%g1, %3, %%g1\n\t"
255 "bne,pn %%icc, 2f\n\t"
256 " andn %%g7, %1, %%g1\n\t"
257 "casx [%2], %%g7, %%g1\n\t"
259 "bne,pn %%xcc, 1b\n\t"
263 : "r" (cpu), "r" (mask), "r" (&page->flags),
264 "i" (PG_dcache_cpu_mask),
265 "i" (PG_dcache_cpu_shift)
269 static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
271 unsigned long tsb_addr = (unsigned long) ent;
273 if (tlb_type == cheetah_plus || tlb_type == hypervisor)
274 tsb_addr = __pa(tsb_addr);
276 __tsb_insert(tsb_addr, tag, pte);
279 unsigned long _PAGE_ALL_SZ_BITS __read_mostly;
281 static void flush_dcache(unsigned long pfn)
285 page = pfn_to_page(pfn);
287 unsigned long pg_flags;
289 pg_flags = page->flags;
290 if (pg_flags & (1UL << PG_dcache_dirty)) {
291 int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
293 int this_cpu = get_cpu();
295 /* This is just to optimize away some function calls
299 flush_dcache_page_impl(page);
301 smp_flush_dcache_page_impl(page, cpu);
303 clear_dcache_dirty_cpu(page, cpu);
310 /* mm->context.lock must be held */
311 static void __update_mmu_tsb_insert(struct mm_struct *mm, unsigned long tsb_index,
312 unsigned long tsb_hash_shift, unsigned long address,
315 struct tsb *tsb = mm->context.tsb_block[tsb_index].tsb;
321 tsb += ((address >> tsb_hash_shift) &
322 (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL));
323 tag = (address >> 22UL);
324 tsb_insert(tsb, tag, tte);
327 #ifdef CONFIG_HUGETLB_PAGE
328 static int __init hugetlbpage_init(void)
330 hugetlb_add_hstate(HPAGE_64K_SHIFT - PAGE_SHIFT);
331 hugetlb_add_hstate(HPAGE_SHIFT - PAGE_SHIFT);
332 hugetlb_add_hstate(HPAGE_256MB_SHIFT - PAGE_SHIFT);
333 hugetlb_add_hstate(HPAGE_2GB_SHIFT - PAGE_SHIFT);
338 arch_initcall(hugetlbpage_init);
340 static void __init pud_huge_patch(void)
342 struct pud_huge_patch_entry *p;
345 p = &__pud_huge_patch;
347 *(unsigned int *)addr = p->insn;
349 __asm__ __volatile__("flush %0" : : "r" (addr));
352 bool __init arch_hugetlb_valid_size(unsigned long size)
354 unsigned int hugepage_shift = ilog2(size);
355 unsigned short hv_pgsz_idx;
356 unsigned int hv_pgsz_mask;
358 switch (hugepage_shift) {
359 case HPAGE_16GB_SHIFT:
360 hv_pgsz_mask = HV_PGSZ_MASK_16GB;
361 hv_pgsz_idx = HV_PGSZ_IDX_16GB;
364 case HPAGE_2GB_SHIFT:
365 hv_pgsz_mask = HV_PGSZ_MASK_2GB;
366 hv_pgsz_idx = HV_PGSZ_IDX_2GB;
368 case HPAGE_256MB_SHIFT:
369 hv_pgsz_mask = HV_PGSZ_MASK_256MB;
370 hv_pgsz_idx = HV_PGSZ_IDX_256MB;
373 hv_pgsz_mask = HV_PGSZ_MASK_4MB;
374 hv_pgsz_idx = HV_PGSZ_IDX_4MB;
376 case HPAGE_64K_SHIFT:
377 hv_pgsz_mask = HV_PGSZ_MASK_64K;
378 hv_pgsz_idx = HV_PGSZ_IDX_64K;
384 if ((hv_pgsz_mask & cpu_pgsz_mask) == 0U)
389 #endif /* CONFIG_HUGETLB_PAGE */
391 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
393 struct mm_struct *mm;
398 if (tlb_type != hypervisor) {
399 unsigned long pfn = pte_pfn(pte);
407 /* Don't insert a non-valid PTE into the TSB, we'll deadlock. */
408 if (!pte_accessible(mm, pte))
411 spin_lock_irqsave(&mm->context.lock, flags);
414 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
415 if (mm->context.hugetlb_pte_count || mm->context.thp_pte_count) {
416 unsigned long hugepage_size = PAGE_SIZE;
418 if (is_vm_hugetlb_page(vma))
419 hugepage_size = huge_page_size(hstate_vma(vma));
421 if (hugepage_size >= PUD_SIZE) {
422 unsigned long mask = 0x1ffc00000UL;
424 /* Transfer bits [32:22] from address to resolve
427 pte_val(pte) &= ~mask;
428 pte_val(pte) |= (address & mask);
429 } else if (hugepage_size >= PMD_SIZE) {
430 /* We are fabricating 8MB pages using 4MB
433 pte_val(pte) |= (address & (1UL << REAL_HPAGE_SHIFT));
436 if (hugepage_size >= PMD_SIZE) {
437 __update_mmu_tsb_insert(mm, MM_TSB_HUGE,
438 REAL_HPAGE_SHIFT, address, pte_val(pte));
444 __update_mmu_tsb_insert(mm, MM_TSB_BASE, PAGE_SHIFT,
445 address, pte_val(pte));
447 spin_unlock_irqrestore(&mm->context.lock, flags);
450 void flush_dcache_page(struct page *page)
452 struct address_space *mapping;
455 if (tlb_type == hypervisor)
458 /* Do not bother with the expensive D-cache flush if it
459 * is merely the zero page. The 'bigcore' testcase in GDB
460 * causes this case to run millions of times.
462 if (page == ZERO_PAGE(0))
465 this_cpu = get_cpu();
467 mapping = page_mapping_file(page);
468 if (mapping && !mapping_mapped(mapping)) {
469 int dirty = test_bit(PG_dcache_dirty, &page->flags);
471 int dirty_cpu = dcache_dirty_cpu(page);
473 if (dirty_cpu == this_cpu)
475 smp_flush_dcache_page_impl(page, dirty_cpu);
477 set_dcache_dirty(page, this_cpu);
479 /* We could delay the flush for the !page_mapping
480 * case too. But that case is for exec env/arg
481 * pages and those are %99 certainly going to get
482 * faulted into the tlb (and thus flushed) anyways.
484 flush_dcache_page_impl(page);
490 EXPORT_SYMBOL(flush_dcache_page);
492 void __kprobes flush_icache_range(unsigned long start, unsigned long end)
494 /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
495 if (tlb_type == spitfire) {
498 /* This code only runs on Spitfire cpus so this is
499 * why we can assume _PAGE_PADDR_4U.
501 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE) {
502 unsigned long paddr, mask = _PAGE_PADDR_4U;
504 if (kaddr >= PAGE_OFFSET)
505 paddr = kaddr & mask;
507 pte_t *ptep = virt_to_kpte(kaddr);
509 paddr = pte_val(*ptep) & mask;
511 __flush_icache_page(paddr);
515 EXPORT_SYMBOL(flush_icache_range);
517 void mmu_info(struct seq_file *m)
519 static const char *pgsz_strings[] = {
520 "8K", "64K", "512K", "4MB", "32MB",
521 "256MB", "2GB", "16GB",
525 if (tlb_type == cheetah)
526 seq_printf(m, "MMU Type\t: Cheetah\n");
527 else if (tlb_type == cheetah_plus)
528 seq_printf(m, "MMU Type\t: Cheetah+\n");
529 else if (tlb_type == spitfire)
530 seq_printf(m, "MMU Type\t: Spitfire\n");
531 else if (tlb_type == hypervisor)
532 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
534 seq_printf(m, "MMU Type\t: ???\n");
536 seq_printf(m, "MMU PGSZs\t: ");
538 for (i = 0; i < ARRAY_SIZE(pgsz_strings); i++) {
539 if (cpu_pgsz_mask & (1UL << i)) {
540 seq_printf(m, "%s%s",
541 printed ? "," : "", pgsz_strings[i]);
547 #ifdef CONFIG_DEBUG_DCFLUSH
548 seq_printf(m, "DCPageFlushes\t: %d\n",
549 atomic_read(&dcpage_flushes));
551 seq_printf(m, "DCPageFlushesXC\t: %d\n",
552 atomic_read(&dcpage_flushes_xcall));
553 #endif /* CONFIG_SMP */
554 #endif /* CONFIG_DEBUG_DCFLUSH */
557 struct linux_prom_translation prom_trans[512] __read_mostly;
558 unsigned int prom_trans_ents __read_mostly;
560 unsigned long kern_locked_tte_data;
562 /* The obp translations are saved based on 8k pagesize, since obp can
563 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
564 * HI_OBP_ADDRESS range are handled in ktlb.S.
566 static inline int in_obp_range(unsigned long vaddr)
568 return (vaddr >= LOW_OBP_ADDRESS &&
569 vaddr < HI_OBP_ADDRESS);
572 static int cmp_ptrans(const void *a, const void *b)
574 const struct linux_prom_translation *x = a, *y = b;
576 if (x->virt > y->virt)
578 if (x->virt < y->virt)
583 /* Read OBP translations property into 'prom_trans[]'. */
584 static void __init read_obp_translations(void)
586 int n, node, ents, first, last, i;
588 node = prom_finddevice("/virtual-memory");
589 n = prom_getproplen(node, "translations");
590 if (unlikely(n == 0 || n == -1)) {
591 prom_printf("prom_mappings: Couldn't get size.\n");
594 if (unlikely(n > sizeof(prom_trans))) {
595 prom_printf("prom_mappings: Size %d is too big.\n", n);
599 if ((n = prom_getproperty(node, "translations",
600 (char *)&prom_trans[0],
601 sizeof(prom_trans))) == -1) {
602 prom_printf("prom_mappings: Couldn't get property.\n");
606 n = n / sizeof(struct linux_prom_translation);
610 sort(prom_trans, ents, sizeof(struct linux_prom_translation),
613 /* Now kick out all the non-OBP entries. */
614 for (i = 0; i < ents; i++) {
615 if (in_obp_range(prom_trans[i].virt))
619 for (; i < ents; i++) {
620 if (!in_obp_range(prom_trans[i].virt))
625 for (i = 0; i < (last - first); i++) {
626 struct linux_prom_translation *src = &prom_trans[i + first];
627 struct linux_prom_translation *dest = &prom_trans[i];
631 for (; i < ents; i++) {
632 struct linux_prom_translation *dest = &prom_trans[i];
633 dest->virt = dest->size = dest->data = 0x0UL;
636 prom_trans_ents = last - first;
638 if (tlb_type == spitfire) {
639 /* Clear diag TTE bits. */
640 for (i = 0; i < prom_trans_ents; i++)
641 prom_trans[i].data &= ~0x0003fe0000000000UL;
644 /* Force execute bit on. */
645 for (i = 0; i < prom_trans_ents; i++)
646 prom_trans[i].data |= (tlb_type == hypervisor ?
647 _PAGE_EXEC_4V : _PAGE_EXEC_4U);
650 static void __init hypervisor_tlb_lock(unsigned long vaddr,
654 unsigned long ret = sun4v_mmu_map_perm_addr(vaddr, 0, pte, mmu);
657 prom_printf("hypervisor_tlb_lock[%lx:%x:%lx:%lx]: "
658 "errors with %lx\n", vaddr, 0, pte, mmu, ret);
663 static unsigned long kern_large_tte(unsigned long paddr);
665 static void __init remap_kernel(void)
667 unsigned long phys_page, tte_vaddr, tte_data;
668 int i, tlb_ent = sparc64_highest_locked_tlbent();
670 tte_vaddr = (unsigned long) KERNBASE;
671 phys_page = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB;
672 tte_data = kern_large_tte(phys_page);
674 kern_locked_tte_data = tte_data;
676 /* Now lock us into the TLBs via Hypervisor or OBP. */
677 if (tlb_type == hypervisor) {
678 for (i = 0; i < num_kernel_image_mappings; i++) {
679 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
680 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
681 tte_vaddr += 0x400000;
682 tte_data += 0x400000;
685 for (i = 0; i < num_kernel_image_mappings; i++) {
686 prom_dtlb_load(tlb_ent - i, tte_data, tte_vaddr);
687 prom_itlb_load(tlb_ent - i, tte_data, tte_vaddr);
688 tte_vaddr += 0x400000;
689 tte_data += 0x400000;
691 sparc64_highest_unlocked_tlb_ent = tlb_ent - i;
693 if (tlb_type == cheetah_plus) {
694 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
695 CTX_CHEETAH_PLUS_NUC);
696 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
697 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
702 static void __init inherit_prom_mappings(void)
704 /* Now fixup OBP's idea about where we really are mapped. */
705 printk("Remapping the kernel... ");
710 void prom_world(int enter)
713 * No need to change the address space any more, just flush
714 * the register windows
716 __asm__ __volatile__("flushw");
719 void __flush_dcache_range(unsigned long start, unsigned long end)
723 if (tlb_type == spitfire) {
726 for (va = start; va < end; va += 32) {
727 spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
731 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
734 for (va = start; va < end; va += 32)
735 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
739 "i" (ASI_DCACHE_INVALIDATE));
742 EXPORT_SYMBOL(__flush_dcache_range);
744 /* get_new_mmu_context() uses "cache + 1". */
745 DEFINE_SPINLOCK(ctx_alloc_lock);
746 unsigned long tlb_context_cache = CTX_FIRST_VERSION;
747 #define MAX_CTX_NR (1UL << CTX_NR_BITS)
748 #define CTX_BMAP_SLOTS BITS_TO_LONGS(MAX_CTX_NR)
749 DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR);
750 DEFINE_PER_CPU(struct mm_struct *, per_cpu_secondary_mm) = {0};
752 static void mmu_context_wrap(void)
754 unsigned long old_ver = tlb_context_cache & CTX_VERSION_MASK;
755 unsigned long new_ver, new_ctx, old_ctx;
756 struct mm_struct *mm;
759 bitmap_zero(mmu_context_bmap, 1 << CTX_NR_BITS);
761 /* Reserve kernel context */
762 set_bit(0, mmu_context_bmap);
764 new_ver = (tlb_context_cache & CTX_VERSION_MASK) + CTX_FIRST_VERSION;
765 if (unlikely(new_ver == 0))
766 new_ver = CTX_FIRST_VERSION;
767 tlb_context_cache = new_ver;
770 * Make sure that any new mm that are added into per_cpu_secondary_mm,
771 * are going to go through get_new_mmu_context() path.
776 * Updated versions to current on those CPUs that had valid secondary
779 for_each_online_cpu(cpu) {
781 * If a new mm is stored after we took this mm from the array,
782 * it will go into get_new_mmu_context() path, because we
783 * already bumped the version in tlb_context_cache.
785 mm = per_cpu(per_cpu_secondary_mm, cpu);
787 if (unlikely(!mm || mm == &init_mm))
790 old_ctx = mm->context.sparc64_ctx_val;
791 if (likely((old_ctx & CTX_VERSION_MASK) == old_ver)) {
792 new_ctx = (old_ctx & ~CTX_VERSION_MASK) | new_ver;
793 set_bit(new_ctx & CTX_NR_MASK, mmu_context_bmap);
794 mm->context.sparc64_ctx_val = new_ctx;
799 /* Caller does TLB context flushing on local CPU if necessary.
800 * The caller also ensures that CTX_VALID(mm->context) is false.
802 * We must be careful about boundary cases so that we never
803 * let the user have CTX 0 (nucleus) or we ever use a CTX
804 * version of zero (and thus NO_CONTEXT would not be caught
805 * by version mis-match tests in mmu_context.h).
807 * Always invoked with interrupts disabled.
809 void get_new_mmu_context(struct mm_struct *mm)
811 unsigned long ctx, new_ctx;
812 unsigned long orig_pgsz_bits;
814 spin_lock(&ctx_alloc_lock);
816 /* wrap might have happened, test again if our context became valid */
817 if (unlikely(CTX_VALID(mm->context)))
819 orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
820 ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
821 new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
822 if (new_ctx >= (1 << CTX_NR_BITS)) {
823 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
824 if (new_ctx >= ctx) {
829 if (mm->context.sparc64_ctx_val)
830 cpumask_clear(mm_cpumask(mm));
831 mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
832 new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
833 tlb_context_cache = new_ctx;
834 mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
836 spin_unlock(&ctx_alloc_lock);
839 static int numa_enabled = 1;
840 static int numa_debug;
842 static int __init early_numa(char *p)
847 if (strstr(p, "off"))
850 if (strstr(p, "debug"))
855 early_param("numa", early_numa);
857 #define numadbg(f, a...) \
858 do { if (numa_debug) \
859 printk(KERN_INFO f, ## a); \
862 static void __init find_ramdisk(unsigned long phys_base)
864 #ifdef CONFIG_BLK_DEV_INITRD
865 if (sparc_ramdisk_image || sparc_ramdisk_image64) {
866 unsigned long ramdisk_image;
868 /* Older versions of the bootloader only supported a
869 * 32-bit physical address for the ramdisk image
870 * location, stored at sparc_ramdisk_image. Newer
871 * SILO versions set sparc_ramdisk_image to zero and
872 * provide a full 64-bit physical address at
873 * sparc_ramdisk_image64.
875 ramdisk_image = sparc_ramdisk_image;
877 ramdisk_image = sparc_ramdisk_image64;
879 /* Another bootloader quirk. The bootloader normalizes
880 * the physical address to KERNBASE, so we have to
881 * factor that back out and add in the lowest valid
882 * physical page address to get the true physical address.
884 ramdisk_image -= KERNBASE;
885 ramdisk_image += phys_base;
887 numadbg("Found ramdisk at physical address 0x%lx, size %u\n",
888 ramdisk_image, sparc_ramdisk_size);
890 initrd_start = ramdisk_image;
891 initrd_end = ramdisk_image + sparc_ramdisk_size;
893 memblock_reserve(initrd_start, sparc_ramdisk_size);
895 initrd_start += PAGE_OFFSET;
896 initrd_end += PAGE_OFFSET;
901 struct node_mem_mask {
905 static struct node_mem_mask node_masks[MAX_NUMNODES];
906 static int num_node_masks;
910 struct mdesc_mlgroup {
917 static struct mdesc_mlgroup *mlgroups;
918 static int num_mlgroups;
920 int numa_cpu_lookup_table[NR_CPUS];
921 cpumask_t numa_cpumask_lookup_table[MAX_NUMNODES];
923 struct mdesc_mblock {
926 u64 offset; /* RA-to-PA */
928 static struct mdesc_mblock *mblocks;
929 static int num_mblocks;
931 static struct mdesc_mblock * __init addr_to_mblock(unsigned long addr)
933 struct mdesc_mblock *m = NULL;
936 for (i = 0; i < num_mblocks; i++) {
939 if (addr >= m->base &&
940 addr < (m->base + m->size)) {
948 static u64 __init memblock_nid_range_sun4u(u64 start, u64 end, int *nid)
950 int prev_nid, new_nid;
952 prev_nid = NUMA_NO_NODE;
953 for ( ; start < end; start += PAGE_SIZE) {
954 for (new_nid = 0; new_nid < num_node_masks; new_nid++) {
955 struct node_mem_mask *p = &node_masks[new_nid];
957 if ((start & p->mask) == p->match) {
958 if (prev_nid == NUMA_NO_NODE)
964 if (new_nid == num_node_masks) {
966 WARN_ONCE(1, "addr[%Lx] doesn't match a NUMA node rule. Some memory will be owned by node 0.",
971 if (prev_nid != new_nid)
976 return start > end ? end : start;
979 static u64 __init memblock_nid_range(u64 start, u64 end, int *nid)
981 u64 ret_end, pa_start, m_mask, m_match, m_end;
982 struct mdesc_mblock *mblock;
985 if (tlb_type != hypervisor)
986 return memblock_nid_range_sun4u(start, end, nid);
988 mblock = addr_to_mblock(start);
990 WARN_ONCE(1, "memblock_nid_range: Can't find mblock addr[%Lx]",
998 pa_start = start + mblock->offset;
1002 for (_nid = 0; _nid < num_node_masks; _nid++) {
1003 struct node_mem_mask *const m = &node_masks[_nid];
1005 if ((pa_start & m->mask) == m->match) {
1012 if (num_node_masks == _nid) {
1013 /* We could not find NUMA group, so default to 0, but lets
1014 * search for latency group, so we could calculate the correct
1015 * end address that we return
1019 for (i = 0; i < num_mlgroups; i++) {
1020 struct mdesc_mlgroup *const m = &mlgroups[i];
1022 if ((pa_start & m->mask) == m->match) {
1029 if (i == num_mlgroups) {
1030 WARN_ONCE(1, "memblock_nid_range: Can't find latency group addr[%Lx]",
1039 * Each latency group has match and mask, and each memory block has an
1040 * offset. An address belongs to a latency group if its address matches
1041 * the following formula: ((addr + offset) & mask) == match
1042 * It is, however, slow to check every single page if it matches a
1043 * particular latency group. As optimization we calculate end value by
1044 * using bit arithmetics.
1046 m_end = m_match + (1ul << __ffs(m_mask)) - mblock->offset;
1047 m_end += pa_start & ~((1ul << fls64(m_mask)) - 1);
1048 ret_end = m_end > end ? end : m_end;
1056 /* This must be invoked after performing all of the necessary
1057 * memblock_set_node() calls for 'nid'. We need to be able to get
1058 * correct data from get_pfn_range_for_nid().
1060 static void __init allocate_node_data(int nid)
1062 struct pglist_data *p;
1063 unsigned long start_pfn, end_pfn;
1066 NODE_DATA(nid) = memblock_alloc_node(sizeof(struct pglist_data),
1067 SMP_CACHE_BYTES, nid);
1068 if (!NODE_DATA(nid)) {
1069 prom_printf("Cannot allocate pglist_data for nid[%d]\n", nid);
1073 NODE_DATA(nid)->node_id = nid;
1078 get_pfn_range_for_nid(nid, &start_pfn, &end_pfn);
1079 p->node_start_pfn = start_pfn;
1080 p->node_spanned_pages = end_pfn - start_pfn;
1083 static void init_node_masks_nonnuma(void)
1089 numadbg("Initializing tables for non-numa.\n");
1091 node_masks[0].mask = 0;
1092 node_masks[0].match = 0;
1096 for (i = 0; i < NR_CPUS; i++)
1097 numa_cpu_lookup_table[i] = 0;
1099 cpumask_setall(&numa_cpumask_lookup_table[0]);
1104 struct pglist_data *node_data[MAX_NUMNODES];
1106 EXPORT_SYMBOL(numa_cpu_lookup_table);
1107 EXPORT_SYMBOL(numa_cpumask_lookup_table);
1108 EXPORT_SYMBOL(node_data);
1110 static int scan_pio_for_cfg_handle(struct mdesc_handle *md, u64 pio,
1115 mdesc_for_each_arc(arc, md, pio, MDESC_ARC_TYPE_FWD) {
1116 u64 target = mdesc_arc_target(md, arc);
1119 val = mdesc_get_property(md, target,
1120 "cfg-handle", NULL);
1121 if (val && *val == cfg_handle)
1127 static int scan_arcs_for_cfg_handle(struct mdesc_handle *md, u64 grp,
1130 u64 arc, candidate, best_latency = ~(u64)0;
1132 candidate = MDESC_NODE_NULL;
1133 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1134 u64 target = mdesc_arc_target(md, arc);
1135 const char *name = mdesc_node_name(md, target);
1138 if (strcmp(name, "pio-latency-group"))
1141 val = mdesc_get_property(md, target, "latency", NULL);
1145 if (*val < best_latency) {
1147 best_latency = *val;
1151 if (candidate == MDESC_NODE_NULL)
1154 return scan_pio_for_cfg_handle(md, candidate, cfg_handle);
1157 int of_node_to_nid(struct device_node *dp)
1159 const struct linux_prom64_registers *regs;
1160 struct mdesc_handle *md;
1165 /* This is the right thing to do on currently supported
1166 * SUN4U NUMA platforms as well, as the PCI controller does
1167 * not sit behind any particular memory controller.
1172 regs = of_get_property(dp, "reg", NULL);
1176 cfg_handle = (regs->phys_addr >> 32UL) & 0x0fffffff;
1182 mdesc_for_each_node_by_name(md, grp, "group") {
1183 if (!scan_arcs_for_cfg_handle(md, grp, cfg_handle)) {
1195 static void __init add_node_ranges(void)
1197 phys_addr_t start, end;
1198 unsigned long prev_max;
1202 prev_max = memblock.memory.max;
1204 for_each_mem_range(i, &start, &end) {
1205 while (start < end) {
1206 unsigned long this_end;
1209 this_end = memblock_nid_range(start, end, &nid);
1211 numadbg("Setting memblock NUMA node nid[%d] "
1212 "start[%llx] end[%lx]\n",
1213 nid, start, this_end);
1215 memblock_set_node(start, this_end - start,
1216 &memblock.memory, nid);
1217 if (memblock.memory.max != prev_max)
1218 goto memblock_resized;
1224 static int __init grab_mlgroups(struct mdesc_handle *md)
1226 unsigned long paddr;
1230 mdesc_for_each_node_by_name(md, node, "memory-latency-group")
1235 paddr = memblock_phys_alloc(count * sizeof(struct mdesc_mlgroup),
1240 mlgroups = __va(paddr);
1241 num_mlgroups = count;
1244 mdesc_for_each_node_by_name(md, node, "memory-latency-group") {
1245 struct mdesc_mlgroup *m = &mlgroups[count++];
1250 val = mdesc_get_property(md, node, "latency", NULL);
1252 val = mdesc_get_property(md, node, "address-match", NULL);
1254 val = mdesc_get_property(md, node, "address-mask", NULL);
1257 numadbg("MLGROUP[%d]: node[%llx] latency[%llx] "
1258 "match[%llx] mask[%llx]\n",
1259 count - 1, m->node, m->latency, m->match, m->mask);
1265 static int __init grab_mblocks(struct mdesc_handle *md)
1267 unsigned long paddr;
1271 mdesc_for_each_node_by_name(md, node, "mblock")
1276 paddr = memblock_phys_alloc(count * sizeof(struct mdesc_mblock),
1281 mblocks = __va(paddr);
1282 num_mblocks = count;
1285 mdesc_for_each_node_by_name(md, node, "mblock") {
1286 struct mdesc_mblock *m = &mblocks[count++];
1289 val = mdesc_get_property(md, node, "base", NULL);
1291 val = mdesc_get_property(md, node, "size", NULL);
1293 val = mdesc_get_property(md, node,
1294 "address-congruence-offset", NULL);
1296 /* The address-congruence-offset property is optional.
1297 * Explicity zero it be identifty this.
1304 numadbg("MBLOCK[%d]: base[%llx] size[%llx] offset[%llx]\n",
1305 count - 1, m->base, m->size, m->offset);
1311 static void __init numa_parse_mdesc_group_cpus(struct mdesc_handle *md,
1312 u64 grp, cpumask_t *mask)
1316 cpumask_clear(mask);
1318 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_BACK) {
1319 u64 target = mdesc_arc_target(md, arc);
1320 const char *name = mdesc_node_name(md, target);
1323 if (strcmp(name, "cpu"))
1325 id = mdesc_get_property(md, target, "id", NULL);
1326 if (*id < nr_cpu_ids)
1327 cpumask_set_cpu(*id, mask);
1331 static struct mdesc_mlgroup * __init find_mlgroup(u64 node)
1335 for (i = 0; i < num_mlgroups; i++) {
1336 struct mdesc_mlgroup *m = &mlgroups[i];
1337 if (m->node == node)
1343 int __node_distance(int from, int to)
1345 if ((from >= MAX_NUMNODES) || (to >= MAX_NUMNODES)) {
1346 pr_warn("Returning default NUMA distance value for %d->%d\n",
1348 return (from == to) ? LOCAL_DISTANCE : REMOTE_DISTANCE;
1350 return numa_latency[from][to];
1352 EXPORT_SYMBOL(__node_distance);
1354 static int __init find_best_numa_node_for_mlgroup(struct mdesc_mlgroup *grp)
1358 for (i = 0; i < MAX_NUMNODES; i++) {
1359 struct node_mem_mask *n = &node_masks[i];
1361 if ((grp->mask == n->mask) && (grp->match == n->match))
1367 static void __init find_numa_latencies_for_group(struct mdesc_handle *md,
1372 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1374 u64 target = mdesc_arc_target(md, arc);
1375 struct mdesc_mlgroup *m = find_mlgroup(target);
1379 tnode = find_best_numa_node_for_mlgroup(m);
1380 if (tnode == MAX_NUMNODES)
1382 numa_latency[index][tnode] = m->latency;
1386 static int __init numa_attach_mlgroup(struct mdesc_handle *md, u64 grp,
1389 struct mdesc_mlgroup *candidate = NULL;
1390 u64 arc, best_latency = ~(u64)0;
1391 struct node_mem_mask *n;
1393 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1394 u64 target = mdesc_arc_target(md, arc);
1395 struct mdesc_mlgroup *m = find_mlgroup(target);
1398 if (m->latency < best_latency) {
1400 best_latency = m->latency;
1406 if (num_node_masks != index) {
1407 printk(KERN_ERR "Inconsistent NUMA state, "
1408 "index[%d] != num_node_masks[%d]\n",
1409 index, num_node_masks);
1413 n = &node_masks[num_node_masks++];
1415 n->mask = candidate->mask;
1416 n->match = candidate->match;
1418 numadbg("NUMA NODE[%d]: mask[%lx] match[%lx] (latency[%llx])\n",
1419 index, n->mask, n->match, candidate->latency);
1424 static int __init numa_parse_mdesc_group(struct mdesc_handle *md, u64 grp,
1430 numa_parse_mdesc_group_cpus(md, grp, &mask);
1432 for_each_cpu(cpu, &mask)
1433 numa_cpu_lookup_table[cpu] = index;
1434 cpumask_copy(&numa_cpumask_lookup_table[index], &mask);
1437 printk(KERN_INFO "NUMA GROUP[%d]: cpus [ ", index);
1438 for_each_cpu(cpu, &mask)
1443 return numa_attach_mlgroup(md, grp, index);
1446 static int __init numa_parse_mdesc(void)
1448 struct mdesc_handle *md = mdesc_grab();
1449 int i, j, err, count;
1452 node = mdesc_node_by_name(md, MDESC_NODE_NULL, "latency-groups");
1453 if (node == MDESC_NODE_NULL) {
1458 err = grab_mblocks(md);
1462 err = grab_mlgroups(md);
1467 mdesc_for_each_node_by_name(md, node, "group") {
1468 err = numa_parse_mdesc_group(md, node, count);
1475 mdesc_for_each_node_by_name(md, node, "group") {
1476 find_numa_latencies_for_group(md, node, count);
1480 /* Normalize numa latency matrix according to ACPI SLIT spec. */
1481 for (i = 0; i < MAX_NUMNODES; i++) {
1482 u64 self_latency = numa_latency[i][i];
1484 for (j = 0; j < MAX_NUMNODES; j++) {
1485 numa_latency[i][j] =
1486 (numa_latency[i][j] * LOCAL_DISTANCE) /
1493 for (i = 0; i < num_node_masks; i++) {
1494 allocate_node_data(i);
1504 static int __init numa_parse_jbus(void)
1506 unsigned long cpu, index;
1508 /* NUMA node id is encoded in bits 36 and higher, and there is
1509 * a 1-to-1 mapping from CPU ID to NUMA node ID.
1512 for_each_present_cpu(cpu) {
1513 numa_cpu_lookup_table[cpu] = index;
1514 cpumask_copy(&numa_cpumask_lookup_table[index], cpumask_of(cpu));
1515 node_masks[index].mask = ~((1UL << 36UL) - 1UL);
1516 node_masks[index].match = cpu << 36UL;
1520 num_node_masks = index;
1524 for (index = 0; index < num_node_masks; index++) {
1525 allocate_node_data(index);
1526 node_set_online(index);
1532 static int __init numa_parse_sun4u(void)
1534 if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1537 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
1538 if ((ver >> 32UL) == __JALAPENO_ID ||
1539 (ver >> 32UL) == __SERRANO_ID)
1540 return numa_parse_jbus();
1545 static int __init bootmem_init_numa(void)
1550 numadbg("bootmem_init_numa()\n");
1552 /* Some sane defaults for numa latency values */
1553 for (i = 0; i < MAX_NUMNODES; i++) {
1554 for (j = 0; j < MAX_NUMNODES; j++)
1555 numa_latency[i][j] = (i == j) ?
1556 LOCAL_DISTANCE : REMOTE_DISTANCE;
1560 if (tlb_type == hypervisor)
1561 err = numa_parse_mdesc();
1563 err = numa_parse_sun4u();
1570 static int bootmem_init_numa(void)
1577 static void __init bootmem_init_nonnuma(void)
1579 unsigned long top_of_ram = memblock_end_of_DRAM();
1580 unsigned long total_ram = memblock_phys_mem_size();
1582 numadbg("bootmem_init_nonnuma()\n");
1584 printk(KERN_INFO "Top of RAM: 0x%lx, Total RAM: 0x%lx\n",
1585 top_of_ram, total_ram);
1586 printk(KERN_INFO "Memory hole size: %ldMB\n",
1587 (top_of_ram - total_ram) >> 20);
1589 init_node_masks_nonnuma();
1590 memblock_set_node(0, PHYS_ADDR_MAX, &memblock.memory, 0);
1591 allocate_node_data(0);
1595 static unsigned long __init bootmem_init(unsigned long phys_base)
1597 unsigned long end_pfn;
1599 end_pfn = memblock_end_of_DRAM() >> PAGE_SHIFT;
1600 max_pfn = max_low_pfn = end_pfn;
1601 min_low_pfn = (phys_base >> PAGE_SHIFT);
1603 if (bootmem_init_numa() < 0)
1604 bootmem_init_nonnuma();
1606 /* Dump memblock with node info. */
1607 memblock_dump_all();
1609 /* XXX cpu notifier XXX */
1616 static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
1617 static int pall_ents __initdata;
1619 static unsigned long max_phys_bits = 40;
1621 bool kern_addr_valid(unsigned long addr)
1629 if ((long)addr < 0L) {
1630 unsigned long pa = __pa(addr);
1632 if ((pa >> max_phys_bits) != 0UL)
1635 return pfn_valid(pa >> PAGE_SHIFT);
1638 if (addr >= (unsigned long) KERNBASE &&
1639 addr < (unsigned long)&_end)
1642 pgd = pgd_offset_k(addr);
1646 p4d = p4d_offset(pgd, addr);
1650 pud = pud_offset(p4d, addr);
1654 if (pud_large(*pud))
1655 return pfn_valid(pud_pfn(*pud));
1657 pmd = pmd_offset(pud, addr);
1661 if (pmd_large(*pmd))
1662 return pfn_valid(pmd_pfn(*pmd));
1664 pte = pte_offset_kernel(pmd, addr);
1668 return pfn_valid(pte_pfn(*pte));
1670 EXPORT_SYMBOL(kern_addr_valid);
1672 static unsigned long __ref kernel_map_hugepud(unsigned long vstart,
1676 const unsigned long mask16gb = (1UL << 34) - 1UL;
1677 u64 pte_val = vstart;
1679 /* Each PUD is 8GB */
1680 if ((vstart & mask16gb) ||
1681 (vend - vstart <= mask16gb)) {
1682 pte_val ^= kern_linear_pte_xor[2];
1683 pud_val(*pud) = pte_val | _PAGE_PUD_HUGE;
1685 return vstart + PUD_SIZE;
1688 pte_val ^= kern_linear_pte_xor[3];
1689 pte_val |= _PAGE_PUD_HUGE;
1691 vend = vstart + mask16gb + 1UL;
1692 while (vstart < vend) {
1693 pud_val(*pud) = pte_val;
1695 pte_val += PUD_SIZE;
1702 static bool kernel_can_map_hugepud(unsigned long vstart, unsigned long vend,
1705 if (guard && !(vstart & ~PUD_MASK) && (vend - vstart) >= PUD_SIZE)
1711 static unsigned long __ref kernel_map_hugepmd(unsigned long vstart,
1715 const unsigned long mask256mb = (1UL << 28) - 1UL;
1716 const unsigned long mask2gb = (1UL << 31) - 1UL;
1717 u64 pte_val = vstart;
1719 /* Each PMD is 8MB */
1720 if ((vstart & mask256mb) ||
1721 (vend - vstart <= mask256mb)) {
1722 pte_val ^= kern_linear_pte_xor[0];
1723 pmd_val(*pmd) = pte_val | _PAGE_PMD_HUGE;
1725 return vstart + PMD_SIZE;
1728 if ((vstart & mask2gb) ||
1729 (vend - vstart <= mask2gb)) {
1730 pte_val ^= kern_linear_pte_xor[1];
1731 pte_val |= _PAGE_PMD_HUGE;
1732 vend = vstart + mask256mb + 1UL;
1734 pte_val ^= kern_linear_pte_xor[2];
1735 pte_val |= _PAGE_PMD_HUGE;
1736 vend = vstart + mask2gb + 1UL;
1739 while (vstart < vend) {
1740 pmd_val(*pmd) = pte_val;
1742 pte_val += PMD_SIZE;
1750 static bool kernel_can_map_hugepmd(unsigned long vstart, unsigned long vend,
1753 if (guard && !(vstart & ~PMD_MASK) && (vend - vstart) >= PMD_SIZE)
1759 static unsigned long __ref kernel_map_range(unsigned long pstart,
1760 unsigned long pend, pgprot_t prot,
1763 unsigned long vstart = PAGE_OFFSET + pstart;
1764 unsigned long vend = PAGE_OFFSET + pend;
1765 unsigned long alloc_bytes = 0UL;
1767 if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
1768 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
1773 while (vstart < vend) {
1774 unsigned long this_end, paddr = __pa(vstart);
1775 pgd_t *pgd = pgd_offset_k(vstart);
1781 if (pgd_none(*pgd)) {
1784 new = memblock_alloc_from(PAGE_SIZE, PAGE_SIZE,
1788 alloc_bytes += PAGE_SIZE;
1789 pgd_populate(&init_mm, pgd, new);
1792 p4d = p4d_offset(pgd, vstart);
1793 if (p4d_none(*p4d)) {
1796 new = memblock_alloc_from(PAGE_SIZE, PAGE_SIZE,
1800 alloc_bytes += PAGE_SIZE;
1801 p4d_populate(&init_mm, p4d, new);
1804 pud = pud_offset(p4d, vstart);
1805 if (pud_none(*pud)) {
1808 if (kernel_can_map_hugepud(vstart, vend, use_huge)) {
1809 vstart = kernel_map_hugepud(vstart, vend, pud);
1812 new = memblock_alloc_from(PAGE_SIZE, PAGE_SIZE,
1816 alloc_bytes += PAGE_SIZE;
1817 pud_populate(&init_mm, pud, new);
1820 pmd = pmd_offset(pud, vstart);
1821 if (pmd_none(*pmd)) {
1824 if (kernel_can_map_hugepmd(vstart, vend, use_huge)) {
1825 vstart = kernel_map_hugepmd(vstart, vend, pmd);
1828 new = memblock_alloc_from(PAGE_SIZE, PAGE_SIZE,
1832 alloc_bytes += PAGE_SIZE;
1833 pmd_populate_kernel(&init_mm, pmd, new);
1836 pte = pte_offset_kernel(pmd, vstart);
1837 this_end = (vstart + PMD_SIZE) & PMD_MASK;
1838 if (this_end > vend)
1841 while (vstart < this_end) {
1842 pte_val(*pte) = (paddr | pgprot_val(prot));
1844 vstart += PAGE_SIZE;
1853 panic("%s: Failed to allocate %lu bytes align=%lx from=%lx\n",
1854 __func__, PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1858 static void __init flush_all_kernel_tsbs(void)
1862 for (i = 0; i < KERNEL_TSB_NENTRIES; i++) {
1863 struct tsb *ent = &swapper_tsb[i];
1865 ent->tag = (1UL << TSB_TAG_INVALID_BIT);
1867 #ifndef CONFIG_DEBUG_PAGEALLOC
1868 for (i = 0; i < KERNEL_TSB4M_NENTRIES; i++) {
1869 struct tsb *ent = &swapper_4m_tsb[i];
1871 ent->tag = (1UL << TSB_TAG_INVALID_BIT);
1876 extern unsigned int kvmap_linear_patch[1];
1878 static void __init kernel_physical_mapping_init(void)
1880 unsigned long i, mem_alloced = 0UL;
1881 bool use_huge = true;
1883 #ifdef CONFIG_DEBUG_PAGEALLOC
1886 for (i = 0; i < pall_ents; i++) {
1887 unsigned long phys_start, phys_end;
1889 phys_start = pall[i].phys_addr;
1890 phys_end = phys_start + pall[i].reg_size;
1892 mem_alloced += kernel_map_range(phys_start, phys_end,
1893 PAGE_KERNEL, use_huge);
1896 printk("Allocated %ld bytes for kernel page tables.\n",
1899 kvmap_linear_patch[0] = 0x01000000; /* nop */
1900 flushi(&kvmap_linear_patch[0]);
1902 flush_all_kernel_tsbs();
1907 #ifdef CONFIG_DEBUG_PAGEALLOC
1908 void __kernel_map_pages(struct page *page, int numpages, int enable)
1910 unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1911 unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1913 kernel_map_range(phys_start, phys_end,
1914 (enable ? PAGE_KERNEL : __pgprot(0)), false);
1916 flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1917 PAGE_OFFSET + phys_end);
1919 /* we should perform an IPI and flush all tlbs,
1920 * but that can deadlock->flush only current cpu.
1922 __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1923 PAGE_OFFSET + phys_end);
1927 unsigned long __init find_ecache_flush_span(unsigned long size)
1931 for (i = 0; i < pavail_ents; i++) {
1932 if (pavail[i].reg_size >= size)
1933 return pavail[i].phys_addr;
1939 unsigned long PAGE_OFFSET;
1940 EXPORT_SYMBOL(PAGE_OFFSET);
1942 unsigned long VMALLOC_END = 0x0000010000000000UL;
1943 EXPORT_SYMBOL(VMALLOC_END);
1945 unsigned long sparc64_va_hole_top = 0xfffff80000000000UL;
1946 unsigned long sparc64_va_hole_bottom = 0x0000080000000000UL;
1948 static void __init setup_page_offset(void)
1950 if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1951 /* Cheetah/Panther support a full 64-bit virtual
1952 * address, so we can use all that our page tables
1955 sparc64_va_hole_top = 0xfff0000000000000UL;
1956 sparc64_va_hole_bottom = 0x0010000000000000UL;
1959 } else if (tlb_type == hypervisor) {
1960 switch (sun4v_chip_type) {
1961 case SUN4V_CHIP_NIAGARA1:
1962 case SUN4V_CHIP_NIAGARA2:
1963 /* T1 and T2 support 48-bit virtual addresses. */
1964 sparc64_va_hole_top = 0xffff800000000000UL;
1965 sparc64_va_hole_bottom = 0x0000800000000000UL;
1969 case SUN4V_CHIP_NIAGARA3:
1970 /* T3 supports 48-bit virtual addresses. */
1971 sparc64_va_hole_top = 0xffff800000000000UL;
1972 sparc64_va_hole_bottom = 0x0000800000000000UL;
1976 case SUN4V_CHIP_NIAGARA4:
1977 case SUN4V_CHIP_NIAGARA5:
1978 case SUN4V_CHIP_SPARC64X:
1979 case SUN4V_CHIP_SPARC_M6:
1980 /* T4 and later support 52-bit virtual addresses. */
1981 sparc64_va_hole_top = 0xfff8000000000000UL;
1982 sparc64_va_hole_bottom = 0x0008000000000000UL;
1985 case SUN4V_CHIP_SPARC_M7:
1986 case SUN4V_CHIP_SPARC_SN:
1987 /* M7 and later support 52-bit virtual addresses. */
1988 sparc64_va_hole_top = 0xfff8000000000000UL;
1989 sparc64_va_hole_bottom = 0x0008000000000000UL;
1992 case SUN4V_CHIP_SPARC_M8:
1994 /* M8 and later support 54-bit virtual addresses.
1995 * However, restricting M8 and above VA bits to 53
1996 * as 4-level page table cannot support more than
1999 sparc64_va_hole_top = 0xfff0000000000000UL;
2000 sparc64_va_hole_bottom = 0x0010000000000000UL;
2006 if (max_phys_bits > MAX_PHYS_ADDRESS_BITS) {
2007 prom_printf("MAX_PHYS_ADDRESS_BITS is too small, need %lu\n",
2012 PAGE_OFFSET = sparc64_va_hole_top;
2013 VMALLOC_END = ((sparc64_va_hole_bottom >> 1) +
2014 (sparc64_va_hole_bottom >> 2));
2016 pr_info("MM: PAGE_OFFSET is 0x%016lx (max_phys_bits == %lu)\n",
2017 PAGE_OFFSET, max_phys_bits);
2018 pr_info("MM: VMALLOC [0x%016lx --> 0x%016lx]\n",
2019 VMALLOC_START, VMALLOC_END);
2020 pr_info("MM: VMEMMAP [0x%016lx --> 0x%016lx]\n",
2021 VMEMMAP_BASE, VMEMMAP_BASE << 1);
2024 static void __init tsb_phys_patch(void)
2026 struct tsb_ldquad_phys_patch_entry *pquad;
2027 struct tsb_phys_patch_entry *p;
2029 pquad = &__tsb_ldquad_phys_patch;
2030 while (pquad < &__tsb_ldquad_phys_patch_end) {
2031 unsigned long addr = pquad->addr;
2033 if (tlb_type == hypervisor)
2034 *(unsigned int *) addr = pquad->sun4v_insn;
2036 *(unsigned int *) addr = pquad->sun4u_insn;
2038 __asm__ __volatile__("flush %0"
2045 p = &__tsb_phys_patch;
2046 while (p < &__tsb_phys_patch_end) {
2047 unsigned long addr = p->addr;
2049 *(unsigned int *) addr = p->insn;
2051 __asm__ __volatile__("flush %0"
2059 /* Don't mark as init, we give this to the Hypervisor. */
2060 #ifndef CONFIG_DEBUG_PAGEALLOC
2061 #define NUM_KTSB_DESCR 2
2063 #define NUM_KTSB_DESCR 1
2065 static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR];
2067 /* The swapper TSBs are loaded with a base sequence of:
2069 * sethi %uhi(SYMBOL), REG1
2070 * sethi %hi(SYMBOL), REG2
2071 * or REG1, %ulo(SYMBOL), REG1
2072 * or REG2, %lo(SYMBOL), REG2
2073 * sllx REG1, 32, REG1
2074 * or REG1, REG2, REG1
2076 * When we use physical addressing for the TSB accesses, we patch the
2077 * first four instructions in the above sequence.
2080 static void patch_one_ktsb_phys(unsigned int *start, unsigned int *end, unsigned long pa)
2082 unsigned long high_bits, low_bits;
2084 high_bits = (pa >> 32) & 0xffffffff;
2085 low_bits = (pa >> 0) & 0xffffffff;
2087 while (start < end) {
2088 unsigned int *ia = (unsigned int *)(unsigned long)*start;
2090 ia[0] = (ia[0] & ~0x3fffff) | (high_bits >> 10);
2091 __asm__ __volatile__("flush %0" : : "r" (ia));
2093 ia[1] = (ia[1] & ~0x3fffff) | (low_bits >> 10);
2094 __asm__ __volatile__("flush %0" : : "r" (ia + 1));
2096 ia[2] = (ia[2] & ~0x1fff) | (high_bits & 0x3ff);
2097 __asm__ __volatile__("flush %0" : : "r" (ia + 2));
2099 ia[3] = (ia[3] & ~0x1fff) | (low_bits & 0x3ff);
2100 __asm__ __volatile__("flush %0" : : "r" (ia + 3));
2106 static void ktsb_phys_patch(void)
2108 extern unsigned int __swapper_tsb_phys_patch;
2109 extern unsigned int __swapper_tsb_phys_patch_end;
2110 unsigned long ktsb_pa;
2112 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
2113 patch_one_ktsb_phys(&__swapper_tsb_phys_patch,
2114 &__swapper_tsb_phys_patch_end, ktsb_pa);
2115 #ifndef CONFIG_DEBUG_PAGEALLOC
2117 extern unsigned int __swapper_4m_tsb_phys_patch;
2118 extern unsigned int __swapper_4m_tsb_phys_patch_end;
2119 ktsb_pa = (kern_base +
2120 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
2121 patch_one_ktsb_phys(&__swapper_4m_tsb_phys_patch,
2122 &__swapper_4m_tsb_phys_patch_end, ktsb_pa);
2127 static void __init sun4v_ktsb_init(void)
2129 unsigned long ktsb_pa;
2131 /* First KTSB for PAGE_SIZE mappings. */
2132 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
2134 switch (PAGE_SIZE) {
2137 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
2138 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
2142 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
2143 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
2147 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
2148 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
2151 case 4 * 1024 * 1024:
2152 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
2153 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
2157 ktsb_descr[0].assoc = 1;
2158 ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
2159 ktsb_descr[0].ctx_idx = 0;
2160 ktsb_descr[0].tsb_base = ktsb_pa;
2161 ktsb_descr[0].resv = 0;
2163 #ifndef CONFIG_DEBUG_PAGEALLOC
2164 /* Second KTSB for 4MB/256MB/2GB/16GB mappings. */
2165 ktsb_pa = (kern_base +
2166 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
2168 ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB;
2169 ktsb_descr[1].pgsz_mask = ((HV_PGSZ_MASK_4MB |
2170 HV_PGSZ_MASK_256MB |
2172 HV_PGSZ_MASK_16GB) &
2174 ktsb_descr[1].assoc = 1;
2175 ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES;
2176 ktsb_descr[1].ctx_idx = 0;
2177 ktsb_descr[1].tsb_base = ktsb_pa;
2178 ktsb_descr[1].resv = 0;
2182 void sun4v_ktsb_register(void)
2184 unsigned long pa, ret;
2186 pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);
2188 ret = sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR, pa);
2190 prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: "
2191 "errors with %lx\n", pa, ret);
2196 static void __init sun4u_linear_pte_xor_finalize(void)
2198 #ifndef CONFIG_DEBUG_PAGEALLOC
2199 /* This is where we would add Panther support for
2200 * 32MB and 256MB pages.
2205 static void __init sun4v_linear_pte_xor_finalize(void)
2207 unsigned long pagecv_flag;
2209 /* Bit 9 of TTE is no longer CV bit on M7 processor and it instead
2210 * enables MCD error. Do not set bit 9 on M7 processor.
2212 switch (sun4v_chip_type) {
2213 case SUN4V_CHIP_SPARC_M7:
2214 case SUN4V_CHIP_SPARC_M8:
2215 case SUN4V_CHIP_SPARC_SN:
2219 pagecv_flag = _PAGE_CV_4V;
2222 #ifndef CONFIG_DEBUG_PAGEALLOC
2223 if (cpu_pgsz_mask & HV_PGSZ_MASK_256MB) {
2224 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^
2226 kern_linear_pte_xor[1] |= (_PAGE_CP_4V | pagecv_flag |
2227 _PAGE_P_4V | _PAGE_W_4V);
2229 kern_linear_pte_xor[1] = kern_linear_pte_xor[0];
2232 if (cpu_pgsz_mask & HV_PGSZ_MASK_2GB) {
2233 kern_linear_pte_xor[2] = (_PAGE_VALID | _PAGE_SZ2GB_4V) ^
2235 kern_linear_pte_xor[2] |= (_PAGE_CP_4V | pagecv_flag |
2236 _PAGE_P_4V | _PAGE_W_4V);
2238 kern_linear_pte_xor[2] = kern_linear_pte_xor[1];
2241 if (cpu_pgsz_mask & HV_PGSZ_MASK_16GB) {
2242 kern_linear_pte_xor[3] = (_PAGE_VALID | _PAGE_SZ16GB_4V) ^
2244 kern_linear_pte_xor[3] |= (_PAGE_CP_4V | pagecv_flag |
2245 _PAGE_P_4V | _PAGE_W_4V);
2247 kern_linear_pte_xor[3] = kern_linear_pte_xor[2];
2252 /* paging_init() sets up the page tables */
2254 static unsigned long last_valid_pfn;
2256 static void sun4u_pgprot_init(void);
2257 static void sun4v_pgprot_init(void);
2259 #define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U)
2260 #define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V)
2261 #define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
2262 #define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
2263 #define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
2264 #define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
2266 /* We need to exclude reserved regions. This exclusion will include
2267 * vmlinux and initrd. To be more precise the initrd size could be used to
2268 * compute a new lower limit because it is freed later during initialization.
2270 static void __init reduce_memory(phys_addr_t limit_ram)
2272 limit_ram += memblock_reserved_size();
2273 memblock_enforce_memory_limit(limit_ram);
2276 void __init paging_init(void)
2278 unsigned long end_pfn, shift, phys_base;
2279 unsigned long real_end, i;
2281 setup_page_offset();
2283 /* These build time checkes make sure that the dcache_dirty_cpu()
2284 * page->flags usage will work.
2286 * When a page gets marked as dcache-dirty, we store the
2287 * cpu number starting at bit 32 in the page->flags. Also,
2288 * functions like clear_dcache_dirty_cpu use the cpu mask
2289 * in 13-bit signed-immediate instruction fields.
2293 * Page flags must not reach into upper 32 bits that are used
2294 * for the cpu number
2296 BUILD_BUG_ON(NR_PAGEFLAGS > 32);
2299 * The bit fields placed in the high range must not reach below
2300 * the 32 bit boundary. Otherwise we cannot place the cpu field
2301 * at the 32 bit boundary.
2303 BUILD_BUG_ON(SECTIONS_WIDTH + NODES_WIDTH + ZONES_WIDTH +
2304 ilog2(roundup_pow_of_two(NR_CPUS)) > 32);
2306 BUILD_BUG_ON(NR_CPUS > 4096);
2308 kern_base = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB;
2309 kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
2311 /* Invalidate both kernel TSBs. */
2312 memset(swapper_tsb, 0x40, sizeof(swapper_tsb));
2313 #ifndef CONFIG_DEBUG_PAGEALLOC
2314 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
2317 /* TTE.cv bit on sparc v9 occupies the same position as TTE.mcde
2318 * bit on M7 processor. This is a conflicting usage of the same
2319 * bit. Enabling TTE.cv on M7 would turn on Memory Corruption
2320 * Detection error on all pages and this will lead to problems
2321 * later. Kernel does not run with MCD enabled and hence rest
2322 * of the required steps to fully configure memory corruption
2323 * detection are not taken. We need to ensure TTE.mcde is not
2324 * set on M7 processor. Compute the value of cacheability
2325 * flag for use later taking this into consideration.
2327 switch (sun4v_chip_type) {
2328 case SUN4V_CHIP_SPARC_M7:
2329 case SUN4V_CHIP_SPARC_M8:
2330 case SUN4V_CHIP_SPARC_SN:
2331 page_cache4v_flag = _PAGE_CP_4V;
2334 page_cache4v_flag = _PAGE_CACHE_4V;
2338 if (tlb_type == hypervisor)
2339 sun4v_pgprot_init();
2341 sun4u_pgprot_init();
2343 if (tlb_type == cheetah_plus ||
2344 tlb_type == hypervisor) {
2349 if (tlb_type == hypervisor)
2350 sun4v_patch_tlb_handlers();
2352 /* Find available physical memory...
2354 * Read it twice in order to work around a bug in openfirmware.
2355 * The call to grab this table itself can cause openfirmware to
2356 * allocate memory, which in turn can take away some space from
2357 * the list of available memory. Reading it twice makes sure
2358 * we really do get the final value.
2360 read_obp_translations();
2361 read_obp_memory("reg", &pall[0], &pall_ents);
2362 read_obp_memory("available", &pavail[0], &pavail_ents);
2363 read_obp_memory("available", &pavail[0], &pavail_ents);
2365 phys_base = 0xffffffffffffffffUL;
2366 for (i = 0; i < pavail_ents; i++) {
2367 phys_base = min(phys_base, pavail[i].phys_addr);
2368 memblock_add(pavail[i].phys_addr, pavail[i].reg_size);
2371 memblock_reserve(kern_base, kern_size);
2373 find_ramdisk(phys_base);
2375 if (cmdline_memory_size)
2376 reduce_memory(cmdline_memory_size);
2378 memblock_allow_resize();
2379 memblock_dump_all();
2381 set_bit(0, mmu_context_bmap);
2383 shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
2385 real_end = (unsigned long)_end;
2386 num_kernel_image_mappings = DIV_ROUND_UP(real_end - KERNBASE, 1 << ILOG2_4MB);
2387 printk("Kernel: Using %d locked TLB entries for main kernel image.\n",
2388 num_kernel_image_mappings);
2390 /* Set kernel pgd to upper alias so physical page computations
2393 init_mm.pgd += ((shift) / (sizeof(pgd_t)));
2395 memset(swapper_pg_dir, 0, sizeof(swapper_pg_dir));
2397 inherit_prom_mappings();
2399 /* Ok, we can use our TLB miss and window trap handlers safely. */
2404 prom_build_devicetree();
2405 of_populate_present_mask();
2407 of_fill_in_cpu_data();
2410 if (tlb_type == hypervisor) {
2412 mdesc_populate_present_mask(cpu_all_mask);
2414 mdesc_fill_in_cpu_data(cpu_all_mask);
2416 mdesc_get_page_sizes(cpu_all_mask, &cpu_pgsz_mask);
2418 sun4v_linear_pte_xor_finalize();
2421 sun4v_ktsb_register();
2423 unsigned long impl, ver;
2425 cpu_pgsz_mask = (HV_PGSZ_MASK_8K | HV_PGSZ_MASK_64K |
2426 HV_PGSZ_MASK_512K | HV_PGSZ_MASK_4MB);
2428 __asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver));
2429 impl = ((ver >> 32) & 0xffff);
2430 if (impl == PANTHER_IMPL)
2431 cpu_pgsz_mask |= (HV_PGSZ_MASK_32MB |
2432 HV_PGSZ_MASK_256MB);
2434 sun4u_linear_pte_xor_finalize();
2437 /* Flush the TLBs and the 4M TSB so that the updated linear
2438 * pte XOR settings are realized for all mappings.
2441 #ifndef CONFIG_DEBUG_PAGEALLOC
2442 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
2446 /* Setup bootmem... */
2447 last_valid_pfn = end_pfn = bootmem_init(phys_base);
2449 kernel_physical_mapping_init();
2452 unsigned long max_zone_pfns[MAX_NR_ZONES];
2454 memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
2456 max_zone_pfns[ZONE_NORMAL] = end_pfn;
2458 free_area_init(max_zone_pfns);
2461 printk("Booting Linux...\n");
2464 int page_in_phys_avail(unsigned long paddr)
2470 for (i = 0; i < pavail_ents; i++) {
2471 unsigned long start, end;
2473 start = pavail[i].phys_addr;
2474 end = start + pavail[i].reg_size;
2476 if (paddr >= start && paddr < end)
2479 if (paddr >= kern_base && paddr < (kern_base + kern_size))
2481 #ifdef CONFIG_BLK_DEV_INITRD
2482 if (paddr >= __pa(initrd_start) &&
2483 paddr < __pa(PAGE_ALIGN(initrd_end)))
2490 static void __init register_page_bootmem_info(void)
2495 for_each_online_node(i)
2496 if (NODE_DATA(i)->node_spanned_pages)
2497 register_page_bootmem_info_node(NODE_DATA(i));
2500 void __init mem_init(void)
2502 high_memory = __va(last_valid_pfn << PAGE_SHIFT);
2504 memblock_free_all();
2507 * Must be done after boot memory is put on freelist, because here we
2508 * might set fields in deferred struct pages that have not yet been
2509 * initialized, and memblock_free_all() initializes all the reserved
2510 * deferred pages for us.
2512 register_page_bootmem_info();
2515 * Set up the zero page, mark it reserved, so that page count
2516 * is not manipulated when freeing the page from user ptes.
2518 mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
2519 if (mem_map_zero == NULL) {
2520 prom_printf("paging_init: Cannot alloc zero page.\n");
2523 mark_page_reserved(mem_map_zero);
2526 if (tlb_type == cheetah || tlb_type == cheetah_plus)
2527 cheetah_ecache_flush_init();
2530 void free_initmem(void)
2532 unsigned long addr, initend;
2535 /* If the physical memory maps were trimmed by kernel command
2536 * line options, don't even try freeing this initmem stuff up.
2537 * The kernel image could have been in the trimmed out region
2538 * and if so the freeing below will free invalid page structs.
2540 if (cmdline_memory_size)
2544 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
2546 addr = PAGE_ALIGN((unsigned long)(__init_begin));
2547 initend = (unsigned long)(__init_end) & PAGE_MASK;
2548 for (; addr < initend; addr += PAGE_SIZE) {
2552 ((unsigned long) __va(kern_base)) -
2553 ((unsigned long) KERNBASE));
2554 memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
2557 free_reserved_page(virt_to_page(page));
2561 pgprot_t PAGE_KERNEL __read_mostly;
2562 EXPORT_SYMBOL(PAGE_KERNEL);
2564 pgprot_t PAGE_KERNEL_LOCKED __read_mostly;
2565 pgprot_t PAGE_COPY __read_mostly;
2567 pgprot_t PAGE_SHARED __read_mostly;
2568 EXPORT_SYMBOL(PAGE_SHARED);
2570 unsigned long pg_iobits __read_mostly;
2572 unsigned long _PAGE_IE __read_mostly;
2573 EXPORT_SYMBOL(_PAGE_IE);
2575 unsigned long _PAGE_E __read_mostly;
2576 EXPORT_SYMBOL(_PAGE_E);
2578 unsigned long _PAGE_CACHE __read_mostly;
2579 EXPORT_SYMBOL(_PAGE_CACHE);
2581 #ifdef CONFIG_SPARSEMEM_VMEMMAP
2582 int __meminit vmemmap_populate(unsigned long vstart, unsigned long vend,
2583 int node, struct vmem_altmap *altmap)
2585 unsigned long pte_base;
2587 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2588 _PAGE_CP_4U | _PAGE_CV_4U |
2589 _PAGE_P_4U | _PAGE_W_4U);
2590 if (tlb_type == hypervisor)
2591 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2592 page_cache4v_flag | _PAGE_P_4V | _PAGE_W_4V);
2594 pte_base |= _PAGE_PMD_HUGE;
2596 vstart = vstart & PMD_MASK;
2597 vend = ALIGN(vend, PMD_SIZE);
2598 for (; vstart < vend; vstart += PMD_SIZE) {
2599 pgd_t *pgd = vmemmap_pgd_populate(vstart, node);
2608 p4d = vmemmap_p4d_populate(pgd, vstart, node);
2612 pud = vmemmap_pud_populate(p4d, vstart, node);
2616 pmd = pmd_offset(pud, vstart);
2617 pte = pmd_val(*pmd);
2618 if (!(pte & _PAGE_VALID)) {
2619 void *block = vmemmap_alloc_block(PMD_SIZE, node);
2624 pmd_val(*pmd) = pte_base | __pa(block);
2631 void vmemmap_free(unsigned long start, unsigned long end,
2632 struct vmem_altmap *altmap)
2635 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
2637 /* These are actually filled in at boot time by sun4{u,v}_pgprot_init() */
2638 static pgprot_t protection_map[16] __ro_after_init;
2640 static void prot_init_common(unsigned long page_none,
2641 unsigned long page_shared,
2642 unsigned long page_copy,
2643 unsigned long page_readonly,
2644 unsigned long page_exec_bit)
2646 PAGE_COPY = __pgprot(page_copy);
2647 PAGE_SHARED = __pgprot(page_shared);
2649 protection_map[0x0] = __pgprot(page_none);
2650 protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit);
2651 protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit);
2652 protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit);
2653 protection_map[0x4] = __pgprot(page_readonly);
2654 protection_map[0x5] = __pgprot(page_readonly);
2655 protection_map[0x6] = __pgprot(page_copy);
2656 protection_map[0x7] = __pgprot(page_copy);
2657 protection_map[0x8] = __pgprot(page_none);
2658 protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit);
2659 protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit);
2660 protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit);
2661 protection_map[0xc] = __pgprot(page_readonly);
2662 protection_map[0xd] = __pgprot(page_readonly);
2663 protection_map[0xe] = __pgprot(page_shared);
2664 protection_map[0xf] = __pgprot(page_shared);
2667 static void __init sun4u_pgprot_init(void)
2669 unsigned long page_none, page_shared, page_copy, page_readonly;
2670 unsigned long page_exec_bit;
2673 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2674 _PAGE_CACHE_4U | _PAGE_P_4U |
2675 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2677 PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2678 _PAGE_CACHE_4U | _PAGE_P_4U |
2679 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2680 _PAGE_EXEC_4U | _PAGE_L_4U);
2682 _PAGE_IE = _PAGE_IE_4U;
2683 _PAGE_E = _PAGE_E_4U;
2684 _PAGE_CACHE = _PAGE_CACHE_4U;
2686 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U |
2687 __ACCESS_BITS_4U | _PAGE_E_4U);
2689 #ifdef CONFIG_DEBUG_PAGEALLOC
2690 kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET;
2692 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
2695 kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U |
2696 _PAGE_P_4U | _PAGE_W_4U);
2698 for (i = 1; i < 4; i++)
2699 kern_linear_pte_xor[i] = kern_linear_pte_xor[0];
2701 _PAGE_ALL_SZ_BITS = (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
2702 _PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
2703 _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);
2706 page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U;
2707 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2708 __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U);
2709 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2710 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2711 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2712 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2714 page_exec_bit = _PAGE_EXEC_4U;
2716 prot_init_common(page_none, page_shared, page_copy, page_readonly,
2720 static void __init sun4v_pgprot_init(void)
2722 unsigned long page_none, page_shared, page_copy, page_readonly;
2723 unsigned long page_exec_bit;
2726 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
2727 page_cache4v_flag | _PAGE_P_4V |
2728 __ACCESS_BITS_4V | __DIRTY_BITS_4V |
2730 PAGE_KERNEL_LOCKED = PAGE_KERNEL;
2732 _PAGE_IE = _PAGE_IE_4V;
2733 _PAGE_E = _PAGE_E_4V;
2734 _PAGE_CACHE = page_cache4v_flag;
2736 #ifdef CONFIG_DEBUG_PAGEALLOC
2737 kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET;
2739 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
2742 kern_linear_pte_xor[0] |= (page_cache4v_flag | _PAGE_P_4V |
2745 for (i = 1; i < 4; i++)
2746 kern_linear_pte_xor[i] = kern_linear_pte_xor[0];
2748 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
2749 __ACCESS_BITS_4V | _PAGE_E_4V);
2751 _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
2752 _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
2753 _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
2754 _PAGE_SZ64K_4V | _PAGE_SZ8K_4V);
2756 page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | page_cache4v_flag;
2757 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag |
2758 __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V);
2759 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag |
2760 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2761 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag |
2762 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2764 page_exec_bit = _PAGE_EXEC_4V;
2766 prot_init_common(page_none, page_shared, page_copy, page_readonly,
2770 unsigned long pte_sz_bits(unsigned long sz)
2772 if (tlb_type == hypervisor) {
2776 return _PAGE_SZ8K_4V;
2778 return _PAGE_SZ64K_4V;
2780 return _PAGE_SZ512K_4V;
2781 case 4 * 1024 * 1024:
2782 return _PAGE_SZ4MB_4V;
2788 return _PAGE_SZ8K_4U;
2790 return _PAGE_SZ64K_4U;
2792 return _PAGE_SZ512K_4U;
2793 case 4 * 1024 * 1024:
2794 return _PAGE_SZ4MB_4U;
2799 pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size)
2803 pte_val(pte) = page | pgprot_val(pgprot_noncached(prot));
2804 pte_val(pte) |= (((unsigned long)space) << 32);
2805 pte_val(pte) |= pte_sz_bits(page_size);
2810 static unsigned long kern_large_tte(unsigned long paddr)
2814 val = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2815 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U |
2816 _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U);
2817 if (tlb_type == hypervisor)
2818 val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2819 page_cache4v_flag | _PAGE_P_4V |
2820 _PAGE_EXEC_4V | _PAGE_W_4V);
2825 /* If not locked, zap it. */
2826 void __flush_tlb_all(void)
2828 unsigned long pstate;
2831 __asm__ __volatile__("flushw\n\t"
2832 "rdpr %%pstate, %0\n\t"
2833 "wrpr %0, %1, %%pstate"
2836 if (tlb_type == hypervisor) {
2837 sun4v_mmu_demap_all();
2838 } else if (tlb_type == spitfire) {
2839 for (i = 0; i < 64; i++) {
2840 /* Spitfire Errata #32 workaround */
2841 /* NOTE: Always runs on spitfire, so no
2842 * cheetah+ page size encodings.
2844 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
2848 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2850 if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) {
2851 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2854 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
2855 spitfire_put_dtlb_data(i, 0x0UL);
2858 /* Spitfire Errata #32 workaround */
2859 /* NOTE: Always runs on spitfire, so no
2860 * cheetah+ page size encodings.
2862 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
2866 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2868 if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) {
2869 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2872 : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
2873 spitfire_put_itlb_data(i, 0x0UL);
2876 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
2877 cheetah_flush_dtlb_all();
2878 cheetah_flush_itlb_all();
2880 __asm__ __volatile__("wrpr %0, 0, %%pstate"
2884 pte_t *pte_alloc_one_kernel(struct mm_struct *mm)
2886 struct page *page = alloc_page(GFP_KERNEL | __GFP_ZERO);
2890 pte = (pte_t *) page_address(page);
2895 pgtable_t pte_alloc_one(struct mm_struct *mm)
2897 struct page *page = alloc_page(GFP_KERNEL | __GFP_ZERO);
2900 if (!pgtable_pte_page_ctor(page)) {
2904 return (pte_t *) page_address(page);
2907 void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
2909 free_page((unsigned long)pte);
2912 static void __pte_free(pgtable_t pte)
2914 struct page *page = virt_to_page(pte);
2916 pgtable_pte_page_dtor(page);
2920 void pte_free(struct mm_struct *mm, pgtable_t pte)
2925 void pgtable_free(void *table, bool is_page)
2930 kmem_cache_free(pgtable_cache, table);
2933 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
2934 void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr,
2937 unsigned long pte, flags;
2938 struct mm_struct *mm;
2941 if (!pmd_large(entry) || !pmd_young(entry))
2944 pte = pmd_val(entry);
2946 /* Don't insert a non-valid PMD into the TSB, we'll deadlock. */
2947 if (!(pte & _PAGE_VALID))
2950 /* We are fabricating 8MB pages using 4MB real hw pages. */
2951 pte |= (addr & (1UL << REAL_HPAGE_SHIFT));
2955 spin_lock_irqsave(&mm->context.lock, flags);
2957 if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL)
2958 __update_mmu_tsb_insert(mm, MM_TSB_HUGE, REAL_HPAGE_SHIFT,
2961 spin_unlock_irqrestore(&mm->context.lock, flags);
2963 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
2965 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
2966 static void context_reload(void *__data)
2968 struct mm_struct *mm = __data;
2970 if (mm == current->mm)
2971 load_secondary_context(mm);
2974 void hugetlb_setup(struct pt_regs *regs)
2976 struct mm_struct *mm = current->mm;
2977 struct tsb_config *tp;
2979 if (faulthandler_disabled() || !mm) {
2980 const struct exception_table_entry *entry;
2982 entry = search_exception_tables(regs->tpc);
2984 regs->tpc = entry->fixup;
2985 regs->tnpc = regs->tpc + 4;
2988 pr_alert("Unexpected HugeTLB setup in atomic context.\n");
2989 die_if_kernel("HugeTSB in atomic", regs);
2992 tp = &mm->context.tsb_block[MM_TSB_HUGE];
2993 if (likely(tp->tsb == NULL))
2994 tsb_grow(mm, MM_TSB_HUGE, 0);
2996 tsb_context_switch(mm);
2999 /* On UltraSPARC-III+ and later, configure the second half of
3000 * the Data-TLB for huge pages.
3002 if (tlb_type == cheetah_plus) {
3003 bool need_context_reload = false;
3006 spin_lock_irq(&ctx_alloc_lock);
3007 ctx = mm->context.sparc64_ctx_val;
3008 ctx &= ~CTX_PGSZ_MASK;
3009 ctx |= CTX_PGSZ_BASE << CTX_PGSZ0_SHIFT;
3010 ctx |= CTX_PGSZ_HUGE << CTX_PGSZ1_SHIFT;
3012 if (ctx != mm->context.sparc64_ctx_val) {
3013 /* When changing the page size fields, we
3014 * must perform a context flush so that no
3015 * stale entries match. This flush must
3016 * occur with the original context register
3019 do_flush_tlb_mm(mm);
3021 /* Reload the context register of all processors
3022 * also executing in this address space.
3024 mm->context.sparc64_ctx_val = ctx;
3025 need_context_reload = true;
3027 spin_unlock_irq(&ctx_alloc_lock);
3029 if (need_context_reload)
3030 on_each_cpu(context_reload, mm, 0);
3035 static struct resource code_resource = {
3036 .name = "Kernel code",
3037 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM
3040 static struct resource data_resource = {
3041 .name = "Kernel data",
3042 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM
3045 static struct resource bss_resource = {
3046 .name = "Kernel bss",
3047 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM
3050 static inline resource_size_t compute_kern_paddr(void *addr)
3052 return (resource_size_t) (addr - KERNBASE + kern_base);
3055 static void __init kernel_lds_init(void)
3057 code_resource.start = compute_kern_paddr(_text);
3058 code_resource.end = compute_kern_paddr(_etext - 1);
3059 data_resource.start = compute_kern_paddr(_etext);
3060 data_resource.end = compute_kern_paddr(_edata - 1);
3061 bss_resource.start = compute_kern_paddr(__bss_start);
3062 bss_resource.end = compute_kern_paddr(_end - 1);
3065 static int __init report_memory(void)
3068 struct resource *res;
3072 for (i = 0; i < pavail_ents; i++) {
3073 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
3076 pr_warn("Failed to allocate source.\n");
3080 res->name = "System RAM";
3081 res->start = pavail[i].phys_addr;
3082 res->end = pavail[i].phys_addr + pavail[i].reg_size - 1;
3083 res->flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM;
3085 if (insert_resource(&iomem_resource, res) < 0) {
3086 pr_warn("Resource insertion failed.\n");
3090 insert_resource(res, &code_resource);
3091 insert_resource(res, &data_resource);
3092 insert_resource(res, &bss_resource);
3097 arch_initcall(report_memory);
3100 #define do_flush_tlb_kernel_range smp_flush_tlb_kernel_range
3102 #define do_flush_tlb_kernel_range __flush_tlb_kernel_range
3105 void flush_tlb_kernel_range(unsigned long start, unsigned long end)
3107 if (start < HI_OBP_ADDRESS && end > LOW_OBP_ADDRESS) {
3108 if (start < LOW_OBP_ADDRESS) {
3109 flush_tsb_kernel_range(start, LOW_OBP_ADDRESS);
3110 do_flush_tlb_kernel_range(start, LOW_OBP_ADDRESS);
3112 if (end > HI_OBP_ADDRESS) {
3113 flush_tsb_kernel_range(HI_OBP_ADDRESS, end);
3114 do_flush_tlb_kernel_range(HI_OBP_ADDRESS, end);
3117 flush_tsb_kernel_range(start, end);
3118 do_flush_tlb_kernel_range(start, end);
3122 void copy_user_highpage(struct page *to, struct page *from,
3123 unsigned long vaddr, struct vm_area_struct *vma)
3127 vfrom = kmap_atomic(from);
3128 vto = kmap_atomic(to);
3129 copy_user_page(vto, vfrom, vaddr, to);
3131 kunmap_atomic(vfrom);
3133 /* If this page has ADI enabled, copy over any ADI tags
3136 if (vma->vm_flags & VM_SPARC_ADI) {
3137 unsigned long pfrom, pto, i, adi_tag;
3139 pfrom = page_to_phys(from);
3140 pto = page_to_phys(to);
3142 for (i = pfrom; i < (pfrom + PAGE_SIZE); i += adi_blksize()) {
3143 asm volatile("ldxa [%1] %2, %0\n\t"
3145 : "r" (i), "i" (ASI_MCD_REAL));
3146 asm volatile("stxa %0, [%1] %2\n\t"
3148 : "r" (adi_tag), "r" (pto),
3149 "i" (ASI_MCD_REAL));
3150 pto += adi_blksize();
3152 asm volatile("membar #Sync\n\t");
3155 EXPORT_SYMBOL(copy_user_highpage);
3157 void copy_highpage(struct page *to, struct page *from)
3161 vfrom = kmap_atomic(from);
3162 vto = kmap_atomic(to);
3163 copy_page(vto, vfrom);
3165 kunmap_atomic(vfrom);
3167 /* If this platform is ADI enabled, copy any ADI tags
3170 if (adi_capable()) {
3171 unsigned long pfrom, pto, i, adi_tag;
3173 pfrom = page_to_phys(from);
3174 pto = page_to_phys(to);
3176 for (i = pfrom; i < (pfrom + PAGE_SIZE); i += adi_blksize()) {
3177 asm volatile("ldxa [%1] %2, %0\n\t"
3179 : "r" (i), "i" (ASI_MCD_REAL));
3180 asm volatile("stxa %0, [%1] %2\n\t"
3182 : "r" (adi_tag), "r" (pto),
3183 "i" (ASI_MCD_REAL));
3184 pto += adi_blksize();
3186 asm volatile("membar #Sync\n\t");
3189 EXPORT_SYMBOL(copy_highpage);
3191 pgprot_t vm_get_page_prot(unsigned long vm_flags)
3193 unsigned long prot = pgprot_val(protection_map[vm_flags &
3194 (VM_READ|VM_WRITE|VM_EXEC|VM_SHARED)]);
3196 if (vm_flags & VM_SPARC_ADI)
3197 prot |= _PAGE_MCD_4V;
3199 return __pgprot(prot);
3201 EXPORT_SYMBOL(vm_get_page_prot);