2 * hypersparc.S: High speed Hypersparc mmu/cache operations.
4 * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
7 #include <asm/ptrace.h>
9 #include <asm/asm-offsets.h>
12 #include <asm/pgtsrmmu.h>
13 #include <linux/init.h>
18 .globl hypersparc_flush_cache_all, hypersparc_flush_cache_mm
19 .globl hypersparc_flush_cache_range, hypersparc_flush_cache_page
20 .globl hypersparc_flush_page_to_ram
21 .globl hypersparc_flush_page_for_dma, hypersparc_flush_sig_insns
22 .globl hypersparc_flush_tlb_all, hypersparc_flush_tlb_mm
23 .globl hypersparc_flush_tlb_range, hypersparc_flush_tlb_page
25 hypersparc_flush_cache_all:
26 WINDOW_FLUSH(%g4, %g5)
27 sethi %hi(vac_cache_size), %g4
28 ld [%g4 + %lo(vac_cache_size)], %g5
29 sethi %hi(vac_line_size), %g1
30 ld [%g1 + %lo(vac_line_size)], %g2
32 subcc %g5, %g2, %g5 ! hyper_flush_unconditional_combined
34 sta %g0, [%g5] ASI_M_FLUSH_CTX
36 sta %g0, [%g0] ASI_M_FLUSH_IWHOLE ! hyper_flush_whole_icache
38 /* We expand the window flush to get maximum performance. */
39 hypersparc_flush_cache_mm:
41 ld [%o0 + AOFF_mm_context], %g1
43 be hypersparc_flush_cache_mm_out
45 WINDOW_FLUSH(%g4, %g5)
47 sethi %hi(vac_line_size), %g1
48 ld [%g1 + %lo(vac_line_size)], %o1
49 sethi %hi(vac_cache_size), %g2
50 ld [%g2 + %lo(vac_cache_size)], %o0
61 subcc %o0, %o5, %o0 ! hyper_flush_cache_user
62 sta %g0, [%o0 + %g0] ASI_M_FLUSH_USER
63 sta %g0, [%o0 + %o1] ASI_M_FLUSH_USER
64 sta %g0, [%o0 + %g1] ASI_M_FLUSH_USER
65 sta %g0, [%o0 + %g2] ASI_M_FLUSH_USER
66 sta %g0, [%o0 + %g3] ASI_M_FLUSH_USER
67 sta %g0, [%o0 + %g4] ASI_M_FLUSH_USER
68 sta %g0, [%o0 + %g5] ASI_M_FLUSH_USER
70 sta %g0, [%o0 + %o4] ASI_M_FLUSH_USER
71 hypersparc_flush_cache_mm_out:
75 /* The things we do for performance... */
76 hypersparc_flush_cache_range:
77 ld [%o0 + VMA_VM_MM], %o0
79 ld [%o0 + AOFF_mm_context], %g1
81 be hypersparc_flush_cache_range_out
83 WINDOW_FLUSH(%g4, %g5)
85 sethi %hi(vac_line_size), %g1
86 ld [%g1 + %lo(vac_line_size)], %o4
87 sethi %hi(vac_cache_size), %g2
88 ld [%g2 + %lo(vac_cache_size)], %o3
90 /* Here comes the fun part... */
91 add %o2, (PAGE_SIZE - 1), %o2
92 andn %o1, (PAGE_SIZE - 1), %o1
94 andn %o2, (PAGE_SIZE - 1), %o2
106 /* Flush entire user space, believe it or not this is quicker
107 * than page at a time flushings for range > (cache_size<<2).
111 sta %g0, [%o3 + %g0] ASI_M_FLUSH_USER
112 sta %g0, [%o3 + %o4] ASI_M_FLUSH_USER
113 sta %g0, [%o3 + %o5] ASI_M_FLUSH_USER
114 sta %g0, [%o3 + %g1] ASI_M_FLUSH_USER
115 sta %g0, [%o3 + %g2] ASI_M_FLUSH_USER
116 sta %g0, [%o3 + %g3] ASI_M_FLUSH_USER
117 sta %g0, [%o3 + %g4] ASI_M_FLUSH_USER
119 sta %g0, [%o3 + %g5] ASI_M_FLUSH_USER
123 /* Below our threshold, flush one page at a time. */
125 ld [%o0 + AOFF_mm_context], %o0
126 mov SRMMU_CTX_REG, %g7
127 lda [%g7] ASI_M_MMUREGS, %o3
128 sta %o0, [%g7] ASI_M_MMUREGS
129 add %o2, -PAGE_SIZE, %o0
132 lda [%g7] ASI_M_FLUSH_PROBE, %g7
139 sta %g0, [%o2 + %g0] ASI_M_FLUSH_PAGE
140 sta %g0, [%o2 + %o4] ASI_M_FLUSH_PAGE
141 sta %g0, [%o2 + %o5] ASI_M_FLUSH_PAGE
142 sta %g0, [%o2 + %g1] ASI_M_FLUSH_PAGE
143 sta %g0, [%o2 + %g2] ASI_M_FLUSH_PAGE
144 sta %g0, [%o2 + %g3] ASI_M_FLUSH_PAGE
145 andcc %o2, 0xffc, %g0
146 sta %g0, [%o2 + %g4] ASI_M_FLUSH_PAGE
148 sta %g0, [%o2 + %g5] ASI_M_FLUSH_PAGE
152 add %o2, -PAGE_SIZE, %o0
153 mov SRMMU_FAULT_STATUS, %g5
154 lda [%g5] ASI_M_MMUREGS, %g0
155 mov SRMMU_CTX_REG, %g7
156 sta %o3, [%g7] ASI_M_MMUREGS
157 hypersparc_flush_cache_range_out:
161 /* HyperSparc requires a valid mapping where we are about to flush
162 * in order to check for a physical tag match during the flush.
164 /* Verified, my ass... */
165 hypersparc_flush_cache_page:
166 ld [%o0 + VMA_VM_MM], %o0
167 ld [%o0 + AOFF_mm_context], %g2
170 be hypersparc_flush_cache_page_out
172 WINDOW_FLUSH(%g4, %g5)
174 sethi %hi(vac_line_size), %g1
175 ld [%g1 + %lo(vac_line_size)], %o4
176 mov SRMMU_CTX_REG, %o3
177 andn %o1, (PAGE_SIZE - 1), %o1
178 lda [%o3] ASI_M_MMUREGS, %o2
179 sta %g2, [%o3] ASI_M_MMUREGS
181 lda [%o5] ASI_M_FLUSH_PROBE, %g1
185 sub %o1, -PAGE_SIZE, %o1
196 sta %g0, [%o1 + %g0] ASI_M_FLUSH_PAGE
197 sta %g0, [%o1 + %o4] ASI_M_FLUSH_PAGE
198 sta %g0, [%o1 + %o5] ASI_M_FLUSH_PAGE
199 sta %g0, [%o1 + %g1] ASI_M_FLUSH_PAGE
200 sta %g0, [%o1 + %g2] ASI_M_FLUSH_PAGE
201 sta %g0, [%o1 + %g3] ASI_M_FLUSH_PAGE
202 andcc %o1, 0xffc, %g0
203 sta %g0, [%o1 + %g4] ASI_M_FLUSH_PAGE
205 sta %g0, [%o1 + %g5] ASI_M_FLUSH_PAGE
207 mov SRMMU_FAULT_STATUS, %g7
208 mov SRMMU_CTX_REG, %g4
209 lda [%g7] ASI_M_MMUREGS, %g0
210 sta %o2, [%g4] ASI_M_MMUREGS
211 hypersparc_flush_cache_page_out:
215 hypersparc_flush_sig_insns:
220 /* HyperSparc is copy-back. */
221 hypersparc_flush_page_to_ram:
222 sethi %hi(vac_line_size), %g1
223 ld [%g1 + %lo(vac_line_size)], %o4
224 andn %o0, (PAGE_SIZE - 1), %o0
227 lda [%g7] ASI_M_FLUSH_PROBE, %g5
233 sub %o0, -PAGE_SIZE, %o0
241 sta %g0, [%o0 + %g0] ASI_M_FLUSH_PAGE
242 sta %g0, [%o0 + %o4] ASI_M_FLUSH_PAGE
243 sta %g0, [%o0 + %o5] ASI_M_FLUSH_PAGE
244 sta %g0, [%o0 + %g1] ASI_M_FLUSH_PAGE
245 sta %g0, [%o0 + %g2] ASI_M_FLUSH_PAGE
246 sta %g0, [%o0 + %g3] ASI_M_FLUSH_PAGE
247 andcc %o0, 0xffc, %g0
248 sta %g0, [%o0 + %g4] ASI_M_FLUSH_PAGE
250 sta %g0, [%o0 + %g5] ASI_M_FLUSH_PAGE
252 mov SRMMU_FAULT_STATUS, %g1
254 lda [%g1] ASI_M_MMUREGS, %g0
256 /* HyperSparc is IO cache coherent. */
257 hypersparc_flush_page_for_dma:
261 /* It was noted that at boot time a TLB flush all in a delay slot
262 * can deliver an illegal instruction to the processor if the timing
265 hypersparc_flush_tlb_all:
267 sta %g0, [%g1] ASI_M_FLUSH_PROBE
271 hypersparc_flush_tlb_mm:
272 mov SRMMU_CTX_REG, %g1
273 ld [%o0 + AOFF_mm_context], %o1
274 lda [%g1] ASI_M_MMUREGS, %g5
277 be hypersparc_flush_tlb_mm_out
280 sta %o1, [%g1] ASI_M_MMUREGS
281 sta %g0, [%g2] ASI_M_FLUSH_PROBE
282 hypersparc_flush_tlb_mm_out:
284 sta %g5, [%g1] ASI_M_MMUREGS
286 hypersparc_flush_tlb_range:
287 ld [%o0 + VMA_VM_MM], %o0
288 mov SRMMU_CTX_REG, %g1
289 ld [%o0 + AOFF_mm_context], %o3
290 lda [%g1] ASI_M_MMUREGS, %g5
293 be hypersparc_flush_tlb_range_out
295 sethi %hi(~((1 << SRMMU_PGDIR_SHIFT) - 1)), %o4
296 sta %o3, [%g1] ASI_M_MMUREGS
299 sta %g0, [%o1] ASI_M_FLUSH_PROBE
304 sta %g0, [%o1] ASI_M_FLUSH_PROBE
305 hypersparc_flush_tlb_range_out:
307 sta %g5, [%g1] ASI_M_MMUREGS
309 hypersparc_flush_tlb_page:
310 ld [%o0 + VMA_VM_MM], %o0
311 mov SRMMU_CTX_REG, %g1
312 ld [%o0 + AOFF_mm_context], %o3
313 andn %o1, (PAGE_SIZE - 1), %o1
316 be hypersparc_flush_tlb_page_out
318 lda [%g1] ASI_M_MMUREGS, %g5
319 sta %o3, [%g1] ASI_M_MMUREGS
320 sta %g0, [%o1] ASI_M_FLUSH_PROBE
321 hypersparc_flush_tlb_page_out:
323 sta %g5, [%g1] ASI_M_MMUREGS
327 /* High speed page clear/copy. */
328 hypersparc_bzero_1page:
329 /* NOTE: This routine has to be shorter than 40insns --jj */
340 stda %g0, [%o0 + %g0] ASI_M_BFILL
341 stda %g0, [%o0 + %g2] ASI_M_BFILL
342 stda %g0, [%o0 + %g3] ASI_M_BFILL
343 stda %g0, [%o0 + %g4] ASI_M_BFILL
344 stda %g0, [%o0 + %g5] ASI_M_BFILL
345 stda %g0, [%o0 + %g7] ASI_M_BFILL
346 stda %g0, [%o0 + %o2] ASI_M_BFILL
347 stda %g0, [%o0 + %o3] ASI_M_BFILL
355 hypersparc_copy_1page:
356 /* NOTE: This routine has to be shorter than 70insns --jj */
357 sub %o1, %o0, %o2 ! difference
360 sta %o0, [%o0 + %o2] ASI_M_BCOPY
362 sta %o0, [%o0 + %o2] ASI_M_BCOPY
364 sta %o0, [%o0 + %o2] ASI_M_BCOPY
366 sta %o0, [%o0 + %o2] ASI_M_BCOPY
368 sta %o0, [%o0 + %o2] ASI_M_BCOPY
370 sta %o0, [%o0 + %o2] ASI_M_BCOPY
372 sta %o0, [%o0 + %o2] ASI_M_BCOPY
374 sta %o0, [%o0 + %o2] ASI_M_BCOPY
382 .globl hypersparc_setup_blockops
383 hypersparc_setup_blockops:
384 sethi %hi(bzero_1page), %o0
385 or %o0, %lo(bzero_1page), %o0
386 sethi %hi(hypersparc_bzero_1page), %o1
387 or %o1, %lo(hypersparc_bzero_1page), %o1
388 sethi %hi(hypersparc_copy_1page), %o2
389 or %o2, %lo(hypersparc_copy_1page), %o2
398 sethi %hi(__copy_1page), %o0
399 or %o0, %lo(__copy_1page), %o0
400 sethi %hi(hypersparc_setup_blockops), %o2
401 or %o2, %lo(hypersparc_setup_blockops), %o2
410 sta %g0, [%g0] ASI_M_FLUSH_IWHOLE