arch/sparc/kernel/rtrap_64.S

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * rtrap.S: Preparing for return from trap on Sparc V9.
   4  *
   5  * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
   6  * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
   7  */
   8
   9
  10 #include <asm/asi.h>
  11 #include <asm/pstate.h>
  12 #include <asm/ptrace.h>
  13 #include <asm/spitfire.h>
  14 #include <asm/head.h>
  15 #include <asm/visasm.h>
  16 #include <asm/processor.h>
  17
  18 #ifdef CONFIG_CONTEXT_TRACKING
  19 # define SCHEDULE_USER schedule_user
  20 #else
  21 # define SCHEDULE_USER schedule
  22 #endif
  23
  24                 .text
  25                 .align                  32
  26 __handle_preemption:
  27                 call                    SCHEDULE_USER
  28                  wrpr                   %g0, RTRAP_PSTATE, %pstate
  29                 ba,pt                   %xcc, __handle_preemption_continue
  30                  wrpr                   %g0, RTRAP_PSTATE_IRQOFF, %pstate
  31
  32 __handle_user_windows:
  33                 add                     %sp, PTREGS_OFF, %o0
  34                 call                    fault_in_user_windows
  35                  wrpr                   %g0, RTRAP_PSTATE, %pstate
  36                 ba,pt                   %xcc, __handle_preemption_continue
  37                  wrpr                   %g0, RTRAP_PSTATE_IRQOFF, %pstate
  38
  39 __handle_userfpu:
  40                 rd                      %fprs, %l5
  41                 andcc                   %l5, FPRS_FEF, %g0
  42                 sethi                   %hi(TSTATE_PEF), %o0
  43                 be,a,pn                 %icc, __handle_userfpu_continue
  44                  andn                   %l1, %o0, %l1
  45                 ba,a,pt                 %xcc, __handle_userfpu_continue
  46
  47 __handle_signal:
  48                 mov                     %l5, %o1
  49                 add                     %sp, PTREGS_OFF, %o0
  50                 mov                     %l0, %o2
  51                 call                    do_notify_resume
  52                  wrpr                   %g0, RTRAP_PSTATE, %pstate
  53                 wrpr                    %g0, RTRAP_PSTATE_IRQOFF, %pstate
  54
  55                 /* Signal delivery can modify pt_regs tstate, so we must
  56                  * reload it.
  57                  */
  58                 ldx                     [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
  59                 sethi                   %hi(0xf << 20), %l4
  60                 and                     %l1, %l4, %l4
  61                 ba,pt                   %xcc, __handle_preemption_continue
  62                  andn                   %l1, %l4, %l1
  63
  64                 /* When returning from a NMI (%pil==15) interrupt we want to
  65                  * avoid running softirqs, doing IRQ tracing, preempting, etc.
  66                  */
  67                 .globl                  rtrap_nmi
  68 rtrap_nmi:      ldx                     [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
  69                 sethi                   %hi(0xf << 20), %l4
  70                 and                     %l1, %l4, %l4
  71                 andn                    %l1, %l4, %l1
  72                 srl                     %l4, 20, %l4
  73                 ba,pt                   %xcc, rtrap_no_irq_enable
  74                 nop
  75                 /* Do not actually set the %pil here.  We will do that
  76                  * below after we clear PSTATE_IE in the %pstate register.
  77                  * If we re-enable interrupts here, we can recurse down
  78                  * the hardirq stack potentially endlessly, causing a
  79                  * stack overflow.
  80                  */
  81
  82                 .align                  64
  83                 .globl                  rtrap_irq, rtrap, irqsz_patchme, rtrap_xcall
  84 rtrap_irq:
  85 rtrap:
  86                 /* mm/ultra.S:xcall_report_regs KNOWS about this load. */
  87                 ldx                     [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
  88 rtrap_xcall:
  89                 sethi                   %hi(0xf << 20), %l4
  90                 and                     %l1, %l4, %l4
  91                 andn                    %l1, %l4, %l1
  92                 srl                     %l4, 20, %l4
  93 #ifdef CONFIG_TRACE_IRQFLAGS
  94                 brnz,pn                 %l4, rtrap_no_irq_enable
  95                  nop
  96                 call                    trace_hardirqs_on
  97                  nop
  98                 /* Do not actually set the %pil here.  We will do that
  99                  * below after we clear PSTATE_IE in the %pstate register.
 100                  * If we re-enable interrupts here, we can recurse down
 101                  * the hardirq stack potentially endlessly, causing a
 102                  * stack overflow.
 103                  *
 104                  * It is tempting to put this test and trace_hardirqs_on
 105                  * call at the 'rt_continue' label, but that will not work
 106                  * as that path hits unconditionally and we do not want to
 107                  * execute this in NMI return paths, for example.
 108                  */
 109 #endif
 110 rtrap_no_irq_enable:
 111                 andcc                   %l1, TSTATE_PRIV, %l3
 112                 bne,pn                  %icc, to_kernel
 113                  nop
 114
 115                 /* We must hold IRQs off and atomically test schedule+signal
 116                  * state, then hold them off all the way back to userspace.
 117                  * If we are returning to kernel, none of this matters.  Note
 118                  * that we are disabling interrupts via PSTATE_IE, not using
 119                  * %pil.
 120                  *
 121                  * If we do not do this, there is a window where we would do
 122                  * the tests, later the signal/resched event arrives but we do
 123                  * not process it since we are still in kernel mode.  It would
 124                  * take until the next local IRQ before the signal/resched
 125                  * event would be handled.
 126                  *
 127                  * This also means that if we have to deal with user
 128                  * windows, we have to redo all of these sched+signal checks
 129                  * with IRQs disabled.
 130                  */
 131 to_user:        wrpr                    %g0, RTRAP_PSTATE_IRQOFF, %pstate
 132                 wrpr                    0, %pil
 133 __handle_preemption_continue:
 134                 ldx                     [%g6 + TI_FLAGS], %l0
 135                 sethi                   %hi(_TIF_USER_WORK_MASK), %o0
 136                 or                      %o0, %lo(_TIF_USER_WORK_MASK), %o0
 137                 andcc                   %l0, %o0, %g0
 138                 sethi                   %hi(TSTATE_PEF), %o0
 139                 be,pt                   %xcc, user_nowork
 140                  andcc                  %l1, %o0, %g0
 141                 andcc                   %l0, _TIF_NEED_RESCHED, %g0
 142                 bne,pn                  %xcc, __handle_preemption
 143                  andcc                  %l0, _TIF_DO_NOTIFY_RESUME_MASK, %g0
 144                 bne,pn                  %xcc, __handle_signal
 145                  ldub                   [%g6 + TI_WSAVED], %o2
 146                 brnz,pn                 %o2, __handle_user_windows
 147                  nop
 148                 sethi                   %hi(TSTATE_PEF), %o0
 149                 andcc                   %l1, %o0, %g0
 150
 151                 /* This fpdepth clear is necessary for non-syscall rtraps only */
 152 user_nowork:
 153                 bne,pn                  %xcc, __handle_userfpu
 154                  stb                    %g0, [%g6 + TI_FPDEPTH]
 155 __handle_userfpu_continue:
 156
 157 rt_continue:    ldx                     [%sp + PTREGS_OFF + PT_V9_G1], %g1
 158                 ldx                     [%sp + PTREGS_OFF + PT_V9_G2], %g2
 159
 160                 ldx                     [%sp + PTREGS_OFF + PT_V9_G3], %g3
 161                 ldx                     [%sp + PTREGS_OFF + PT_V9_G4], %g4
 162                 ldx                     [%sp + PTREGS_OFF + PT_V9_G5], %g5
 163                 brz,pt                  %l3, 1f
 164                 mov                     %g6, %l2
 165
 166                 /* Must do this before thread reg is clobbered below.  */
 167                 LOAD_PER_CPU_BASE(%g5, %g6, %i0, %i1, %i2)
 168 1:
 169                 ldx                     [%sp + PTREGS_OFF + PT_V9_G6], %g6
 170                 ldx                     [%sp + PTREGS_OFF + PT_V9_G7], %g7
 171
 172                 /* Normal globals are restored, go to trap globals.  */
 173 661:            wrpr                    %g0, RTRAP_PSTATE_AG_IRQOFF, %pstate
 174                 nop
 175                 .section                .sun4v_2insn_patch, "ax"
 176                 .word                   661b
 177                 wrpr                    %g0, RTRAP_PSTATE_IRQOFF, %pstate
 178                 SET_GL(1)
 179                 .previous
 180
 181                 mov                     %l2, %g6
 182
 183                 ldx                     [%sp + PTREGS_OFF + PT_V9_I0], %i0
 184                 ldx                     [%sp + PTREGS_OFF + PT_V9_I1], %i1
 185
 186                 ldx                     [%sp + PTREGS_OFF + PT_V9_I2], %i2
 187                 ldx                     [%sp + PTREGS_OFF + PT_V9_I3], %i3
 188                 ldx                     [%sp + PTREGS_OFF + PT_V9_I4], %i4
 189                 ldx                     [%sp + PTREGS_OFF + PT_V9_I5], %i5
 190                 ldx                     [%sp + PTREGS_OFF + PT_V9_I6], %i6
 191                 ldx                     [%sp + PTREGS_OFF + PT_V9_I7], %i7
 192                 ldx                     [%sp + PTREGS_OFF + PT_V9_TPC], %l2
 193                 ldx                     [%sp + PTREGS_OFF + PT_V9_TNPC], %o2
 194
 195                 ld                      [%sp + PTREGS_OFF + PT_V9_Y], %o3
 196                 wr                      %o3, %g0, %y
 197                 wrpr                    %l4, 0x0, %pil
 198                 wrpr                    %g0, 0x1, %tl
 199                 andn                    %l1, TSTATE_SYSCALL, %l1
 200                 wrpr                    %l1, %g0, %tstate
 201                 wrpr                    %l2, %g0, %tpc
 202                 wrpr                    %o2, %g0, %tnpc
 203
 204                 brnz,pn                 %l3, kern_rtt
 205                  mov                    PRIMARY_CONTEXT, %l7
 206
 207 661:            ldxa                    [%l7 + %l7] ASI_DMMU, %l0
 208                 .section                .sun4v_1insn_patch, "ax"
 209                 .word                   661b
 210                 ldxa                    [%l7 + %l7] ASI_MMU, %l0
 211                 .previous
 212
 213                 sethi                   %hi(sparc64_kern_pri_nuc_bits), %l1
 214                 ldx                     [%l1 + %lo(sparc64_kern_pri_nuc_bits)], %l1
 215                 or                      %l0, %l1, %l0
 216
 217 661:            stxa                    %l0, [%l7] ASI_DMMU
 218                 .section                .sun4v_1insn_patch, "ax"
 219                 .word                   661b
 220                 stxa                    %l0, [%l7] ASI_MMU
 221                 .previous
 222
 223                 sethi                   %hi(KERNBASE), %l7
 224                 flush                   %l7
 225                 rdpr                    %wstate, %l1
 226                 rdpr                    %otherwin, %l2
 227                 srl                     %l1, 3, %l1
 228
 229 661:            wrpr                    %l2, %g0, %canrestore
 230                 .section                .fast_win_ctrl_1insn_patch, "ax"
 231                 .word                   661b
 232                 .word                   0x89880000      ! normalw
 233                 .previous
 234
 235                 wrpr                    %l1, %g0, %wstate
 236                 brnz,pt                 %l2, user_rtt_restore
 237 661:             wrpr                   %g0, %g0, %otherwin
 238                 .section                .fast_win_ctrl_1insn_patch, "ax"
 239                 .word                   661b
 240                  nop
 241                 .previous
 242
 243                 ldx                     [%g6 + TI_FLAGS], %g3
 244                 wr                      %g0, ASI_AIUP, %asi
 245                 rdpr                    %cwp, %g1
 246                 andcc                   %g3, _TIF_32BIT, %g0
 247                 sub                     %g1, 1, %g1
 248                 bne,pt                  %xcc, user_rtt_fill_32bit
 249                  wrpr                   %g1, %cwp
 250                 ba,a,pt                 %xcc, user_rtt_fill_64bit
 251                  nop
 252
 253 user_rtt_fill_fixup_dax:
 254                 ba,pt   %xcc, user_rtt_fill_fixup_common
 255                  mov    1, %g3
 256
 257 user_rtt_fill_fixup_mna:
 258                 ba,pt   %xcc, user_rtt_fill_fixup_common
 259                  mov    2, %g3
 260
 261 user_rtt_fill_fixup:
 262                 ba,pt   %xcc, user_rtt_fill_fixup_common
 263                  clr    %g3
 264
 265 user_rtt_pre_restore:
 266                 add                     %g1, 1, %g1
 267                 wrpr                    %g1, 0x0, %cwp
 268
 269 user_rtt_restore:
 270                 restore
 271                 rdpr                    %canrestore, %g1
 272                 wrpr                    %g1, 0x0, %cleanwin
 273                 retry
 274                 nop
 275
 276 kern_rtt:       rdpr                    %canrestore, %g1
 277                 brz,pn                  %g1, kern_rtt_fill
 278                  nop
 279 kern_rtt_restore:
 280                 stw                     %g0, [%sp + PTREGS_OFF + PT_V9_MAGIC]
 281                 restore
 282                 retry
 283
 284 to_kernel:
 285 #ifdef CONFIG_PREEMPT
 286                 ldsw                    [%g6 + TI_PRE_COUNT], %l5
 287                 brnz                    %l5, kern_fpucheck
 288                  ldx                    [%g6 + TI_FLAGS], %l5
 289                 andcc                   %l5, _TIF_NEED_RESCHED, %g0
 290                 be,pt                   %xcc, kern_fpucheck
 291                  nop
 292                 cmp                     %l4, 0
 293                 bne,pn                  %xcc, kern_fpucheck
 294                  nop
 295                 call                    preempt_schedule_irq
 296                  nop
 297                 ba,pt                   %xcc, rtrap
 298 #endif
 299 kern_fpucheck:  ldub                    [%g6 + TI_FPDEPTH], %l5
 300                 brz,pt                  %l5, rt_continue
 301                  srl                    %l5, 1, %o0
 302                 add                     %g6, TI_FPSAVED, %l6
 303                 ldub                    [%l6 + %o0], %l2
 304                 sub                     %l5, 2, %l5
 305
 306                 add                     %g6, TI_GSR, %o1
 307                 andcc                   %l2, (FPRS_FEF|FPRS_DU), %g0
 308                 be,pt                   %icc, 2f
 309                  and                    %l2, FPRS_DL, %l6
 310                 andcc                   %l2, FPRS_FEF, %g0
 311                 be,pn                   %icc, 5f
 312                  sll                    %o0, 3, %o5
 313                 rd                      %fprs, %g1
 314
 315                 wr                      %g1, FPRS_FEF, %fprs
 316                 ldx                     [%o1 + %o5], %g1
 317                 add                     %g6, TI_XFSR, %o1
 318                 sll                     %o0, 8, %o2
 319                 add                     %g6, TI_FPREGS, %o3
 320                 brz,pn                  %l6, 1f
 321                  add                    %g6, TI_FPREGS+0x40, %o4
 322
 323                 membar                  #Sync
 324                 ldda                    [%o3 + %o2] ASI_BLK_P, %f0
 325                 ldda                    [%o4 + %o2] ASI_BLK_P, %f16
 326                 membar                  #Sync
 327 1:              andcc                   %l2, FPRS_DU, %g0
 328                 be,pn                   %icc, 1f
 329                  wr                     %g1, 0, %gsr
 330                 add                     %o2, 0x80, %o2
 331                 membar                  #Sync
 332                 ldda                    [%o3 + %o2] ASI_BLK_P, %f32
 333                 ldda                    [%o4 + %o2] ASI_BLK_P, %f48
 334 1:              membar                  #Sync
 335                 ldx                     [%o1 + %o5], %fsr
 336 2:              stb                     %l5, [%g6 + TI_FPDEPTH]
 337                 ba,pt                   %xcc, rt_continue
 338                  nop
 339 5:              wr                      %g0, FPRS_FEF, %fprs
 340                 sll                     %o0, 8, %o2
 341
 342                 add                     %g6, TI_FPREGS+0x80, %o3
 343                 add                     %g6, TI_FPREGS+0xc0, %o4
 344                 membar                  #Sync
 345                 ldda                    [%o3 + %o2] ASI_BLK_P, %f32
 346                 ldda                    [%o4 + %o2] ASI_BLK_P, %f48
 347                 membar                  #Sync
 348                 wr                      %g0, FPRS_DU, %fprs
 349                 ba,pt                   %xcc, rt_continue
 350                  stb                    %l5, [%g6 + TI_FPDEPTH]