arch/sparc/kernel/perf_event.c

   1 /* Performance event support for sparc64.
   2  *
   3  * Copyright (C) 2009, 2010 David S. Miller <davem@davemloft.net>
   4  *
   5  * This code is based almost entirely upon the x86 perf event
   6  * code, which is:
   7  *
   8  *  Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
   9  *  Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
  10  *  Copyright (C) 2009 Jaswinder Singh Rajput
  11  *  Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
  12  *  Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra
  13  */
  14
  15 #include <linux/perf_event.h>
  16 #include <linux/kprobes.h>
  17 #include <linux/ftrace.h>
  18 #include <linux/kernel.h>
  19 #include <linux/kdebug.h>
  20 #include <linux/mutex.h>
  21
  22 #include <asm/stacktrace.h>
  23 #include <asm/cpudata.h>
  24 #include <linux/uaccess.h>
  25 #include <linux/atomic.h>
  26 #include <asm/nmi.h>
  27 #include <asm/pcr.h>
  28 #include <asm/cacheflush.h>
  29
  30 #include "kernel.h"
  31 #include "kstack.h"
  32
  33 /* Two classes of sparc64 chips currently exist.  All of which have
  34  * 32-bit counters which can generate overflow interrupts on the
  35  * transition from 0xffffffff to 0.
  36  *
  37  * All chips upto and including SPARC-T3 have two performance
  38  * counters.  The two 32-bit counters are accessed in one go using a
  39  * single 64-bit register.
  40  *
  41  * On these older chips both counters are controlled using a single
  42  * control register.  The only way to stop all sampling is to clear
  43  * all of the context (user, supervisor, hypervisor) sampling enable
  44  * bits.  But these bits apply to both counters, thus the two counters
  45  * can't be enabled/disabled individually.
  46  *
  47  * Furthermore, the control register on these older chips have two
  48  * event fields, one for each of the two counters.  It's thus nearly
  49  * impossible to have one counter going while keeping the other one
  50  * stopped.  Therefore it is possible to get overflow interrupts for
  51  * counters not currently "in use" and that condition must be checked
  52  * in the overflow interrupt handler.
  53  *
  54  * So we use a hack, in that we program inactive counters with the
  55  * "sw_count0" and "sw_count1" events.  These count how many times
  56  * the instruction "sethi %hi(0xfc000), %g0" is executed.  It's an
  57  * unusual way to encode a NOP and therefore will not trigger in
  58  * normal code.
  59  *
  60  * Starting with SPARC-T4 we have one control register per counter.
  61  * And the counters are stored in individual registers.  The registers
  62  * for the counters are 64-bit but only a 32-bit counter is
  63  * implemented.  The event selections on SPARC-T4 lack any
  64  * restrictions, therefore we can elide all of the complicated
  65  * conflict resolution code we have for SPARC-T3 and earlier chips.
  66  */
  67
  68 #define MAX_HWEVENTS                    4
  69 #define MAX_PCRS                        4
  70 #define MAX_PERIOD                      ((1UL << 32) - 1)
  71
  72 #define PIC_UPPER_INDEX                 0
  73 #define PIC_LOWER_INDEX                 1
  74 #define PIC_NO_INDEX                    -1
  75
  76 struct cpu_hw_events {
  77         /* Number of events currently scheduled onto this cpu.
  78          * This tells how many entries in the arrays below
  79          * are valid.
  80          */
  81         int                     n_events;
  82
  83         /* Number of new events added since the last hw_perf_disable().
  84          * This works because the perf event layer always adds new
  85          * events inside of a perf_{disable,enable}() sequence.
  86          */
  87         int                     n_added;
  88
  89         /* Array of events current scheduled on this cpu.  */
  90         struct perf_event       *event[MAX_HWEVENTS];
  91
  92         /* Array of encoded longs, specifying the %pcr register
  93          * encoding and the mask of PIC counters this even can
  94          * be scheduled on.  See perf_event_encode() et al.
  95          */
  96         unsigned long           events[MAX_HWEVENTS];
  97
  98         /* The current counter index assigned to an event.  When the
  99          * event hasn't been programmed into the cpu yet, this will
 100          * hold PIC_NO_INDEX.  The event->hw.idx value tells us where
 101          * we ought to schedule the event.
 102          */
 103         int                     current_idx[MAX_HWEVENTS];
 104
 105         /* Software copy of %pcr register(s) on this cpu.  */
 106         u64                     pcr[MAX_HWEVENTS];
 107
 108         /* Enabled/disable state.  */
 109         int                     enabled;
 110
 111         unsigned int            txn_flags;
 112 };
 113 static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { .enabled = 1, };
 114
 115 /* An event map describes the characteristics of a performance
 116  * counter event.  In particular it gives the encoding as well as
 117  * a mask telling which counters the event can be measured on.
 118  *
 119  * The mask is unused on SPARC-T4 and later.
 120  */
 121 struct perf_event_map {
 122         u16     encoding;
 123         u8      pic_mask;
 124 #define PIC_NONE        0x00
 125 #define PIC_UPPER       0x01
 126 #define PIC_LOWER       0x02
 127 };
 128
 129 /* Encode a perf_event_map entry into a long.  */
 130 static unsigned long perf_event_encode(const struct perf_event_map *pmap)
 131 {
 132         return ((unsigned long) pmap->encoding << 16) | pmap->pic_mask;
 133 }
 134
 135 static u8 perf_event_get_msk(unsigned long val)
 136 {
 137         return val & 0xff;
 138 }
 139
 140 static u64 perf_event_get_enc(unsigned long val)
 141 {
 142         return val >> 16;
 143 }
 144
 145 #define C(x) PERF_COUNT_HW_CACHE_##x
 146
 147 #define CACHE_OP_UNSUPPORTED    0xfffe
 148 #define CACHE_OP_NONSENSE       0xffff
 149
 150 typedef struct perf_event_map cache_map_t
 151                                 [PERF_COUNT_HW_CACHE_MAX]
 152                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 153                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
 154
 155 struct sparc_pmu {
 156         const struct perf_event_map     *(*event_map)(int);
 157         const cache_map_t               *cache_map;
 158         int                             max_events;
 159         u32                             (*read_pmc)(int);
 160         void                            (*write_pmc)(int, u64);
 161         int                             upper_shift;
 162         int                             lower_shift;
 163         int                             event_mask;
 164         int                             user_bit;
 165         int                             priv_bit;
 166         int                             hv_bit;
 167         int                             irq_bit;
 168         int                             upper_nop;
 169         int                             lower_nop;
 170         unsigned int                    flags;
 171 #define SPARC_PMU_ALL_EXCLUDES_SAME     0x00000001
 172 #define SPARC_PMU_HAS_CONFLICTS         0x00000002
 173         int                             max_hw_events;
 174         int                             num_pcrs;
 175         int                             num_pic_regs;
 176 };
 177
 178 static u32 sparc_default_read_pmc(int idx)
 179 {
 180         u64 val;
 181
 182         val = pcr_ops->read_pic(0);
 183         if (idx == PIC_UPPER_INDEX)
 184                 val >>= 32;
 185
 186         return val & 0xffffffff;
 187 }
 188
 189 static void sparc_default_write_pmc(int idx, u64 val)
 190 {
 191         u64 shift, mask, pic;
 192
 193         shift = 0;
 194         if (idx == PIC_UPPER_INDEX)
 195                 shift = 32;
 196
 197         mask = ((u64) 0xffffffff) << shift;
 198         val <<= shift;
 199
 200         pic = pcr_ops->read_pic(0);
 201         pic &= ~mask;
 202         pic |= val;
 203         pcr_ops->write_pic(0, pic);
 204 }
 205
 206 static const struct perf_event_map ultra3_perfmon_event_map[] = {
 207         [PERF_COUNT_HW_CPU_CYCLES] = { 0x0000, PIC_UPPER | PIC_LOWER },
 208         [PERF_COUNT_HW_INSTRUCTIONS] = { 0x0001, PIC_UPPER | PIC_LOWER },
 209         [PERF_COUNT_HW_CACHE_REFERENCES] = { 0x0009, PIC_LOWER },
 210         [PERF_COUNT_HW_CACHE_MISSES] = { 0x0009, PIC_UPPER },
 211 };
 212
 213 static const struct perf_event_map *ultra3_event_map(int event_id)
 214 {
 215         return &ultra3_perfmon_event_map[event_id];
 216 }
 217
 218 static const cache_map_t ultra3_cache_map = {
 219 [C(L1D)] = {
 220         [C(OP_READ)] = {
 221                 [C(RESULT_ACCESS)] = { 0x09, PIC_LOWER, },
 222                 [C(RESULT_MISS)] = { 0x09, PIC_UPPER, },
 223         },
 224         [C(OP_WRITE)] = {
 225                 [C(RESULT_ACCESS)] = { 0x0a, PIC_LOWER },
 226                 [C(RESULT_MISS)] = { 0x0a, PIC_UPPER },
 227         },
 228         [C(OP_PREFETCH)] = {
 229                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 230                 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
 231         },
 232 },
 233 [C(L1I)] = {
 234         [C(OP_READ)] = {
 235                 [C(RESULT_ACCESS)] = { 0x09, PIC_LOWER, },
 236                 [C(RESULT_MISS)] = { 0x09, PIC_UPPER, },
 237         },
 238         [ C(OP_WRITE) ] = {
 239                 [ C(RESULT_ACCESS) ] = { CACHE_OP_NONSENSE },
 240                 [ C(RESULT_MISS)   ] = { CACHE_OP_NONSENSE },
 241         },
 242         [ C(OP_PREFETCH) ] = {
 243                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 244                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 245         },
 246 },
 247 [C(LL)] = {
 248         [C(OP_READ)] = {
 249                 [C(RESULT_ACCESS)] = { 0x0c, PIC_LOWER, },
 250                 [C(RESULT_MISS)] = { 0x0c, PIC_UPPER, },
 251         },
 252         [C(OP_WRITE)] = {
 253                 [C(RESULT_ACCESS)] = { 0x0c, PIC_LOWER },
 254                 [C(RESULT_MISS)] = { 0x0c, PIC_UPPER },
 255         },
 256         [C(OP_PREFETCH)] = {
 257                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 258                 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
 259         },
 260 },
 261 [C(DTLB)] = {
 262         [C(OP_READ)] = {
 263                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 264                 [C(RESULT_MISS)] = { 0x12, PIC_UPPER, },
 265         },
 266         [ C(OP_WRITE) ] = {
 267                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 268                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 269         },
 270         [ C(OP_PREFETCH) ] = {
 271                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 272                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 273         },
 274 },
 275 [C(ITLB)] = {
 276         [C(OP_READ)] = {
 277                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 278                 [C(RESULT_MISS)] = { 0x11, PIC_UPPER, },
 279         },
 280         [ C(OP_WRITE) ] = {
 281                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 282                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 283         },
 284         [ C(OP_PREFETCH) ] = {
 285                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 286                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 287         },
 288 },
 289 [C(BPU)] = {
 290         [C(OP_READ)] = {
 291                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 292                 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
 293         },
 294         [ C(OP_WRITE) ] = {
 295                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 296                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 297         },
 298         [ C(OP_PREFETCH) ] = {
 299                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 300                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 301         },
 302 },
 303 [C(NODE)] = {
 304         [C(OP_READ)] = {
 305                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 306                 [C(RESULT_MISS)  ] = { CACHE_OP_UNSUPPORTED },
 307         },
 308         [ C(OP_WRITE) ] = {
 309                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 310                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 311         },
 312         [ C(OP_PREFETCH) ] = {
 313                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 314                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 315         },
 316 },
 317 };
 318
 319 static const struct sparc_pmu ultra3_pmu = {
 320         .event_map      = ultra3_event_map,
 321         .cache_map      = &ultra3_cache_map,
 322         .max_events     = ARRAY_SIZE(ultra3_perfmon_event_map),
 323         .read_pmc       = sparc_default_read_pmc,
 324         .write_pmc      = sparc_default_write_pmc,
 325         .upper_shift    = 11,
 326         .lower_shift    = 4,
 327         .event_mask     = 0x3f,
 328         .user_bit       = PCR_UTRACE,
 329         .priv_bit       = PCR_STRACE,
 330         .upper_nop      = 0x1c,
 331         .lower_nop      = 0x14,
 332         .flags          = (SPARC_PMU_ALL_EXCLUDES_SAME |
 333                            SPARC_PMU_HAS_CONFLICTS),
 334         .max_hw_events  = 2,
 335         .num_pcrs       = 1,
 336         .num_pic_regs   = 1,
 337 };
 338
 339 /* Niagara1 is very limited.  The upper PIC is hard-locked to count
 340  * only instructions, so it is free running which creates all kinds of
 341  * problems.  Some hardware designs make one wonder if the creator
 342  * even looked at how this stuff gets used by software.
 343  */
 344 static const struct perf_event_map niagara1_perfmon_event_map[] = {
 345         [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, PIC_UPPER },
 346         [PERF_COUNT_HW_INSTRUCTIONS] = { 0x00, PIC_UPPER },
 347         [PERF_COUNT_HW_CACHE_REFERENCES] = { 0, PIC_NONE },
 348         [PERF_COUNT_HW_CACHE_MISSES] = { 0x03, PIC_LOWER },
 349 };
 350
 351 static const struct perf_event_map *niagara1_event_map(int event_id)
 352 {
 353         return &niagara1_perfmon_event_map[event_id];
 354 }
 355
 356 static const cache_map_t niagara1_cache_map = {
 357 [C(L1D)] = {
 358         [C(OP_READ)] = {
 359                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 360                 [C(RESULT_MISS)] = { 0x03, PIC_LOWER, },
 361         },
 362         [C(OP_WRITE)] = {
 363                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 364                 [C(RESULT_MISS)] = { 0x03, PIC_LOWER, },
 365         },
 366         [C(OP_PREFETCH)] = {
 367                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 368                 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
 369         },
 370 },
 371 [C(L1I)] = {
 372         [C(OP_READ)] = {
 373                 [C(RESULT_ACCESS)] = { 0x00, PIC_UPPER },
 374                 [C(RESULT_MISS)] = { 0x02, PIC_LOWER, },
 375         },
 376         [ C(OP_WRITE) ] = {
 377                 [ C(RESULT_ACCESS) ] = { CACHE_OP_NONSENSE },
 378                 [ C(RESULT_MISS)   ] = { CACHE_OP_NONSENSE },
 379         },
 380         [ C(OP_PREFETCH) ] = {
 381                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 382                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 383         },
 384 },
 385 [C(LL)] = {
 386         [C(OP_READ)] = {
 387                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 388                 [C(RESULT_MISS)] = { 0x07, PIC_LOWER, },
 389         },
 390         [C(OP_WRITE)] = {
 391                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 392                 [C(RESULT_MISS)] = { 0x07, PIC_LOWER, },
 393         },
 394         [C(OP_PREFETCH)] = {
 395                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 396                 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
 397         },
 398 },
 399 [C(DTLB)] = {
 400         [C(OP_READ)] = {
 401                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 402                 [C(RESULT_MISS)] = { 0x05, PIC_LOWER, },
 403         },
 404         [ C(OP_WRITE) ] = {
 405                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 406                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 407         },
 408         [ C(OP_PREFETCH) ] = {
 409                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 410                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 411         },
 412 },
 413 [C(ITLB)] = {
 414         [C(OP_READ)] = {
 415                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 416                 [C(RESULT_MISS)] = { 0x04, PIC_LOWER, },
 417         },
 418         [ C(OP_WRITE) ] = {
 419                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 420                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 421         },
 422         [ C(OP_PREFETCH) ] = {
 423                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 424                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 425         },
 426 },
 427 [C(BPU)] = {
 428         [C(OP_READ)] = {
 429                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 430                 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
 431         },
 432         [ C(OP_WRITE) ] = {
 433                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 434                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 435         },
 436         [ C(OP_PREFETCH) ] = {
 437                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 438                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 439         },
 440 },
 441 [C(NODE)] = {
 442         [C(OP_READ)] = {
 443                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 444                 [C(RESULT_MISS)  ] = { CACHE_OP_UNSUPPORTED },
 445         },
 446         [ C(OP_WRITE) ] = {
 447                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 448                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 449         },
 450         [ C(OP_PREFETCH) ] = {
 451                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 452                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 453         },
 454 },
 455 };
 456
 457 static const struct sparc_pmu niagara1_pmu = {
 458         .event_map      = niagara1_event_map,
 459         .cache_map      = &niagara1_cache_map,
 460         .max_events     = ARRAY_SIZE(niagara1_perfmon_event_map),
 461         .read_pmc       = sparc_default_read_pmc,
 462         .write_pmc      = sparc_default_write_pmc,
 463         .upper_shift    = 0,
 464         .lower_shift    = 4,
 465         .event_mask     = 0x7,
 466         .user_bit       = PCR_UTRACE,
 467         .priv_bit       = PCR_STRACE,
 468         .upper_nop      = 0x0,
 469         .lower_nop      = 0x0,
 470         .flags          = (SPARC_PMU_ALL_EXCLUDES_SAME |
 471                            SPARC_PMU_HAS_CONFLICTS),
 472         .max_hw_events  = 2,
 473         .num_pcrs       = 1,
 474         .num_pic_regs   = 1,
 475 };
 476
 477 static const struct perf_event_map niagara2_perfmon_event_map[] = {
 478         [PERF_COUNT_HW_CPU_CYCLES] = { 0x02ff, PIC_UPPER | PIC_LOWER },
 479         [PERF_COUNT_HW_INSTRUCTIONS] = { 0x02ff, PIC_UPPER | PIC_LOWER },
 480         [PERF_COUNT_HW_CACHE_REFERENCES] = { 0x0208, PIC_UPPER | PIC_LOWER },
 481         [PERF_COUNT_HW_CACHE_MISSES] = { 0x0302, PIC_UPPER | PIC_LOWER },
 482         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x0201, PIC_UPPER | PIC_LOWER },
 483         [PERF_COUNT_HW_BRANCH_MISSES] = { 0x0202, PIC_UPPER | PIC_LOWER },
 484 };
 485
 486 static const struct perf_event_map *niagara2_event_map(int event_id)
 487 {
 488         return &niagara2_perfmon_event_map[event_id];
 489 }
 490
 491 static const cache_map_t niagara2_cache_map = {
 492 [C(L1D)] = {
 493         [C(OP_READ)] = {
 494                 [C(RESULT_ACCESS)] = { 0x0208, PIC_UPPER | PIC_LOWER, },
 495                 [C(RESULT_MISS)] = { 0x0302, PIC_UPPER | PIC_LOWER, },
 496         },
 497         [C(OP_WRITE)] = {
 498                 [C(RESULT_ACCESS)] = { 0x0210, PIC_UPPER | PIC_LOWER, },
 499                 [C(RESULT_MISS)] = { 0x0302, PIC_UPPER | PIC_LOWER, },
 500         },
 501         [C(OP_PREFETCH)] = {
 502                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 503                 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
 504         },
 505 },
 506 [C(L1I)] = {
 507         [C(OP_READ)] = {
 508                 [C(RESULT_ACCESS)] = { 0x02ff, PIC_UPPER | PIC_LOWER, },
 509                 [C(RESULT_MISS)] = { 0x0301, PIC_UPPER | PIC_LOWER, },
 510         },
 511         [ C(OP_WRITE) ] = {
 512                 [ C(RESULT_ACCESS) ] = { CACHE_OP_NONSENSE },
 513                 [ C(RESULT_MISS)   ] = { CACHE_OP_NONSENSE },
 514         },
 515         [ C(OP_PREFETCH) ] = {
 516                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 517                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 518         },
 519 },
 520 [C(LL)] = {
 521         [C(OP_READ)] = {
 522                 [C(RESULT_ACCESS)] = { 0x0208, PIC_UPPER | PIC_LOWER, },
 523                 [C(RESULT_MISS)] = { 0x0330, PIC_UPPER | PIC_LOWER, },
 524         },
 525         [C(OP_WRITE)] = {
 526                 [C(RESULT_ACCESS)] = { 0x0210, PIC_UPPER | PIC_LOWER, },
 527                 [C(RESULT_MISS)] = { 0x0320, PIC_UPPER | PIC_LOWER, },
 528         },
 529         [C(OP_PREFETCH)] = {
 530                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 531                 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
 532         },
 533 },
 534 [C(DTLB)] = {
 535         [C(OP_READ)] = {
 536                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 537                 [C(RESULT_MISS)] = { 0x0b08, PIC_UPPER | PIC_LOWER, },
 538         },
 539         [ C(OP_WRITE) ] = {
 540                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 541                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 542         },
 543         [ C(OP_PREFETCH) ] = {
 544                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 545                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 546         },
 547 },
 548 [C(ITLB)] = {
 549         [C(OP_READ)] = {
 550                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 551                 [C(RESULT_MISS)] = { 0xb04, PIC_UPPER | PIC_LOWER, },
 552         },
 553         [ C(OP_WRITE) ] = {
 554                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 555                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 556         },
 557         [ C(OP_PREFETCH) ] = {
 558                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 559                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 560         },
 561 },
 562 [C(BPU)] = {
 563         [C(OP_READ)] = {
 564                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 565                 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
 566         },
 567         [ C(OP_WRITE) ] = {
 568                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 569                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 570         },
 571         [ C(OP_PREFETCH) ] = {
 572                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 573                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 574         },
 575 },
 576 [C(NODE)] = {
 577         [C(OP_READ)] = {
 578                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 579                 [C(RESULT_MISS)  ] = { CACHE_OP_UNSUPPORTED },
 580         },
 581         [ C(OP_WRITE) ] = {
 582                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 583                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 584         },
 585         [ C(OP_PREFETCH) ] = {
 586                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 587                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 588         },
 589 },
 590 };
 591
 592 static const struct sparc_pmu niagara2_pmu = {
 593         .event_map      = niagara2_event_map,
 594         .cache_map      = &niagara2_cache_map,
 595         .max_events     = ARRAY_SIZE(niagara2_perfmon_event_map),
 596         .read_pmc       = sparc_default_read_pmc,
 597         .write_pmc      = sparc_default_write_pmc,
 598         .upper_shift    = 19,
 599         .lower_shift    = 6,
 600         .event_mask     = 0xfff,
 601         .user_bit       = PCR_UTRACE,
 602         .priv_bit       = PCR_STRACE,
 603         .hv_bit         = PCR_N2_HTRACE,
 604         .irq_bit        = 0x30,
 605         .upper_nop      = 0x220,
 606         .lower_nop      = 0x220,
 607         .flags          = (SPARC_PMU_ALL_EXCLUDES_SAME |
 608                            SPARC_PMU_HAS_CONFLICTS),
 609         .max_hw_events  = 2,
 610         .num_pcrs       = 1,
 611         .num_pic_regs   = 1,
 612 };
 613
 614 static const struct perf_event_map niagara4_perfmon_event_map[] = {
 615         [PERF_COUNT_HW_CPU_CYCLES] = { (26 << 6) },
 616         [PERF_COUNT_HW_INSTRUCTIONS] = { (3 << 6) | 0x3f },
 617         [PERF_COUNT_HW_CACHE_REFERENCES] = { (3 << 6) | 0x04 },
 618         [PERF_COUNT_HW_CACHE_MISSES] = { (16 << 6) | 0x07 },
 619         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { (4 << 6) | 0x01 },
 620         [PERF_COUNT_HW_BRANCH_MISSES] = { (25 << 6) | 0x0f },
 621 };
 622
 623 static const struct perf_event_map *niagara4_event_map(int event_id)
 624 {
 625         return &niagara4_perfmon_event_map[event_id];
 626 }
 627
 628 static const cache_map_t niagara4_cache_map = {
 629 [C(L1D)] = {
 630         [C(OP_READ)] = {
 631                 [C(RESULT_ACCESS)] = { (3 << 6) | 0x04 },
 632                 [C(RESULT_MISS)] = { (16 << 6) | 0x07 },
 633         },
 634         [C(OP_WRITE)] = {
 635                 [C(RESULT_ACCESS)] = { (3 << 6) | 0x08 },
 636                 [C(RESULT_MISS)] = { (16 << 6) | 0x07 },
 637         },
 638         [C(OP_PREFETCH)] = {
 639                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 640                 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
 641         },
 642 },
 643 [C(L1I)] = {
 644         [C(OP_READ)] = {
 645                 [C(RESULT_ACCESS)] = { (3 << 6) | 0x3f },
 646                 [C(RESULT_MISS)] = { (11 << 6) | 0x03 },
 647         },
 648         [ C(OP_WRITE) ] = {
 649                 [ C(RESULT_ACCESS) ] = { CACHE_OP_NONSENSE },
 650                 [ C(RESULT_MISS)   ] = { CACHE_OP_NONSENSE },
 651         },
 652         [ C(OP_PREFETCH) ] = {
 653                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 654                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 655         },
 656 },
 657 [C(LL)] = {
 658         [C(OP_READ)] = {
 659                 [C(RESULT_ACCESS)] = { (3 << 6) | 0x04 },
 660                 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
 661         },
 662         [C(OP_WRITE)] = {
 663                 [C(RESULT_ACCESS)] = { (3 << 6) | 0x08 },
 664                 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
 665         },
 666         [C(OP_PREFETCH)] = {
 667                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 668                 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
 669         },
 670 },
 671 [C(DTLB)] = {
 672         [C(OP_READ)] = {
 673                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 674                 [C(RESULT_MISS)] = { (17 << 6) | 0x3f },
 675         },
 676         [ C(OP_WRITE) ] = {
 677                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 678                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 679         },
 680         [ C(OP_PREFETCH) ] = {
 681                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 682                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 683         },
 684 },
 685 [C(ITLB)] = {
 686         [C(OP_READ)] = {
 687                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 688                 [C(RESULT_MISS)] = { (6 << 6) | 0x3f },
 689         },
 690         [ C(OP_WRITE) ] = {
 691                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 692                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 693         },
 694         [ C(OP_PREFETCH) ] = {
 695                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 696                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 697         },
 698 },
 699 [C(BPU)] = {
 700         [C(OP_READ)] = {
 701                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 702                 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
 703         },
 704         [ C(OP_WRITE) ] = {
 705                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 706                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 707         },
 708         [ C(OP_PREFETCH) ] = {
 709                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 710                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 711         },
 712 },
 713 [C(NODE)] = {
 714         [C(OP_READ)] = {
 715                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 716                 [C(RESULT_MISS)  ] = { CACHE_OP_UNSUPPORTED },
 717         },
 718         [ C(OP_WRITE) ] = {
 719                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 720                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 721         },
 722         [ C(OP_PREFETCH) ] = {
 723                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 724                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 725         },
 726 },
 727 };
 728
 729 static u32 sparc_vt_read_pmc(int idx)
 730 {
 731         u64 val = pcr_ops->read_pic(idx);
 732
 733         return val & 0xffffffff;
 734 }
 735
 736 static void sparc_vt_write_pmc(int idx, u64 val)
 737 {
 738         u64 pcr;
 739
 740         pcr = pcr_ops->read_pcr(idx);
 741         /* ensure ov and ntc are reset */
 742         pcr &= ~(PCR_N4_OV | PCR_N4_NTC);
 743
 744         pcr_ops->write_pic(idx, val & 0xffffffff);
 745
 746         pcr_ops->write_pcr(idx, pcr);
 747 }
 748
 749 static const struct sparc_pmu niagara4_pmu = {
 750         .event_map      = niagara4_event_map,
 751         .cache_map      = &niagara4_cache_map,
 752         .max_events     = ARRAY_SIZE(niagara4_perfmon_event_map),
 753         .read_pmc       = sparc_vt_read_pmc,
 754         .write_pmc      = sparc_vt_write_pmc,
 755         .upper_shift    = 5,
 756         .lower_shift    = 5,
 757         .event_mask     = 0x7ff,
 758         .user_bit       = PCR_N4_UTRACE,
 759         .priv_bit       = PCR_N4_STRACE,
 760
 761         /* We explicitly don't support hypervisor tracing.  The T4
 762          * generates the overflow event for precise events via a trap
 763          * which will not be generated (ie. it's completely lost) if
 764          * we happen to be in the hypervisor when the event triggers.
 765          * Essentially, the overflow event reporting is completely
 766          * unusable when you have hypervisor mode tracing enabled.
 767          */
 768         .hv_bit         = 0,
 769
 770         .irq_bit        = PCR_N4_TOE,
 771         .upper_nop      = 0,
 772         .lower_nop      = 0,
 773         .flags          = 0,
 774         .max_hw_events  = 4,
 775         .num_pcrs       = 4,
 776         .num_pic_regs   = 4,
 777 };
 778
 779 static const struct sparc_pmu sparc_m7_pmu = {
 780         .event_map      = niagara4_event_map,
 781         .cache_map      = &niagara4_cache_map,
 782         .max_events     = ARRAY_SIZE(niagara4_perfmon_event_map),
 783         .read_pmc       = sparc_vt_read_pmc,
 784         .write_pmc      = sparc_vt_write_pmc,
 785         .upper_shift    = 5,
 786         .lower_shift    = 5,
 787         .event_mask     = 0x7ff,
 788         .user_bit       = PCR_N4_UTRACE,
 789         .priv_bit       = PCR_N4_STRACE,
 790
 791         /* We explicitly don't support hypervisor tracing. */
 792         .hv_bit         = 0,
 793
 794         .irq_bit        = PCR_N4_TOE,
 795         .upper_nop      = 0,
 796         .lower_nop      = 0,
 797         .flags          = 0,
 798         .max_hw_events  = 4,
 799         .num_pcrs       = 4,
 800         .num_pic_regs   = 4,
 801 };
 802 static const struct sparc_pmu *sparc_pmu __read_mostly;
 803
 804 static u64 event_encoding(u64 event_id, int idx)
 805 {
 806         if (idx == PIC_UPPER_INDEX)
 807                 event_id <<= sparc_pmu->upper_shift;
 808         else
 809                 event_id <<= sparc_pmu->lower_shift;
 810         return event_id;
 811 }
 812
 813 static u64 mask_for_index(int idx)
 814 {
 815         return event_encoding(sparc_pmu->event_mask, idx);
 816 }
 817
 818 static u64 nop_for_index(int idx)
 819 {
 820         return event_encoding(idx == PIC_UPPER_INDEX ?
 821                               sparc_pmu->upper_nop :
 822                               sparc_pmu->lower_nop, idx);
 823 }
 824
 825 static inline void sparc_pmu_enable_event(struct cpu_hw_events *cpuc, struct hw_perf_event *hwc, int idx)
 826 {
 827         u64 enc, val, mask = mask_for_index(idx);
 828         int pcr_index = 0;
 829
 830         if (sparc_pmu->num_pcrs > 1)
 831                 pcr_index = idx;
 832
 833         enc = perf_event_get_enc(cpuc->events[idx]);
 834
 835         val = cpuc->pcr[pcr_index];
 836         val &= ~mask;
 837         val |= event_encoding(enc, idx);
 838         cpuc->pcr[pcr_index] = val;
 839
 840         pcr_ops->write_pcr(pcr_index, cpuc->pcr[pcr_index]);
 841 }
 842
 843 static inline void sparc_pmu_disable_event(struct cpu_hw_events *cpuc, struct hw_perf_event *hwc, int idx)
 844 {
 845         u64 mask = mask_for_index(idx);
 846         u64 nop = nop_for_index(idx);
 847         int pcr_index = 0;
 848         u64 val;
 849
 850         if (sparc_pmu->num_pcrs > 1)
 851                 pcr_index = idx;
 852
 853         val = cpuc->pcr[pcr_index];
 854         val &= ~mask;
 855         val |= nop;
 856         cpuc->pcr[pcr_index] = val;
 857
 858         pcr_ops->write_pcr(pcr_index, cpuc->pcr[pcr_index]);
 859 }
 860
 861 static u64 sparc_perf_event_update(struct perf_event *event,
 862                                    struct hw_perf_event *hwc, int idx)
 863 {
 864         int shift = 64 - 32;
 865         u64 prev_raw_count, new_raw_count;
 866         s64 delta;
 867
 868 again:
 869         prev_raw_count = local64_read(&hwc->prev_count);
 870         new_raw_count = sparc_pmu->read_pmc(idx);
 871
 872         if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
 873                              new_raw_count) != prev_raw_count)
 874                 goto again;
 875
 876         delta = (new_raw_count << shift) - (prev_raw_count << shift);
 877         delta >>= shift;
 878
 879         local64_add(delta, &event->count);
 880         local64_sub(delta, &hwc->period_left);
 881
 882         return new_raw_count;
 883 }
 884
 885 static int sparc_perf_event_set_period(struct perf_event *event,
 886                                        struct hw_perf_event *hwc, int idx)
 887 {
 888         s64 left = local64_read(&hwc->period_left);
 889         s64 period = hwc->sample_period;
 890         int ret = 0;
 891
 892         /* The period may have been changed by PERF_EVENT_IOC_PERIOD */
 893         if (unlikely(period != hwc->last_period))
 894                 left = period - (hwc->last_period - left);
 895
 896         if (unlikely(left <= -period)) {
 897                 left = period;
 898                 local64_set(&hwc->period_left, left);
 899                 hwc->last_period = period;
 900                 ret = 1;
 901         }
 902
 903         if (unlikely(left <= 0)) {
 904                 left += period;
 905                 local64_set(&hwc->period_left, left);
 906                 hwc->last_period = period;
 907                 ret = 1;
 908         }
 909         if (left > MAX_PERIOD)
 910                 left = MAX_PERIOD;
 911
 912         local64_set(&hwc->prev_count, (u64)-left);
 913
 914         sparc_pmu->write_pmc(idx, (u64)(-left) & 0xffffffff);
 915
 916         perf_event_update_userpage(event);
 917
 918         return ret;
 919 }
 920
 921 static void read_in_all_counters(struct cpu_hw_events *cpuc)
 922 {
 923         int i;
 924
 925         for (i = 0; i < cpuc->n_events; i++) {
 926                 struct perf_event *cp = cpuc->event[i];
 927
 928                 if (cpuc->current_idx[i] != PIC_NO_INDEX &&
 929                     cpuc->current_idx[i] != cp->hw.idx) {
 930                         sparc_perf_event_update(cp, &cp->hw,
 931                                                 cpuc->current_idx[i]);
 932                         cpuc->current_idx[i] = PIC_NO_INDEX;
 933                         if (cp->hw.state & PERF_HES_STOPPED)
 934                                 cp->hw.state |= PERF_HES_ARCH;
 935                 }
 936         }
 937 }
 938
 939 /* On this PMU all PICs are programmed using a single PCR.  Calculate
 940  * the combined control register value.
 941  *
 942  * For such chips we require that all of the events have the same
 943  * configuration, so just fetch the settings from the first entry.
 944  */
 945 static void calculate_single_pcr(struct cpu_hw_events *cpuc)
 946 {
 947         int i;
 948
 949         if (!cpuc->n_added)
 950                 goto out;
 951
 952         /* Assign to counters all unassigned events.  */
 953         for (i = 0; i < cpuc->n_events; i++) {
 954                 struct perf_event *cp = cpuc->event[i];
 955                 struct hw_perf_event *hwc = &cp->hw;
 956                 int idx = hwc->idx;
 957                 u64 enc;
 958
 959                 if (cpuc->current_idx[i] != PIC_NO_INDEX)
 960                         continue;
 961
 962                 sparc_perf_event_set_period(cp, hwc, idx);
 963                 cpuc->current_idx[i] = idx;
 964
 965                 enc = perf_event_get_enc(cpuc->events[i]);
 966                 cpuc->pcr[0] &= ~mask_for_index(idx);
 967                 if (hwc->state & PERF_HES_ARCH) {
 968                         cpuc->pcr[0] |= nop_for_index(idx);
 969                 } else {
 970                         cpuc->pcr[0] |= event_encoding(enc, idx);
 971                         hwc->state = 0;
 972                 }
 973         }
 974 out:
 975         cpuc->pcr[0] |= cpuc->event[0]->hw.config_base;
 976 }
 977
 978 static void sparc_pmu_start(struct perf_event *event, int flags);
 979
 980 /* On this PMU each PIC has it's own PCR control register.  */
 981 static void calculate_multiple_pcrs(struct cpu_hw_events *cpuc)
 982 {
 983         int i;
 984
 985         if (!cpuc->n_added)
 986                 goto out;
 987
 988         for (i = 0; i < cpuc->n_events; i++) {
 989                 struct perf_event *cp = cpuc->event[i];
 990                 struct hw_perf_event *hwc = &cp->hw;
 991                 int idx = hwc->idx;
 992
 993                 if (cpuc->current_idx[i] != PIC_NO_INDEX)
 994                         continue;
 995
 996                 cpuc->current_idx[i] = idx;
 997
 998                 if (cp->hw.state & PERF_HES_ARCH)
 999                         continue;
1000
1001                 sparc_pmu_start(cp, PERF_EF_RELOAD);
1002         }
1003 out:
1004         for (i = 0; i < cpuc->n_events; i++) {
1005                 struct perf_event *cp = cpuc->event[i];
1006                 int idx = cp->hw.idx;
1007
1008                 cpuc->pcr[idx] |= cp->hw.config_base;
1009         }
1010 }
1011
1012 /* If performance event entries have been added, move existing events
1013  * around (if necessary) and then assign new entries to counters.
1014  */
1015 static void update_pcrs_for_enable(struct cpu_hw_events *cpuc)
1016 {
1017         if (cpuc->n_added)
1018                 read_in_all_counters(cpuc);
1019
1020         if (sparc_pmu->num_pcrs == 1) {
1021                 calculate_single_pcr(cpuc);
1022         } else {
1023                 calculate_multiple_pcrs(cpuc);
1024         }
1025 }
1026
1027 static void sparc_pmu_enable(struct pmu *pmu)
1028 {
1029         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1030         int i;
1031
1032         if (cpuc->enabled)
1033                 return;
1034
1035         cpuc->enabled = 1;
1036         barrier();
1037
1038         if (cpuc->n_events)
1039                 update_pcrs_for_enable(cpuc);
1040
1041         for (i = 0; i < sparc_pmu->num_pcrs; i++)
1042                 pcr_ops->write_pcr(i, cpuc->pcr[i]);
1043 }
1044
1045 static void sparc_pmu_disable(struct pmu *pmu)
1046 {
1047         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1048         int i;
1049
1050         if (!cpuc->enabled)
1051                 return;
1052
1053         cpuc->enabled = 0;
1054         cpuc->n_added = 0;
1055
1056         for (i = 0; i < sparc_pmu->num_pcrs; i++) {
1057                 u64 val = cpuc->pcr[i];
1058
1059                 val &= ~(sparc_pmu->user_bit | sparc_pmu->priv_bit |
1060                          sparc_pmu->hv_bit | sparc_pmu->irq_bit);
1061                 cpuc->pcr[i] = val;
1062                 pcr_ops->write_pcr(i, cpuc->pcr[i]);
1063         }
1064 }
1065
1066 static int active_event_index(struct cpu_hw_events *cpuc,
1067                               struct perf_event *event)
1068 {
1069         int i;
1070
1071         for (i = 0; i < cpuc->n_events; i++) {
1072                 if (cpuc->event[i] == event)
1073                         break;
1074         }
1075         BUG_ON(i == cpuc->n_events);
1076         return cpuc->current_idx[i];
1077 }
1078
1079 static void sparc_pmu_start(struct perf_event *event, int flags)
1080 {
1081         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1082         int idx = active_event_index(cpuc, event);
1083
1084         if (flags & PERF_EF_RELOAD) {
1085                 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
1086                 sparc_perf_event_set_period(event, &event->hw, idx);
1087         }
1088
1089         event->hw.state = 0;
1090
1091         sparc_pmu_enable_event(cpuc, &event->hw, idx);
1092
1093         perf_event_update_userpage(event);
1094 }
1095
1096 static void sparc_pmu_stop(struct perf_event *event, int flags)
1097 {
1098         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1099         int idx = active_event_index(cpuc, event);
1100
1101         if (!(event->hw.state & PERF_HES_STOPPED)) {
1102                 sparc_pmu_disable_event(cpuc, &event->hw, idx);
1103                 event->hw.state |= PERF_HES_STOPPED;
1104         }
1105
1106         if (!(event->hw.state & PERF_HES_UPTODATE) && (flags & PERF_EF_UPDATE)) {
1107                 sparc_perf_event_update(event, &event->hw, idx);
1108                 event->hw.state |= PERF_HES_UPTODATE;
1109         }
1110 }
1111
1112 static void sparc_pmu_del(struct perf_event *event, int _flags)
1113 {
1114         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1115         unsigned long flags;
1116         int i;
1117
1118         local_irq_save(flags);
1119
1120         for (i = 0; i < cpuc->n_events; i++) {
1121                 if (event == cpuc->event[i]) {
1122                         /* Absorb the final count and turn off the
1123                          * event.
1124                          */
1125                         sparc_pmu_stop(event, PERF_EF_UPDATE);
1126
1127                         /* Shift remaining entries down into
1128                          * the existing slot.
1129                          */
1130                         while (++i < cpuc->n_events) {
1131                                 cpuc->event[i - 1] = cpuc->event[i];
1132                                 cpuc->events[i - 1] = cpuc->events[i];
1133                                 cpuc->current_idx[i - 1] =
1134                                         cpuc->current_idx[i];
1135                         }
1136
1137                         perf_event_update_userpage(event);
1138
1139                         cpuc->n_events--;
1140                         break;
1141                 }
1142         }
1143
1144         local_irq_restore(flags);
1145 }
1146
1147 static void sparc_pmu_read(struct perf_event *event)
1148 {
1149         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1150         int idx = active_event_index(cpuc, event);
1151         struct hw_perf_event *hwc = &event->hw;
1152
1153         sparc_perf_event_update(event, hwc, idx);
1154 }
1155
1156 static atomic_t active_events = ATOMIC_INIT(0);
1157 static DEFINE_MUTEX(pmc_grab_mutex);
1158
1159 static void perf_stop_nmi_watchdog(void *unused)
1160 {
1161         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1162         int i;
1163
1164         stop_nmi_watchdog(NULL);
1165         for (i = 0; i < sparc_pmu->num_pcrs; i++)
1166                 cpuc->pcr[i] = pcr_ops->read_pcr(i);
1167 }
1168
1169 static void perf_event_grab_pmc(void)
1170 {
1171         if (atomic_inc_not_zero(&active_events))
1172                 return;
1173
1174         mutex_lock(&pmc_grab_mutex);
1175         if (atomic_read(&active_events) == 0) {
1176                 if (atomic_read(&nmi_active) > 0) {
1177                         on_each_cpu(perf_stop_nmi_watchdog, NULL, 1);
1178                         BUG_ON(atomic_read(&nmi_active) != 0);
1179                 }
1180                 atomic_inc(&active_events);
1181         }
1182         mutex_unlock(&pmc_grab_mutex);
1183 }
1184
1185 static void perf_event_release_pmc(void)
1186 {
1187         if (atomic_dec_and_mutex_lock(&active_events, &pmc_grab_mutex)) {
1188                 if (atomic_read(&nmi_active) == 0)
1189                         on_each_cpu(start_nmi_watchdog, NULL, 1);
1190                 mutex_unlock(&pmc_grab_mutex);
1191         }
1192 }
1193
1194 static const struct perf_event_map *sparc_map_cache_event(u64 config)
1195 {
1196         unsigned int cache_type, cache_op, cache_result;
1197         const struct perf_event_map *pmap;
1198
1199         if (!sparc_pmu->cache_map)
1200                 return ERR_PTR(-ENOENT);
1201
1202         cache_type = (config >>  0) & 0xff;
1203         if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
1204                 return ERR_PTR(-EINVAL);
1205
1206         cache_op = (config >>  8) & 0xff;
1207         if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
1208                 return ERR_PTR(-EINVAL);
1209
1210         cache_result = (config >> 16) & 0xff;
1211         if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
1212                 return ERR_PTR(-EINVAL);
1213
1214         pmap = &((*sparc_pmu->cache_map)[cache_type][cache_op][cache_result]);
1215
1216         if (pmap->encoding == CACHE_OP_UNSUPPORTED)
1217                 return ERR_PTR(-ENOENT);
1218
1219         if (pmap->encoding == CACHE_OP_NONSENSE)
1220                 return ERR_PTR(-EINVAL);
1221
1222         return pmap;
1223 }
1224
1225 static void hw_perf_event_destroy(struct perf_event *event)
1226 {
1227         perf_event_release_pmc();
1228 }
1229
1230 /* Make sure all events can be scheduled into the hardware at
1231  * the same time.  This is simplified by the fact that we only
1232  * need to support 2 simultaneous HW events.
1233  *
1234  * As a side effect, the evts[]->hw.idx values will be assigned
1235  * on success.  These are pending indexes.  When the events are
1236  * actually programmed into the chip, these values will propagate
1237  * to the per-cpu cpuc->current_idx[] slots, see the code in
1238  * maybe_change_configuration() for details.
1239  */
1240 static int sparc_check_constraints(struct perf_event **evts,
1241                                    unsigned long *events, int n_ev)
1242 {
1243         u8 msk0 = 0, msk1 = 0;
1244         int idx0 = 0;
1245
1246         /* This case is possible when we are invoked from
1247          * hw_perf_group_sched_in().
1248          */
1249         if (!n_ev)
1250                 return 0;
1251
1252         if (n_ev > sparc_pmu->max_hw_events)
1253                 return -1;
1254
1255         if (!(sparc_pmu->flags & SPARC_PMU_HAS_CONFLICTS)) {
1256                 int i;
1257
1258                 for (i = 0; i < n_ev; i++)
1259                         evts[i]->hw.idx = i;
1260                 return 0;
1261         }
1262
1263         msk0 = perf_event_get_msk(events[0]);
1264         if (n_ev == 1) {
1265                 if (msk0 & PIC_LOWER)
1266                         idx0 = 1;
1267                 goto success;
1268         }
1269         BUG_ON(n_ev != 2);
1270         msk1 = perf_event_get_msk(events[1]);
1271
1272         /* If both events can go on any counter, OK.  */
1273         if (msk0 == (PIC_UPPER | PIC_LOWER) &&
1274             msk1 == (PIC_UPPER | PIC_LOWER))
1275                 goto success;
1276
1277         /* If one event is limited to a specific counter,
1278          * and the other can go on both, OK.
1279          */
1280         if ((msk0 == PIC_UPPER || msk0 == PIC_LOWER) &&
1281             msk1 == (PIC_UPPER | PIC_LOWER)) {
1282                 if (msk0 & PIC_LOWER)
1283                         idx0 = 1;
1284                 goto success;
1285         }
1286
1287         if ((msk1 == PIC_UPPER || msk1 == PIC_LOWER) &&
1288             msk0 == (PIC_UPPER | PIC_LOWER)) {
1289                 if (msk1 & PIC_UPPER)
1290                         idx0 = 1;
1291                 goto success;
1292         }
1293
1294         /* If the events are fixed to different counters, OK.  */
1295         if ((msk0 == PIC_UPPER && msk1 == PIC_LOWER) ||
1296             (msk0 == PIC_LOWER && msk1 == PIC_UPPER)) {
1297                 if (msk0 & PIC_LOWER)
1298                         idx0 = 1;
1299                 goto success;
1300         }
1301
1302         /* Otherwise, there is a conflict.  */
1303         return -1;
1304
1305 success:
1306         evts[0]->hw.idx = idx0;
1307         if (n_ev == 2)
1308                 evts[1]->hw.idx = idx0 ^ 1;
1309         return 0;
1310 }
1311
1312 static int check_excludes(struct perf_event **evts, int n_prev, int n_new)
1313 {
1314         int eu = 0, ek = 0, eh = 0;
1315         struct perf_event *event;
1316         int i, n, first;
1317
1318         if (!(sparc_pmu->flags & SPARC_PMU_ALL_EXCLUDES_SAME))
1319                 return 0;
1320
1321         n = n_prev + n_new;
1322         if (n <= 1)
1323                 return 0;
1324
1325         first = 1;
1326         for (i = 0; i < n; i++) {
1327                 event = evts[i];
1328                 if (first) {
1329                         eu = event->attr.exclude_user;
1330                         ek = event->attr.exclude_kernel;
1331                         eh = event->attr.exclude_hv;
1332                         first = 0;
1333                 } else if (event->attr.exclude_user != eu ||
1334                            event->attr.exclude_kernel != ek ||
1335                            event->attr.exclude_hv != eh) {
1336                         return -EAGAIN;
1337                 }
1338         }
1339
1340         return 0;
1341 }
1342
1343 static int collect_events(struct perf_event *group, int max_count,
1344                           struct perf_event *evts[], unsigned long *events,
1345                           int *current_idx)
1346 {
1347         struct perf_event *event;
1348         int n = 0;
1349
1350         if (!is_software_event(group)) {
1351                 if (n >= max_count)
1352                         return -1;
1353                 evts[n] = group;
1354                 events[n] = group->hw.event_base;
1355                 current_idx[n++] = PIC_NO_INDEX;
1356         }
1357         list_for_each_entry(event, &group->sibling_list, group_entry) {
1358                 if (!is_software_event(event) &&
1359                     event->state != PERF_EVENT_STATE_OFF) {
1360                         if (n >= max_count)
1361                                 return -1;
1362                         evts[n] = event;
1363                         events[n] = event->hw.event_base;
1364                         current_idx[n++] = PIC_NO_INDEX;
1365                 }
1366         }
1367         return n;
1368 }
1369
1370 static int sparc_pmu_add(struct perf_event *event, int ef_flags)
1371 {
1372         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1373         int n0, ret = -EAGAIN;
1374         unsigned long flags;
1375
1376         local_irq_save(flags);
1377
1378         n0 = cpuc->n_events;
1379         if (n0 >= sparc_pmu->max_hw_events)
1380                 goto out;
1381
1382         cpuc->event[n0] = event;
1383         cpuc->events[n0] = event->hw.event_base;
1384         cpuc->current_idx[n0] = PIC_NO_INDEX;
1385
1386         event->hw.state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
1387         if (!(ef_flags & PERF_EF_START))
1388                 event->hw.state |= PERF_HES_ARCH;
1389
1390         /*
1391          * If group events scheduling transaction was started,
1392          * skip the schedulability test here, it will be performed
1393          * at commit time(->commit_txn) as a whole
1394          */
1395         if (cpuc->txn_flags & PERF_PMU_TXN_ADD)
1396                 goto nocheck;
1397
1398         if (check_excludes(cpuc->event, n0, 1))
1399                 goto out;
1400         if (sparc_check_constraints(cpuc->event, cpuc->events, n0 + 1))
1401                 goto out;
1402
1403 nocheck:
1404         cpuc->n_events++;
1405         cpuc->n_added++;
1406
1407         ret = 0;
1408 out:
1409         local_irq_restore(flags);
1410         return ret;
1411 }
1412
1413 static int sparc_pmu_event_init(struct perf_event *event)
1414 {
1415         struct perf_event_attr *attr = &event->attr;
1416         struct perf_event *evts[MAX_HWEVENTS];
1417         struct hw_perf_event *hwc = &event->hw;
1418         unsigned long events[MAX_HWEVENTS];
1419         int current_idx_dmy[MAX_HWEVENTS];
1420         const struct perf_event_map *pmap;
1421         int n;
1422
1423         if (atomic_read(&nmi_active) < 0)
1424                 return -ENODEV;
1425
1426         /* does not support taken branch sampling */
1427         if (has_branch_stack(event))
1428                 return -EOPNOTSUPP;
1429
1430         switch (attr->type) {
1431         case PERF_TYPE_HARDWARE:
1432                 if (attr->config >= sparc_pmu->max_events)
1433                         return -EINVAL;
1434                 pmap = sparc_pmu->event_map(attr->config);
1435                 break;
1436
1437         case PERF_TYPE_HW_CACHE:
1438                 pmap = sparc_map_cache_event(attr->config);
1439                 if (IS_ERR(pmap))
1440                         return PTR_ERR(pmap);
1441                 break;
1442
1443         case PERF_TYPE_RAW:
1444                 pmap = NULL;
1445                 break;
1446
1447         default:
1448                 return -ENOENT;
1449
1450         }
1451
1452         if (pmap) {
1453                 hwc->event_base = perf_event_encode(pmap);
1454         } else {
1455                 /*
1456                  * User gives us "(encoding << 16) | pic_mask" for
1457                  * PERF_TYPE_RAW events.
1458                  */
1459                 hwc->event_base = attr->config;
1460         }
1461
1462         /* We save the enable bits in the config_base.  */
1463         hwc->config_base = sparc_pmu->irq_bit;
1464         if (!attr->exclude_user)
1465                 hwc->config_base |= sparc_pmu->user_bit;
1466         if (!attr->exclude_kernel)
1467                 hwc->config_base |= sparc_pmu->priv_bit;
1468         if (!attr->exclude_hv)
1469                 hwc->config_base |= sparc_pmu->hv_bit;
1470
1471         n = 0;
1472         if (event->group_leader != event) {
1473                 n = collect_events(event->group_leader,
1474                                    sparc_pmu->max_hw_events - 1,
1475                                    evts, events, current_idx_dmy);
1476                 if (n < 0)
1477                         return -EINVAL;
1478         }
1479         events[n] = hwc->event_base;
1480         evts[n] = event;
1481
1482         if (check_excludes(evts, n, 1))
1483                 return -EINVAL;
1484
1485         if (sparc_check_constraints(evts, events, n + 1))
1486                 return -EINVAL;
1487
1488         hwc->idx = PIC_NO_INDEX;
1489
1490         /* Try to do all error checking before this point, as unwinding
1491          * state after grabbing the PMC is difficult.
1492          */
1493         perf_event_grab_pmc();
1494         event->destroy = hw_perf_event_destroy;
1495
1496         if (!hwc->sample_period) {
1497                 hwc->sample_period = MAX_PERIOD;
1498                 hwc->last_period = hwc->sample_period;
1499                 local64_set(&hwc->period_left, hwc->sample_period);
1500         }
1501
1502         return 0;
1503 }
1504
1505 /*
1506  * Start group events scheduling transaction
1507  * Set the flag to make pmu::enable() not perform the
1508  * schedulability test, it will be performed at commit time
1509  */
1510 static void sparc_pmu_start_txn(struct pmu *pmu, unsigned int txn_flags)
1511 {
1512         struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
1513
1514         WARN_ON_ONCE(cpuhw->txn_flags);         /* txn already in flight */
1515
1516         cpuhw->txn_flags = txn_flags;
1517         if (txn_flags & ~PERF_PMU_TXN_ADD)
1518                 return;
1519
1520         perf_pmu_disable(pmu);
1521 }
1522
1523 /*
1524  * Stop group events scheduling transaction
1525  * Clear the flag and pmu::enable() will perform the
1526  * schedulability test.
1527  */
1528 static void sparc_pmu_cancel_txn(struct pmu *pmu)
1529 {
1530         struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
1531         unsigned int txn_flags;
1532
1533         WARN_ON_ONCE(!cpuhw->txn_flags);        /* no txn in flight */
1534
1535         txn_flags = cpuhw->txn_flags;
1536         cpuhw->txn_flags = 0;
1537         if (txn_flags & ~PERF_PMU_TXN_ADD)
1538                 return;
1539
1540         perf_pmu_enable(pmu);
1541 }
1542
1543 /*
1544  * Commit group events scheduling transaction
1545  * Perform the group schedulability test as a whole
1546  * Return 0 if success
1547  */
1548 static int sparc_pmu_commit_txn(struct pmu *pmu)
1549 {
1550         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1551         int n;
1552
1553         if (!sparc_pmu)
1554                 return -EINVAL;
1555
1556         WARN_ON_ONCE(!cpuc->txn_flags); /* no txn in flight */
1557
1558         if (cpuc->txn_flags & ~PERF_PMU_TXN_ADD) {
1559                 cpuc->txn_flags = 0;
1560                 return 0;
1561         }
1562
1563         n = cpuc->n_events;
1564         if (check_excludes(cpuc->event, 0, n))
1565                 return -EINVAL;
1566         if (sparc_check_constraints(cpuc->event, cpuc->events, n))
1567                 return -EAGAIN;
1568
1569         cpuc->txn_flags = 0;
1570         perf_pmu_enable(pmu);
1571         return 0;
1572 }
1573
1574 static struct pmu pmu = {
1575         .pmu_enable     = sparc_pmu_enable,
1576         .pmu_disable    = sparc_pmu_disable,
1577         .event_init     = sparc_pmu_event_init,
1578         .add            = sparc_pmu_add,
1579         .del            = sparc_pmu_del,
1580         .start          = sparc_pmu_start,
1581         .stop           = sparc_pmu_stop,
1582         .read           = sparc_pmu_read,
1583         .start_txn      = sparc_pmu_start_txn,
1584         .cancel_txn     = sparc_pmu_cancel_txn,
1585         .commit_txn     = sparc_pmu_commit_txn,
1586 };
1587
1588 void perf_event_print_debug(void)
1589 {
1590         unsigned long flags;
1591         int cpu, i;
1592
1593         if (!sparc_pmu)
1594                 return;
1595
1596         local_irq_save(flags);
1597
1598         cpu = smp_processor_id();
1599
1600         pr_info("\n");
1601         for (i = 0; i < sparc_pmu->num_pcrs; i++)
1602                 pr_info("CPU#%d: PCR%d[%016llx]\n",
1603                         cpu, i, pcr_ops->read_pcr(i));
1604         for (i = 0; i < sparc_pmu->num_pic_regs; i++)
1605                 pr_info("CPU#%d: PIC%d[%016llx]\n",
1606                         cpu, i, pcr_ops->read_pic(i));
1607
1608         local_irq_restore(flags);
1609 }
1610
1611 static int __kprobes perf_event_nmi_handler(struct notifier_block *self,
1612                                             unsigned long cmd, void *__args)
1613 {
1614         struct die_args *args = __args;
1615         struct perf_sample_data data;
1616         struct cpu_hw_events *cpuc;
1617         struct pt_regs *regs;
1618         int i;
1619
1620         if (!atomic_read(&active_events))
1621                 return NOTIFY_DONE;
1622
1623         switch (cmd) {
1624         case DIE_NMI:
1625                 break;
1626
1627         default:
1628                 return NOTIFY_DONE;
1629         }
1630
1631         regs = args->regs;
1632
1633         cpuc = this_cpu_ptr(&cpu_hw_events);
1634
1635         /* If the PMU has the TOE IRQ enable bits, we need to do a
1636          * dummy write to the %pcr to clear the overflow bits and thus
1637          * the interrupt.
1638          *
1639          * Do this before we peek at the counters to determine
1640          * overflow so we don't lose any events.
1641          */
1642         if (sparc_pmu->irq_bit &&
1643             sparc_pmu->num_pcrs == 1)
1644                 pcr_ops->write_pcr(0, cpuc->pcr[0]);
1645
1646         for (i = 0; i < cpuc->n_events; i++) {
1647                 struct perf_event *event = cpuc->event[i];
1648                 int idx = cpuc->current_idx[i];
1649                 struct hw_perf_event *hwc;
1650                 u64 val;
1651
1652                 if (sparc_pmu->irq_bit &&
1653                     sparc_pmu->num_pcrs > 1)
1654                         pcr_ops->write_pcr(idx, cpuc->pcr[idx]);
1655
1656                 hwc = &event->hw;
1657                 val = sparc_perf_event_update(event, hwc, idx);
1658                 if (val & (1ULL << 31))
1659                         continue;
1660
1661                 perf_sample_data_init(&data, 0, hwc->last_period);
1662                 if (!sparc_perf_event_set_period(event, hwc, idx))
1663                         continue;
1664
1665                 if (perf_event_overflow(event, &data, regs))
1666                         sparc_pmu_stop(event, 0);
1667         }
1668
1669         return NOTIFY_STOP;
1670 }
1671
1672 static __read_mostly struct notifier_block perf_event_nmi_notifier = {
1673         .notifier_call          = perf_event_nmi_handler,
1674 };
1675
1676 static bool __init supported_pmu(void)
1677 {
1678         if (!strcmp(sparc_pmu_type, "ultra3") ||
1679             !strcmp(sparc_pmu_type, "ultra3+") ||
1680             !strcmp(sparc_pmu_type, "ultra3i") ||
1681             !strcmp(sparc_pmu_type, "ultra4+")) {
1682                 sparc_pmu = &ultra3_pmu;
1683                 return true;
1684         }
1685         if (!strcmp(sparc_pmu_type, "niagara")) {
1686                 sparc_pmu = &niagara1_pmu;
1687                 return true;
1688         }
1689         if (!strcmp(sparc_pmu_type, "niagara2") ||
1690             !strcmp(sparc_pmu_type, "niagara3")) {
1691                 sparc_pmu = &niagara2_pmu;
1692                 return true;
1693         }
1694         if (!strcmp(sparc_pmu_type, "niagara4") ||
1695             !strcmp(sparc_pmu_type, "niagara5")) {
1696                 sparc_pmu = &niagara4_pmu;
1697                 return true;
1698         }
1699         if (!strcmp(sparc_pmu_type, "sparc-m7")) {
1700                 sparc_pmu = &sparc_m7_pmu;
1701                 return true;
1702         }
1703         return false;
1704 }
1705
1706 static int __init init_hw_perf_events(void)
1707 {
1708         int err;
1709
1710         pr_info("Performance events: ");
1711
1712         err = pcr_arch_init();
1713         if (err || !supported_pmu()) {
1714                 pr_cont("No support for PMU type '%s'\n", sparc_pmu_type);
1715                 return 0;
1716         }
1717
1718         pr_cont("Supported PMU type is '%s'\n", sparc_pmu_type);
1719
1720         perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
1721         register_die_notifier(&perf_event_nmi_notifier);
1722
1723         return 0;
1724 }
1725 pure_initcall(init_hw_perf_events);
1726
1727 void perf_callchain_kernel(struct perf_callchain_entry_ctx *entry,
1728                            struct pt_regs *regs)
1729 {
1730         unsigned long ksp, fp;
1731 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1732         int graph = 0;
1733 #endif
1734
1735         stack_trace_flush();
1736
1737         perf_callchain_store(entry, regs->tpc);
1738
1739         ksp = regs->u_regs[UREG_I6];
1740         fp = ksp + STACK_BIAS;
1741         do {
1742                 struct sparc_stackf *sf;
1743                 struct pt_regs *regs;
1744                 unsigned long pc;
1745
1746                 if (!kstack_valid(current_thread_info(), fp))
1747                         break;
1748
1749                 sf = (struct sparc_stackf *) fp;
1750                 regs = (struct pt_regs *) (sf + 1);
1751
1752                 if (kstack_is_trap_frame(current_thread_info(), regs)) {
1753                         if (user_mode(regs))
1754                                 break;
1755                         pc = regs->tpc;
1756                         fp = regs->u_regs[UREG_I6] + STACK_BIAS;
1757                 } else {
1758                         pc = sf->callers_pc;
1759                         fp = (unsigned long)sf->fp + STACK_BIAS;
1760                 }
1761                 perf_callchain_store(entry, pc);
1762 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1763                 if ((pc + 8UL) == (unsigned long) &return_to_handler) {
1764                         int index = current->curr_ret_stack;
1765                         if (current->ret_stack && index >= graph) {
1766                                 pc = current->ret_stack[index - graph].ret;
1767                                 perf_callchain_store(entry, pc);
1768                                 graph++;
1769                         }
1770                 }
1771 #endif
1772         } while (entry->nr < entry->max_stack);
1773 }
1774
1775 static inline int
1776 valid_user_frame(const void __user *fp, unsigned long size)
1777 {
1778         /* addresses should be at least 4-byte aligned */
1779         if (((unsigned long) fp) & 3)
1780                 return 0;
1781
1782         return (__range_not_ok(fp, size, TASK_SIZE) == 0);
1783 }
1784
1785 static void perf_callchain_user_64(struct perf_callchain_entry_ctx *entry,
1786                                    struct pt_regs *regs)
1787 {
1788         unsigned long ufp;
1789
1790         ufp = regs->u_regs[UREG_FP] + STACK_BIAS;
1791         do {
1792                 struct sparc_stackf __user *usf;
1793                 struct sparc_stackf sf;
1794                 unsigned long pc;
1795
1796                 usf = (struct sparc_stackf __user *)ufp;
1797                 if (!valid_user_frame(usf, sizeof(sf)))
1798                         break;
1799
1800                 if (__copy_from_user_inatomic(&sf, usf, sizeof(sf)))
1801                         break;
1802
1803                 pc = sf.callers_pc;
1804                 ufp = (unsigned long)sf.fp + STACK_BIAS;
1805                 perf_callchain_store(entry, pc);
1806         } while (entry->nr < entry->max_stack);
1807 }
1808
1809 static void perf_callchain_user_32(struct perf_callchain_entry_ctx *entry,
1810                                    struct pt_regs *regs)
1811 {
1812         unsigned long ufp;
1813
1814         ufp = regs->u_regs[UREG_FP] & 0xffffffffUL;
1815         do {
1816                 unsigned long pc;
1817
1818                 if (thread32_stack_is_64bit(ufp)) {
1819                         struct sparc_stackf __user *usf;
1820                         struct sparc_stackf sf;
1821
1822                         ufp += STACK_BIAS;
1823                         usf = (struct sparc_stackf __user *)ufp;
1824                         if (__copy_from_user_inatomic(&sf, usf, sizeof(sf)))
1825                                 break;
1826                         pc = sf.callers_pc & 0xffffffff;
1827                         ufp = ((unsigned long) sf.fp) & 0xffffffff;
1828                 } else {
1829                         struct sparc_stackf32 __user *usf;
1830                         struct sparc_stackf32 sf;
1831                         usf = (struct sparc_stackf32 __user *)ufp;
1832                         if (__copy_from_user_inatomic(&sf, usf, sizeof(sf)))
1833                                 break;
1834                         pc = sf.callers_pc;
1835                         ufp = (unsigned long)sf.fp;
1836                 }
1837                 perf_callchain_store(entry, pc);
1838         } while (entry->nr < entry->max_stack);
1839 }
1840
1841 void
1842 perf_callchain_user(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs)
1843 {
1844         u64 saved_fault_address = current_thread_info()->fault_address;
1845         u8 saved_fault_code = get_thread_fault_code();
1846         mm_segment_t old_fs;
1847
1848         perf_callchain_store(entry, regs->tpc);
1849
1850         if (!current->mm)
1851                 return;
1852
1853         old_fs = get_fs();
1854         set_fs(USER_DS);
1855
1856         flushw_user();
1857
1858         pagefault_disable();
1859
1860         if (test_thread_flag(TIF_32BIT))
1861                 perf_callchain_user_32(entry, regs);
1862         else
1863                 perf_callchain_user_64(entry, regs);
1864
1865         pagefault_enable();
1866
1867         set_fs(old_fs);
1868         set_thread_fault_code(saved_fault_code);
1869         current_thread_info()->fault_address = saved_fault_address;
1870 }