1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* head.S: Initial boot code for the Sparc64 port of Linux.
4 * Copyright (C) 1996, 1997, 2007 David S. Miller (davem@davemloft.net)
5 * Copyright (C) 1996 David Sitsky (David.Sitsky@anu.edu.au)
6 * Copyright (C) 1997, 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
7 * Copyright (C) 1997 Miguel de Icaza (miguel@nuclecu.unam.mx)
10 #include <linux/version.h>
11 #include <linux/errno.h>
12 #include <linux/threads.h>
13 #include <linux/init.h>
14 #include <linux/linkage.h>
15 #include <asm/thread_info.h>
17 #include <asm/pstate.h>
18 #include <asm/ptrace.h>
19 #include <asm/spitfire.h>
21 #include <asm/pgtable.h>
22 #include <asm/errno.h>
23 #include <asm/signal.h>
24 #include <asm/processor.h>
29 #include <asm/ttable.h>
31 #include <asm/cpudata.h>
33 #include <asm/estate.h>
34 #include <asm/sfafsr.h>
35 #include <asm/unistd.h>
36 #include <asm/export.h>
38 /* This section from from _start to sparc64_boot_end should fit into
39 * 0x0000000000404000 to 0x0000000000408000.
42 .globl start, _start, stext, _stext
49 flushw /* Flush register file. */
51 /* This stuff has to be in sync with SILO and other potential boot loaders
52 * Fields should be kept upward compatible and whenever any change is made,
53 * HdrS version should be incremented.
55 .global root_flags, ram_flags, root_dev
56 .global sparc_ramdisk_image, sparc_ramdisk_size
57 .global sparc_ramdisk_image64
60 .word LINUX_VERSION_CODE
64 * 0x0300 : Supports being located at other than 0x4000
65 * 0x0202 : Supports kernel params string
66 * 0x0201 : Supports reboot_command
68 .half 0x0301 /* HdrS version */
82 sparc_ramdisk_image64:
86 /* PROM cif handler code address is in %o4. */
90 /* We need to remap the kernel. Use position independent
91 * code to remap us to KERNBASE.
93 * SILO can invoke us with 32-bit address masking enabled,
94 * so make sure that's clear.
97 andn %g1, PSTATE_AM, %g1
98 wrpr %g1, 0x0, %pstate
102 .globl prom_finddev_name, prom_chosen_path, prom_root_node
103 .globl prom_getprop_name, prom_mmu_name, prom_peer_name
104 .globl prom_callmethod_name, prom_translate_name, prom_root_compatible
105 .globl prom_map_name, prom_unmap_name, prom_mmu_ihandle_cache
106 .globl prom_boot_mapped_pc, prom_boot_mapping_mode
107 .globl prom_boot_mapping_phys_high, prom_boot_mapping_phys_low
108 .globl prom_compatible_name, prom_cpu_path, prom_cpu_compatible
109 .globl is_sun4v, sun4v_chip_type, prom_set_trap_table_name
112 prom_compatible_name:
124 prom_callmethod_name:
132 prom_set_trap_table_name:
133 .asciz "SUNW,set-trap-table"
137 .asciz "SUNW,UltraSPARC-T"
140 prom_sparc64x_prefix:
143 prom_root_compatible:
149 EXPORT_SYMBOL(prom_root_node)
150 prom_mmu_ihandle_cache:
154 prom_boot_mapping_mode:
157 prom_boot_mapping_phys_high:
159 prom_boot_mapping_phys_low:
164 .word SUN4V_CHIP_INVALID
165 EXPORT_SYMBOL(sun4v_chip_type)
169 mov (1b - prom_peer_name), %l1
173 /* prom_root_node = prom_peer(0) */
174 stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "peer"
176 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 1
177 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
178 stx %l2, [%sp + 2047 + 128 + 0x18] ! arg1, 0
179 stx %g0, [%sp + 2047 + 128 + 0x20] ! ret1
181 add %sp, (2047 + 128), %o0 ! argument array
183 ldx [%sp + 2047 + 128 + 0x20], %l4 ! prom root node
184 mov (1b - prom_root_node), %l1
188 mov (1b - prom_getprop_name), %l1
189 mov (1b - prom_compatible_name), %l2
190 mov (1b - prom_root_compatible), %l5
195 /* prom_getproperty(prom_root_node, "compatible",
196 * &prom_root_compatible, 64)
198 stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "getprop"
200 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 4
202 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
203 stx %l4, [%sp + 2047 + 128 + 0x18] ! arg1, prom_root_node
204 stx %l2, [%sp + 2047 + 128 + 0x20] ! arg2, "compatible"
205 stx %l5, [%sp + 2047 + 128 + 0x28] ! arg3, &prom_root_compatible
207 stx %l3, [%sp + 2047 + 128 + 0x30] ! arg4, size
208 stx %g0, [%sp + 2047 + 128 + 0x38] ! ret1
210 add %sp, (2047 + 128), %o0 ! argument array
212 mov (1b - prom_finddev_name), %l1
213 mov (1b - prom_chosen_path), %l2
214 mov (1b - prom_boot_mapped_pc), %l3
219 sub %sp, (192 + 128), %sp
221 /* chosen_node = prom_finddevice("/chosen") */
222 stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "finddevice"
224 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 1
225 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
226 stx %l2, [%sp + 2047 + 128 + 0x18] ! arg1, "/chosen"
227 stx %g0, [%sp + 2047 + 128 + 0x20] ! ret1
229 add %sp, (2047 + 128), %o0 ! argument array
231 ldx [%sp + 2047 + 128 + 0x20], %l4 ! chosen device node
233 mov (1b - prom_getprop_name), %l1
234 mov (1b - prom_mmu_name), %l2
235 mov (1b - prom_mmu_ihandle_cache), %l5
240 /* prom_mmu_ihandle_cache = prom_getint(chosen_node, "mmu") */
241 stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "getprop"
243 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 4
245 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
246 stx %l4, [%sp + 2047 + 128 + 0x18] ! arg1, chosen_node
247 stx %l2, [%sp + 2047 + 128 + 0x20] ! arg2, "mmu"
248 stx %l5, [%sp + 2047 + 128 + 0x28] ! arg3, &prom_mmu_ihandle_cache
250 stx %l3, [%sp + 2047 + 128 + 0x30] ! arg4, sizeof(arg3)
251 stx %g0, [%sp + 2047 + 128 + 0x38] ! ret1
253 add %sp, (2047 + 128), %o0 ! argument array
255 mov (1b - prom_callmethod_name), %l1
256 mov (1b - prom_translate_name), %l2
259 lduw [%l5], %l5 ! prom_mmu_ihandle_cache
261 stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "call-method"
263 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 3
265 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 5
266 stx %l2, [%sp + 2047 + 128 + 0x18] ! arg1: "translate"
267 stx %l5, [%sp + 2047 + 128 + 0x20] ! arg2: prom_mmu_ihandle_cache
271 stx %l3, [%sp + 2047 + 128 + 0x28] ! arg3: vaddr, our PC
272 stx %g0, [%sp + 2047 + 128 + 0x30] ! res1
273 stx %g0, [%sp + 2047 + 128 + 0x38] ! res2
274 stx %g0, [%sp + 2047 + 128 + 0x40] ! res3
275 stx %g0, [%sp + 2047 + 128 + 0x48] ! res4
276 stx %g0, [%sp + 2047 + 128 + 0x50] ! res5
278 add %sp, (2047 + 128), %o0 ! argument array
280 ldx [%sp + 2047 + 128 + 0x40], %l1 ! translation mode
281 mov (1b - prom_boot_mapping_mode), %l4
284 mov (1b - prom_boot_mapping_phys_high), %l4
286 ldx [%sp + 2047 + 128 + 0x48], %l2 ! physaddr high
288 ldx [%sp + 2047 + 128 + 0x50], %l3 ! physaddr low
290 srlx %l3, ILOG2_4MB, %l3
291 sllx %l3, ILOG2_4MB, %l3
294 /* Leave service as-is, "call-method" */
296 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 7
298 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
299 mov (1b - prom_map_name), %l3
301 stx %l3, [%sp + 2047 + 128 + 0x18] ! arg1: "map"
302 /* Leave arg2 as-is, prom_mmu_ihandle_cache */
304 stx %l3, [%sp + 2047 + 128 + 0x28] ! arg3: mode (-1 default)
305 /* 4MB align the kernel image size. */
306 set (_end - KERNBASE), %l3
307 set ((4 * 1024 * 1024) - 1), %l4
310 stx %l3, [%sp + 2047 + 128 + 0x30] ! arg4: roundup(ksize, 4MB)
311 sethi %hi(KERNBASE), %l3
312 stx %l3, [%sp + 2047 + 128 + 0x38] ! arg5: vaddr (KERNBASE)
313 stx %g0, [%sp + 2047 + 128 + 0x40] ! arg6: empty
314 mov (1b - prom_boot_mapping_phys_low), %l3
317 stx %l3, [%sp + 2047 + 128 + 0x48] ! arg7: phys addr
319 add %sp, (2047 + 128), %o0 ! argument array
321 add %sp, (192 + 128), %sp
323 sethi %hi(prom_root_compatible), %g1
324 or %g1, %lo(prom_root_compatible), %g1
325 sethi %hi(prom_sun4v_name), %g7
326 or %g7, %lo(prom_sun4v_name), %g7
337 sethi %hi(is_sun4v), %g1
338 or %g1, %lo(is_sun4v), %g1
342 /* cpu_node = prom_finddevice("/cpu") */
343 mov (1b - prom_finddev_name), %l1
344 mov (1b - prom_cpu_path), %l2
347 sub %sp, (192 + 128), %sp
349 stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "finddevice"
351 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 1
352 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
353 stx %l2, [%sp + 2047 + 128 + 0x18] ! arg1, "/cpu"
354 stx %g0, [%sp + 2047 + 128 + 0x20] ! ret1
356 add %sp, (2047 + 128), %o0 ! argument array
358 ldx [%sp + 2047 + 128 + 0x20], %l4 ! cpu device node
360 mov (1b - prom_getprop_name), %l1
361 mov (1b - prom_compatible_name), %l2
362 mov (1b - prom_cpu_compatible), %l5
367 /* prom_getproperty(cpu_node, "compatible",
368 * &prom_cpu_compatible, 64)
370 stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "getprop"
372 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 4
374 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
375 stx %l4, [%sp + 2047 + 128 + 0x18] ! arg1, cpu_node
376 stx %l2, [%sp + 2047 + 128 + 0x20] ! arg2, "compatible"
377 stx %l5, [%sp + 2047 + 128 + 0x28] ! arg3, &prom_cpu_compatible
379 stx %l3, [%sp + 2047 + 128 + 0x30] ! arg4, size
380 stx %g0, [%sp + 2047 + 128 + 0x38] ! ret1
382 add %sp, (2047 + 128), %o0 ! argument array
384 add %sp, (192 + 128), %sp
386 sethi %hi(prom_cpu_compatible), %g1
387 or %g1, %lo(prom_cpu_compatible), %g1
388 sethi %hi(prom_niagara_prefix), %g7
389 or %g7, %lo(prom_niagara_prefix), %g7
402 89: sethi %hi(prom_cpu_compatible), %g1
403 or %g1, %lo(prom_cpu_compatible), %g1
404 sethi %hi(prom_sparc_prefix), %g7
405 or %g7, %lo(prom_sparc_prefix), %g7
416 sethi %hi(prom_cpu_compatible), %g1
417 or %g1, %lo(prom_cpu_compatible), %g1
427 70: ldub [%g1 + 7], %g2
428 cmp %g2, CPU_ID_NIAGARA3
430 mov SUN4V_CHIP_NIAGARA3, %g4
431 cmp %g2, CPU_ID_NIAGARA4
433 mov SUN4V_CHIP_NIAGARA4, %g4
434 cmp %g2, CPU_ID_NIAGARA5
436 mov SUN4V_CHIP_NIAGARA5, %g4
439 mov SUN4V_CHIP_SPARC_M6, %g4
442 mov SUN4V_CHIP_SPARC_M7, %g4
445 mov SUN4V_CHIP_SPARC_M8, %g4
446 cmp %g2, CPU_ID_SONOMA1
448 mov SUN4V_CHIP_SPARC_SN, %g4
452 91: sethi %hi(prom_cpu_compatible), %g1
453 or %g1, %lo(prom_cpu_compatible), %g1
455 cmp %g2, CPU_ID_NIAGARA1
457 mov SUN4V_CHIP_NIAGARA1, %g4
458 cmp %g2, CPU_ID_NIAGARA2
460 mov SUN4V_CHIP_NIAGARA2, %g4
464 sethi %hi(prom_cpu_compatible), %g1
465 or %g1, %lo(prom_cpu_compatible), %g1
466 sethi %hi(prom_sparc64x_prefix), %g7
467 or %g7, %lo(prom_sparc64x_prefix), %g7
478 mov SUN4V_CHIP_SPARC64X, %g4
481 mov SUN4V_CHIP_UNKNOWN, %g4
482 5: sethi %hi(sun4v_chip_type), %g2
483 or %g2, %lo(sun4v_chip_type), %g2
487 BRANCH_IF_SUN4V(g1, jump_to_sun4u_init)
488 BRANCH_IF_CHEETAH_BASE(g1,g7,cheetah_boot)
489 BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g7,cheetah_plus_boot)
490 ba,pt %xcc, spitfire_boot
494 /* Preserve OBP chosen DCU and DCR register settings. */
495 ba,pt %xcc, cheetah_generic_boot
499 mov DCR_BPE | DCR_RPE | DCR_SI | DCR_IFPOE | DCR_MS, %g1
502 sethi %uhi(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g7
503 or %g7, %ulo(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g7
505 or %g7, DCU_DM | DCU_IM | DCU_DC | DCU_IC, %g7
506 stxa %g7, [%g0] ASI_DCU_CONTROL_REG
509 cheetah_generic_boot:
510 mov TSB_EXTENSION_P, %g3
511 stxa %g0, [%g3] ASI_DMMU
512 stxa %g0, [%g3] ASI_IMMU
515 mov TSB_EXTENSION_S, %g3
516 stxa %g0, [%g3] ASI_DMMU
519 mov TSB_EXTENSION_N, %g3
520 stxa %g0, [%g3] ASI_DMMU
521 stxa %g0, [%g3] ASI_IMMU
524 ba,a,pt %xcc, jump_to_sun4u_init
527 /* Typically PROM has already enabled both MMU's and both on-chip
528 * caches, but we do it here anyway just to be paranoid.
530 mov (LSU_CONTROL_IC|LSU_CONTROL_DC|LSU_CONTROL_IM|LSU_CONTROL_DM), %g1
531 stxa %g1, [%g0] ASI_LSU_CONTROL
536 * Make sure we are in privileged mode, have address masking,
537 * using the ordinary globals and have enabled floating
540 * Again, typically PROM has left %pil at 13 or similar, and
541 * (PSTATE_PRIV | PSTATE_PEF | PSTATE_IE) in %pstate.
543 wrpr %g0, (PSTATE_PRIV|PSTATE_PEF|PSTATE_IE), %pstate
552 BRANCH_IF_SUN4V(g1, sun4v_init)
555 mov PRIMARY_CONTEXT, %g7
556 stxa %g0, [%g7] ASI_DMMU
559 mov SECONDARY_CONTEXT, %g7
560 stxa %g0, [%g7] ASI_DMMU
563 ba,a,pt %xcc, sun4u_continue
567 mov PRIMARY_CONTEXT, %g7
568 stxa %g0, [%g7] ASI_MMU
571 mov SECONDARY_CONTEXT, %g7
572 stxa %g0, [%g7] ASI_MMU
574 ba,a,pt %xcc, niagara_tlb_fixup
577 BRANCH_IF_ANY_CHEETAH(g1, g7, cheetah_tlb_fixup)
579 ba,a,pt %xcc, spitfire_tlb_fixup
582 mov 3, %g2 /* Set TLB type to hypervisor. */
583 sethi %hi(tlb_type), %g1
584 stw %g2, [%g1 + %lo(tlb_type)]
586 /* Patch copy/clear ops. */
587 sethi %hi(sun4v_chip_type), %g1
588 lduw [%g1 + %lo(sun4v_chip_type)], %g1
589 cmp %g1, SUN4V_CHIP_NIAGARA1
590 be,pt %xcc, niagara_patch
591 cmp %g1, SUN4V_CHIP_NIAGARA2
592 be,pt %xcc, niagara2_patch
594 cmp %g1, SUN4V_CHIP_NIAGARA3
595 be,pt %xcc, niagara2_patch
597 cmp %g1, SUN4V_CHIP_NIAGARA4
598 be,pt %xcc, niagara4_patch
600 cmp %g1, SUN4V_CHIP_NIAGARA5
601 be,pt %xcc, niagara4_patch
603 cmp %g1, SUN4V_CHIP_SPARC_M6
604 be,pt %xcc, niagara4_patch
606 cmp %g1, SUN4V_CHIP_SPARC_M7
607 be,pt %xcc, sparc_m7_patch
609 cmp %g1, SUN4V_CHIP_SPARC_M8
610 be,pt %xcc, sparc_m7_patch
612 cmp %g1, SUN4V_CHIP_SPARC_SN
613 be,pt %xcc, niagara4_patch
616 call generic_patch_copyops
618 call generic_patch_bzero
620 call generic_patch_pageops
627 call m7_patch_copyops
631 call m7_patch_pageops
638 call niagara4_patch_copyops
640 call niagara4_patch_bzero
642 call niagara4_patch_pageops
649 call niagara2_patch_copyops
651 call niagara_patch_bzero
653 call niagara_patch_pageops
660 call niagara_patch_copyops
662 call niagara_patch_bzero
664 call niagara_patch_pageops
668 /* Patch TLB/cache ops. */
669 call hypervisor_patch_cachetlbops
672 ba,a,pt %xcc, tlb_fixup_done
675 mov 2, %g2 /* Set TLB type to cheetah+. */
676 BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g7,1f)
678 mov 1, %g2 /* Set TLB type to cheetah. */
680 1: sethi %hi(tlb_type), %g1
681 stw %g2, [%g1 + %lo(tlb_type)]
683 /* Patch copy/page operations to cheetah optimized versions. */
684 call cheetah_patch_copyops
686 call cheetah_patch_copy_page
688 call cheetah_patch_cachetlbops
691 ba,a,pt %xcc, tlb_fixup_done
694 /* Set TLB type to spitfire. */
696 sethi %hi(tlb_type), %g1
697 stw %g2, [%g1 + %lo(tlb_type)]
700 sethi %hi(init_thread_union), %g6
701 or %g6, %lo(init_thread_union), %g6
702 ldx [%g6 + TI_TASK], %g4
706 sllx %g1, THREAD_SHIFT, %g1
707 sub %g1, (STACKFRAME_SZ + STACK_BIAS), %g1
710 /* Set per-cpu pointer initially to zero, this makes
711 * the boot-cpu use the in-kernel-image per-cpu areas
712 * before setup_per_cpu_area() is invoked.
720 sethi %hi(__bss_start), %o0
721 or %o0, %lo(__bss_start), %o0
723 or %o1, %lo(_end), %o1
728 mov %l7, %o0 ! OpenPROM cif handler
730 /* To create a one-register-window buffer between the kernel's
731 * initial stack and the last stack frame we use from the firmware,
732 * do the rest of the boot from a C helper function.
734 call start_early_boot
740 /* This is meant to allow the sharing of this code between
741 * boot processor invocation (via setup_tba() below) and
742 * secondary processor startup (via trampoline.S). The
743 * former does use this code, the latter does not yet due
744 * to some complexities. That should be fixed up at some
747 * There used to be enormous complexity wrt. transferring
748 * over from the firmware's trap table to the Linux kernel's.
749 * For example, there was a chicken & egg problem wrt. building
750 * the OBP page tables, yet needing to be on the Linux kernel
751 * trap table (to translate PAGE_OFFSET addresses) in order to
754 * We now handle OBP tlb misses differently, via linear lookups
755 * into the prom_trans[] array. So that specific problem no
756 * longer exists. Yet, unfortunately there are still some issues
757 * preventing trampoline.S from using this code... ho hum.
759 .globl setup_trap_table
763 /* Force interrupts to be disabled. */
765 andn %l0, PSTATE_IE, %o1
766 wrpr %o1, 0x0, %pstate
768 wrpr %g0, PIL_NORMAL_MAX, %pil
770 /* Make the firmware call to jump over to the Linux trap table. */
771 sethi %hi(is_sun4v), %o0
772 lduw [%o0 + %lo(is_sun4v)], %o0
776 TRAP_LOAD_TRAP_BLOCK(%g2, %g3)
777 add %g2, TRAP_PER_CPU_FAULT_INFO, %g2
778 stxa %g2, [%g0] ASI_SCRATCHPAD
780 /* Compute physical address:
782 * paddr = kern_base + (mmfsa_vaddr - KERNBASE)
784 sethi %hi(KERNBASE), %g3
786 sethi %hi(kern_base), %g3
787 ldx [%g3 + %lo(kern_base)], %g3
789 sethi %hi(sparc64_ttable_tl0), %o0
791 set prom_set_trap_table_name, %g2
792 stx %g2, [%sp + 2047 + 128 + 0x00]
794 stx %g2, [%sp + 2047 + 128 + 0x08]
796 stx %g2, [%sp + 2047 + 128 + 0x10]
797 stx %o0, [%sp + 2047 + 128 + 0x18]
798 stx %o1, [%sp + 2047 + 128 + 0x20]
799 sethi %hi(p1275buf), %g2
800 or %g2, %lo(p1275buf), %g2
801 ldx [%g2 + 0x08], %o1
803 add %sp, (2047 + 128), %o0
807 1: sethi %hi(sparc64_ttable_tl0), %o0
808 set prom_set_trap_table_name, %g2
809 stx %g2, [%sp + 2047 + 128 + 0x00]
811 stx %g2, [%sp + 2047 + 128 + 0x08]
813 stx %g2, [%sp + 2047 + 128 + 0x10]
814 stx %o0, [%sp + 2047 + 128 + 0x18]
815 sethi %hi(p1275buf), %g2
816 or %g2, %lo(p1275buf), %g2
817 ldx [%g2 + 0x08], %o1
819 add %sp, (2047 + 128), %o0
821 /* Start using proper page size encodings in ctx register. */
822 2: sethi %hi(sparc64_kern_pri_context), %g3
823 ldx [%g3 + %lo(sparc64_kern_pri_context)], %g2
825 mov PRIMARY_CONTEXT, %g1
827 661: stxa %g2, [%g1] ASI_DMMU
828 .section .sun4v_1insn_patch, "ax"
830 stxa %g2, [%g1] ASI_MMU
835 BRANCH_IF_SUN4V(o2, 1f)
837 /* Kill PROM timer */
838 sethi %hi(0x80000000), %o2
840 wr %o2, 0, %tick_cmpr
842 BRANCH_IF_ANY_CHEETAH(o2, o3, 1f)
846 /* Disable STICK_INT interrupts. */
848 sethi %hi(0x80000000), %o2
853 wrpr %g0, %g0, %wstate
855 call init_irqwork_curcpu
858 /* Now we can restore interrupt state. */
869 /* The boot processor is the only cpu which invokes this
870 * routine, the other cpus set things up via trampoline.S.
871 * So save the OBP trap table address here.
874 sethi %hi(prom_tba), %o1
875 or %o1, %lo(prom_tba), %o1
878 call setup_trap_table
885 #include "etrap_64.S"
886 #include "rtrap_64.S"
887 #include "winfixup.S"
888 #include "fpu_traps.S"
890 #include "getsetcc.S"
892 #include "spiterrs.S"
894 #include "misctrap.S"
895 #include "syscalls.S"
897 #include "sun4v_tlb_miss.S"
898 #include "sun4v_ivec.S"
903 * The following skip makes sure the trap table in ttable.S is aligned
904 * on a 32K boundary as required by the v9 specs for TBA register.
906 * We align to a 32K boundary, then we have the 32K kernel TSB,
907 * the 64K kernel 4MB TSB, and then the 32K aligned trap table.
910 .skip 0x4000 + _start - 1b
918 .globl swapper_4m_tsb
924 /* Some care needs to be exercised if you try to move the
925 * location of the trap table relative to other things. For
926 * one thing there are br* instructions in some of the
927 * trap table entires which branch back to code in ktlb.S
928 * Those instructions can only handle a signed 16-bit
931 * There is a binutils bug (bugzilla #4558) which causes
932 * the relocation overflow checks for such instructions to
933 * not be done correctly. So bintuils will not notice the
934 * error and will instead write junk into the relocation and
935 * you'll have an unbootable kernel.
937 #include "ttable_64.S"
942 #include "systbls_64.S"
946 .globl prom_tba, tlb_type
948 tlb_type: .word 0 /* Must NOT end up in BSS */
949 EXPORT_SYMBOL(tlb_type)
950 .section ".fixup",#alloc,#execinstr
955 ENDPROC(__retl_efault)
966 ENDPROC(__retl_o1_asi)