1 /* SPDX-License-Identifier: GPL-2.0 */
5 #include <linux/kernel.h>
6 #include <linux/compiler.h>
7 #include <linux/types.h>
9 #include <asm/page.h> /* IO address mapping routines need this */
11 #include <asm-generic/pci_iomap.h>
12 #define pci_iomap pci_iomap
14 /* BIO layer definitions. */
15 extern unsigned long kern_base, kern_size;
17 /* __raw_{read,write}{b,w,l,q} uses direct access.
18 * Access the memory as big endian bypassing the cache
19 * by using ASI_PHYS_BYPASS_EC_E
21 #define __raw_readb __raw_readb
22 static inline u8 __raw_readb(const volatile void __iomem *addr)
26 __asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_raw_readb */"
28 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
33 #define __raw_readw __raw_readw
34 static inline u16 __raw_readw(const volatile void __iomem *addr)
38 __asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_raw_readw */"
40 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
45 #define __raw_readl __raw_readl
46 static inline u32 __raw_readl(const volatile void __iomem *addr)
50 __asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_raw_readl */"
52 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
57 #define __raw_readq __raw_readq
58 static inline u64 __raw_readq(const volatile void __iomem *addr)
62 __asm__ __volatile__("ldxa\t[%1] %2, %0\t/* pci_raw_readq */"
64 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
69 #define __raw_writeb __raw_writeb
70 static inline void __raw_writeb(u8 b, const volatile void __iomem *addr)
72 __asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_raw_writeb */"
74 : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
77 #define __raw_writew __raw_writew
78 static inline void __raw_writew(u16 w, const volatile void __iomem *addr)
80 __asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_raw_writew */"
82 : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
85 #define __raw_writel __raw_writel
86 static inline void __raw_writel(u32 l, const volatile void __iomem *addr)
88 __asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_raw_writel */"
90 : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
93 #define __raw_writeq __raw_writeq
94 static inline void __raw_writeq(u64 q, const volatile void __iomem *addr)
96 __asm__ __volatile__("stxa\t%r0, [%1] %2\t/* pci_raw_writeq */"
98 : "Jr" (q), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
101 /* Memory functions, same as I/O accesses on Ultra.
102 * Access memory as little endian bypassing
103 * the cache by using ASI_PHYS_BYPASS_EC_E_L
106 #define readb_relaxed readb
107 static inline u8 readb(const volatile void __iomem *addr)
110 __asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_readb */"
112 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
118 #define readw_relaxed readw
119 static inline u16 readw(const volatile void __iomem *addr)
122 __asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_readw */"
124 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
131 #define readl_relaxed readl
132 static inline u32 readl(const volatile void __iomem *addr)
135 __asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_readl */"
137 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
144 #define readq_relaxed readq
145 static inline u64 readq(const volatile void __iomem *addr)
148 __asm__ __volatile__("ldxa\t[%1] %2, %0\t/* pci_readq */"
150 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
156 #define writeb writeb
157 #define writeb_relaxed writeb
158 static inline void writeb(u8 b, volatile void __iomem *addr)
160 __asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_writeb */"
162 : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
166 #define writew writew
167 #define writew_relaxed writew
168 static inline void writew(u16 w, volatile void __iomem *addr)
170 __asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_writew */"
172 : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
176 #define writel writel
177 #define writel_relaxed writel
178 static inline void writel(u32 l, volatile void __iomem *addr)
180 __asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_writel */"
182 : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
186 #define writeq writeq
187 #define writeq_relaxed writeq
188 static inline void writeq(u64 q, volatile void __iomem *addr)
190 __asm__ __volatile__("stxa\t%r0, [%1] %2\t/* pci_writeq */"
192 : "Jr" (q), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
197 static inline u8 inb(unsigned long addr)
199 return readb((volatile void __iomem *)addr);
203 static inline u16 inw(unsigned long addr)
205 return readw((volatile void __iomem *)addr);
209 static inline u32 inl(unsigned long addr)
211 return readl((volatile void __iomem *)addr);
215 static inline void outb(u8 b, unsigned long addr)
217 writeb(b, (volatile void __iomem *)addr);
221 static inline void outw(u16 w, unsigned long addr)
223 writew(w, (volatile void __iomem *)addr);
227 static inline void outl(u32 l, unsigned long addr)
229 writel(l, (volatile void __iomem *)addr);
233 #define inb_p(__addr) inb(__addr)
234 #define outb_p(__b, __addr) outb(__b, __addr)
235 #define inw_p(__addr) inw(__addr)
236 #define outw_p(__w, __addr) outw(__w, __addr)
237 #define inl_p(__addr) inl(__addr)
238 #define outl_p(__l, __addr) outl(__l, __addr)
240 void outsb(unsigned long, const void *, unsigned long);
241 void outsw(unsigned long, const void *, unsigned long);
242 void outsl(unsigned long, const void *, unsigned long);
246 void insb(unsigned long, void *, unsigned long);
247 void insw(unsigned long, void *, unsigned long);
248 void insl(unsigned long, void *, unsigned long);
253 static inline void readsb(void __iomem *port, void *buf, unsigned long count)
255 insb((unsigned long __force)port, buf, count);
257 #define readsb readsb
259 static inline void readsw(void __iomem *port, void *buf, unsigned long count)
261 insw((unsigned long __force)port, buf, count);
263 #define readsw readsw
265 static inline void readsl(void __iomem *port, void *buf, unsigned long count)
267 insl((unsigned long __force)port, buf, count);
269 #define readsl readsl
271 static inline void writesb(void __iomem *port, const void *buf, unsigned long count)
273 outsb((unsigned long __force)port, buf, count);
275 #define writesb writesb
277 static inline void writesw(void __iomem *port, const void *buf, unsigned long count)
279 outsw((unsigned long __force)port, buf, count);
281 #define writesw writesw
283 static inline void writesl(void __iomem *port, const void *buf, unsigned long count)
285 outsl((unsigned long __force)port, buf, count);
287 #define writesl writesl
289 #define ioread8_rep(p,d,l) readsb(p,d,l)
290 #define ioread16_rep(p,d,l) readsw(p,d,l)
291 #define ioread32_rep(p,d,l) readsl(p,d,l)
292 #define iowrite8_rep(p,d,l) writesb(p,d,l)
293 #define iowrite16_rep(p,d,l) writesw(p,d,l)
294 #define iowrite32_rep(p,d,l) writesl(p,d,l)
296 /* Valid I/O Space regions are anywhere, because each PCI bus supported
297 * can live in an arbitrary area of the physical address range.
299 #define IO_SPACE_LIMIT 0xffffffffffffffffUL
301 /* Now, SBUS variants, only difference from PCI is that we do
302 * not use little-endian ASIs.
304 static inline u8 sbus_readb(const volatile void __iomem *addr)
306 return __raw_readb(addr);
309 static inline u16 sbus_readw(const volatile void __iomem *addr)
311 return __raw_readw(addr);
314 static inline u32 sbus_readl(const volatile void __iomem *addr)
316 return __raw_readl(addr);
319 static inline u64 sbus_readq(const volatile void __iomem *addr)
321 return __raw_readq(addr);
324 static inline void sbus_writeb(u8 b, volatile void __iomem *addr)
326 __raw_writeb(b, addr);
329 static inline void sbus_writew(u16 w, volatile void __iomem *addr)
331 __raw_writew(w, addr);
334 static inline void sbus_writel(u32 l, volatile void __iomem *addr)
336 __raw_writel(l, addr);
339 static inline void sbus_writeq(u64 q, volatile void __iomem *addr)
341 __raw_writeq(q, addr);
344 static inline void sbus_memset_io(volatile void __iomem *dst, int c, __kernel_size_t n)
352 static inline void memset_io(volatile void __iomem *dst, int c, __kernel_size_t n)
354 volatile void __iomem *d = dst;
361 #define memset_io memset_io
363 static inline void sbus_memcpy_fromio(void *dst, const volatile void __iomem *src,
369 char tmp = sbus_readb(src);
376 static inline void memcpy_fromio(void *dst, const volatile void __iomem *src,
382 char tmp = readb(src);
387 #define memcpy_fromio memcpy_fromio
389 static inline void sbus_memcpy_toio(volatile void __iomem *dst, const void *src,
393 volatile void __iomem *d = dst;
402 static inline void memcpy_toio(volatile void __iomem *dst, const void *src,
406 volatile void __iomem *d = dst;
414 #define memcpy_toio memcpy_toio
418 /* On sparc64 we have the whole physical IO address space accessible
419 * using physically addressed loads and stores, so this does nothing.
421 static inline void __iomem *ioremap(unsigned long offset, unsigned long size)
423 return (void __iomem *)offset;
426 #define ioremap_wc(X,Y) ioremap((X),(Y))
427 #define ioremap_wt(X,Y) ioremap((X),(Y))
428 static inline void __iomem *ioremap_np(unsigned long offset, unsigned long size)
433 #define ioremap_np ioremap_np
435 static inline void iounmap(volatile void __iomem *addr)
439 #define ioread8 readb
440 #define ioread16 readw
441 #define ioread16be __raw_readw
442 #define ioread32 readl
443 #define ioread32be __raw_readl
444 #define iowrite8 writeb
445 #define iowrite16 writew
446 #define iowrite16be __raw_writew
447 #define iowrite32 writel
448 #define iowrite32be __raw_writel
450 /* Create a virtual mapping cookie for an IO port range */
451 void __iomem *ioport_map(unsigned long port, unsigned int nr);
452 void ioport_unmap(void __iomem *);
453 #define ioport_map ioport_map
454 #define ioport_unmap ioport_unmap
456 /* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
458 void pci_iounmap(struct pci_dev *dev, void __iomem *);
459 #define pci_iounmap pci_iounmap
461 static inline int sbus_can_dma_64bit(void)
465 static inline int sbus_can_burst64(void)
470 void sbus_set_sbus64(struct device *, int);
474 #endif /* !(__SPARC64_IO_H) */