1 /* SPDX-License-Identifier: GPL-2.0 */
5 #include <linux/kernel.h>
6 #include <linux/compiler.h>
7 #include <linux/types.h>
9 #include <asm/page.h> /* IO address mapping routines need this */
11 #include <asm-generic/pci_iomap.h>
13 /* BIO layer definitions. */
14 extern unsigned long kern_base, kern_size;
16 /* __raw_{read,write}{b,w,l,q} uses direct access.
17 * Access the memory as big endian bypassing the cache
18 * by using ASI_PHYS_BYPASS_EC_E
20 #define __raw_readb __raw_readb
21 static inline u8 __raw_readb(const volatile void __iomem *addr)
25 __asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_raw_readb */"
27 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
32 #define __raw_readw __raw_readw
33 static inline u16 __raw_readw(const volatile void __iomem *addr)
37 __asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_raw_readw */"
39 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
44 #define __raw_readl __raw_readl
45 static inline u32 __raw_readl(const volatile void __iomem *addr)
49 __asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_raw_readl */"
51 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
56 #define __raw_readq __raw_readq
57 static inline u64 __raw_readq(const volatile void __iomem *addr)
61 __asm__ __volatile__("ldxa\t[%1] %2, %0\t/* pci_raw_readq */"
63 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
68 #define __raw_writeb __raw_writeb
69 static inline void __raw_writeb(u8 b, const volatile void __iomem *addr)
71 __asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_raw_writeb */"
73 : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
76 #define __raw_writew __raw_writew
77 static inline void __raw_writew(u16 w, const volatile void __iomem *addr)
79 __asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_raw_writew */"
81 : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
84 #define __raw_writel __raw_writel
85 static inline void __raw_writel(u32 l, const volatile void __iomem *addr)
87 __asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_raw_writel */"
89 : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
92 #define __raw_writeq __raw_writeq
93 static inline void __raw_writeq(u64 q, const volatile void __iomem *addr)
95 __asm__ __volatile__("stxa\t%r0, [%1] %2\t/* pci_raw_writeq */"
97 : "Jr" (q), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
100 /* Memory functions, same as I/O accesses on Ultra.
101 * Access memory as little endian bypassing
102 * the cache by using ASI_PHYS_BYPASS_EC_E_L
105 #define readb_relaxed readb
106 static inline u8 readb(const volatile void __iomem *addr)
109 __asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_readb */"
111 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
117 #define readw_relaxed readw
118 static inline u16 readw(const volatile void __iomem *addr)
121 __asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_readw */"
123 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
130 #define readl_relaxed readl
131 static inline u32 readl(const volatile void __iomem *addr)
134 __asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_readl */"
136 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
143 #define readq_relaxed readq
144 static inline u64 readq(const volatile void __iomem *addr)
147 __asm__ __volatile__("ldxa\t[%1] %2, %0\t/* pci_readq */"
149 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
155 #define writeb writeb
156 #define writeb_relaxed writeb
157 static inline void writeb(u8 b, volatile void __iomem *addr)
159 __asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_writeb */"
161 : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
165 #define writew writew
166 #define writew_relaxed writew
167 static inline void writew(u16 w, volatile void __iomem *addr)
169 __asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_writew */"
171 : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
175 #define writel writel
176 #define writel_relaxed writel
177 static inline void writel(u32 l, volatile void __iomem *addr)
179 __asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_writel */"
181 : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
185 #define writeq writeq
186 #define writeq_relaxed writeq
187 static inline void writeq(u64 q, volatile void __iomem *addr)
189 __asm__ __volatile__("stxa\t%r0, [%1] %2\t/* pci_writeq */"
191 : "Jr" (q), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
196 static inline u8 inb(unsigned long addr)
198 return readb((volatile void __iomem *)addr);
202 static inline u16 inw(unsigned long addr)
204 return readw((volatile void __iomem *)addr);
208 static inline u32 inl(unsigned long addr)
210 return readl((volatile void __iomem *)addr);
214 static inline void outb(u8 b, unsigned long addr)
216 writeb(b, (volatile void __iomem *)addr);
220 static inline void outw(u16 w, unsigned long addr)
222 writew(w, (volatile void __iomem *)addr);
226 static inline void outl(u32 l, unsigned long addr)
228 writel(l, (volatile void __iomem *)addr);
232 #define inb_p(__addr) inb(__addr)
233 #define outb_p(__b, __addr) outb(__b, __addr)
234 #define inw_p(__addr) inw(__addr)
235 #define outw_p(__w, __addr) outw(__w, __addr)
236 #define inl_p(__addr) inl(__addr)
237 #define outl_p(__l, __addr) outl(__l, __addr)
239 void outsb(unsigned long, const void *, unsigned long);
240 void outsw(unsigned long, const void *, unsigned long);
241 void outsl(unsigned long, const void *, unsigned long);
242 void insb(unsigned long, void *, unsigned long);
243 void insw(unsigned long, void *, unsigned long);
244 void insl(unsigned long, void *, unsigned long);
246 static inline void readsb(void __iomem *port, void *buf, unsigned long count)
248 insb((unsigned long __force)port, buf, count);
250 static inline void readsw(void __iomem *port, void *buf, unsigned long count)
252 insw((unsigned long __force)port, buf, count);
255 static inline void readsl(void __iomem *port, void *buf, unsigned long count)
257 insl((unsigned long __force)port, buf, count);
260 static inline void writesb(void __iomem *port, const void *buf, unsigned long count)
262 outsb((unsigned long __force)port, buf, count);
265 static inline void writesw(void __iomem *port, const void *buf, unsigned long count)
267 outsw((unsigned long __force)port, buf, count);
270 static inline void writesl(void __iomem *port, const void *buf, unsigned long count)
272 outsl((unsigned long __force)port, buf, count);
275 #define ioread8_rep(p,d,l) readsb(p,d,l)
276 #define ioread16_rep(p,d,l) readsw(p,d,l)
277 #define ioread32_rep(p,d,l) readsl(p,d,l)
278 #define iowrite8_rep(p,d,l) writesb(p,d,l)
279 #define iowrite16_rep(p,d,l) writesw(p,d,l)
280 #define iowrite32_rep(p,d,l) writesl(p,d,l)
282 /* Valid I/O Space regions are anywhere, because each PCI bus supported
283 * can live in an arbitrary area of the physical address range.
285 #define IO_SPACE_LIMIT 0xffffffffffffffffUL
287 /* Now, SBUS variants, only difference from PCI is that we do
288 * not use little-endian ASIs.
290 static inline u8 sbus_readb(const volatile void __iomem *addr)
292 return __raw_readb(addr);
295 static inline u16 sbus_readw(const volatile void __iomem *addr)
297 return __raw_readw(addr);
300 static inline u32 sbus_readl(const volatile void __iomem *addr)
302 return __raw_readl(addr);
305 static inline u64 sbus_readq(const volatile void __iomem *addr)
307 return __raw_readq(addr);
310 static inline void sbus_writeb(u8 b, volatile void __iomem *addr)
312 __raw_writeb(b, addr);
315 static inline void sbus_writew(u16 w, volatile void __iomem *addr)
317 __raw_writew(w, addr);
320 static inline void sbus_writel(u32 l, volatile void __iomem *addr)
322 __raw_writel(l, addr);
325 static inline void sbus_writeq(u64 q, volatile void __iomem *addr)
327 __raw_writeq(q, addr);
330 static inline void sbus_memset_io(volatile void __iomem *dst, int c, __kernel_size_t n)
338 static inline void memset_io(volatile void __iomem *dst, int c, __kernel_size_t n)
340 volatile void __iomem *d = dst;
348 static inline void sbus_memcpy_fromio(void *dst, const volatile void __iomem *src,
354 char tmp = sbus_readb(src);
361 static inline void memcpy_fromio(void *dst, const volatile void __iomem *src,
367 char tmp = readb(src);
373 static inline void sbus_memcpy_toio(volatile void __iomem *dst, const void *src,
377 volatile void __iomem *d = dst;
386 static inline void memcpy_toio(volatile void __iomem *dst, const void *src,
390 volatile void __iomem *d = dst;
403 /* On sparc64 we have the whole physical IO address space accessible
404 * using physically addressed loads and stores, so this does nothing.
406 static inline void __iomem *ioremap(unsigned long offset, unsigned long size)
408 return (void __iomem *)offset;
411 #define ioremap_nocache(X,Y) ioremap((X),(Y))
412 #define ioremap_uc(X,Y) ioremap((X),(Y))
413 #define ioremap_wc(X,Y) ioremap((X),(Y))
414 #define ioremap_wt(X,Y) ioremap((X),(Y))
416 static inline void iounmap(volatile void __iomem *addr)
420 #define ioread8 readb
421 #define ioread16 readw
422 #define ioread16be __raw_readw
423 #define ioread32 readl
424 #define ioread32be __raw_readl
425 #define iowrite8 writeb
426 #define iowrite16 writew
427 #define iowrite16be __raw_writew
428 #define iowrite32 writel
429 #define iowrite32be __raw_writel
431 /* Create a virtual mapping cookie for an IO port range */
432 void __iomem *ioport_map(unsigned long port, unsigned int nr);
433 void ioport_unmap(void __iomem *);
435 /* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
437 void pci_iounmap(struct pci_dev *dev, void __iomem *);
439 static inline int sbus_can_dma_64bit(void)
443 static inline int sbus_can_burst64(void)
448 void sbus_set_sbus64(struct device *, int);
451 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
454 #define xlate_dev_mem_ptr(p) __va(p)
457 * Convert a virtual cached pointer to an uncached pointer
459 #define xlate_dev_kmem_ptr(p) p
463 #endif /* !(__SPARC64_IO_H) */