1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _SPARC64_HYPERVISOR_H
3 #define _SPARC64_HYPERVISOR_H
5 /* Sun4v hypervisor interfaces and defines.
7 * Hypervisor calls are made via traps to software traps number 0x80
8 * and above. Registers %o0 to %o5 serve as argument, status, and
9 * return value registers.
11 * There are two kinds of these traps. First there are the normal
12 * "fast traps" which use software trap 0x80 and encode the function
13 * to invoke by number in register %o5. Argument and return value
14 * handling is as follows:
16 * -----------------------------------------------
17 * | %o5 | function number | undefined |
18 * | %o0 | argument 0 | return status |
19 * | %o1 | argument 1 | return value 1 |
20 * | %o2 | argument 2 | return value 2 |
21 * | %o3 | argument 3 | return value 3 |
22 * | %o4 | argument 4 | return value 4 |
23 * -----------------------------------------------
25 * The second type are "hyper-fast traps" which encode the function
26 * number in the software trap number itself. So these use trap
27 * numbers > 0x80. The register usage for hyper-fast traps is as
30 * -----------------------------------------------
31 * | %o0 | argument 0 | return status |
32 * | %o1 | argument 1 | return value 1 |
33 * | %o2 | argument 2 | return value 2 |
34 * | %o3 | argument 3 | return value 3 |
35 * | %o4 | argument 4 | return value 4 |
36 * -----------------------------------------------
38 * Registers providing explicit arguments to the hypervisor calls
39 * are volatile across the call. Upon return their values are
40 * undefined unless explicitly specified as containing a particular
41 * return value by the specific call. The return status is always
42 * returned in register %o0, zero indicates a successful execution of
43 * the hypervisor call and other values indicate an error status as
44 * defined below. So, for example, if a hyper-fast trap takes
45 * arguments 0, 1, and 2, then %o0, %o1, and %o2 are volatile across
46 * the call and %o3, %o4, and %o5 would be preserved.
48 * If the hypervisor trap is invalid, or the fast trap function number
49 * is invalid, HV_EBADTRAP will be returned in %o0. Also, all 64-bits
50 * of the argument and return values are significant.
54 #define HV_FAST_TRAP 0x80
55 #define HV_MMU_MAP_ADDR_TRAP 0x83
56 #define HV_MMU_UNMAP_ADDR_TRAP 0x84
57 #define HV_TTRACE_ADDENTRY_TRAP 0x85
58 #define HV_CORE_TRAP 0xff
61 #define HV_EOK 0 /* Successful return */
62 #define HV_ENOCPU 1 /* Invalid CPU id */
63 #define HV_ENORADDR 2 /* Invalid real address */
64 #define HV_ENOINTR 3 /* Invalid interrupt id */
65 #define HV_EBADPGSZ 4 /* Invalid pagesize encoding */
66 #define HV_EBADTSB 5 /* Invalid TSB description */
67 #define HV_EINVAL 6 /* Invalid argument */
68 #define HV_EBADTRAP 7 /* Invalid function number */
69 #define HV_EBADALIGN 8 /* Invalid address alignment */
70 #define HV_EWOULDBLOCK 9 /* Cannot complete w/o blocking */
71 #define HV_ENOACCESS 10 /* No access to resource */
72 #define HV_EIO 11 /* I/O error */
73 #define HV_ECPUERROR 12 /* CPU in error state */
74 #define HV_ENOTSUPPORTED 13 /* Function not supported */
75 #define HV_ENOMAP 14 /* No mapping found */
76 #define HV_ETOOMANY 15 /* Too many items specified */
77 #define HV_ECHANNEL 16 /* Invalid LDC channel */
78 #define HV_EBUSY 17 /* Resource busy */
82 * FUNCTION: HV_FAST_MACH_EXIT
84 * ERRORS: This service does not return.
86 * Stop all CPUs in the virtual domain and place them into the stopped
87 * state. The 64-bit exit code may be passed to a service entity as
88 * the domain's exit status. On systems without a service entity, the
89 * domain will undergo a reset, and the boot firmware will be
92 * This function will never return to the guest that invokes it.
94 * Note: By convention an exit code of zero denotes a successful exit by
95 * the guest code. A non-zero exit code denotes a guest specific
99 #define HV_FAST_MACH_EXIT 0x00
102 void sun4v_mach_exit(unsigned long exit_code);
105 /* Domain services. */
109 * FUNCTION: HV_FAST_MACH_DESC
114 * ERRORS: HV_EBADALIGN Buffer is badly aligned
115 * HV_ENORADDR Buffer is to an illegal real address.
116 * HV_EINVAL Buffer length is too small for complete
117 * machine description.
119 * Copy the most current machine description into the buffer indicated
120 * by the real address in ARG0. The buffer provided must be 16 byte
121 * aligned. Upon success or HV_EINVAL, this service returns the
122 * actual size of the machine description in the RET1 return value.
124 * Note: A method of determining the appropriate buffer size for the
125 * machine description is to first call this service with a buffer
128 #define HV_FAST_MACH_DESC 0x01
131 unsigned long sun4v_mach_desc(unsigned long buffer_pa,
132 unsigned long buf_len,
133 unsigned long *real_buf_len);
138 * FUNCTION: HV_FAST_MACH_SIR
139 * ERRORS: This service does not return.
141 * Perform a software initiated reset of the virtual machine domain.
142 * All CPUs are captured as soon as possible, all hardware devices are
143 * returned to the entry default state, and the domain is restarted at
144 * the SIR (trap type 0x04) real trap table (RTBA) entry point on one
145 * of the CPUs. The single CPU restarted is selected as determined by
146 * platform specific policy. Memory is preserved across this
149 #define HV_FAST_MACH_SIR 0x02
152 void sun4v_mach_sir(void);
155 /* mach_set_watchdog()
157 * FUNCTION: HV_FAST_MACH_SET_WATCHDOG
158 * ARG0: timeout in milliseconds
160 * RET1: time remaining in milliseconds
162 * A guest uses this API to set a watchdog timer. Once the gues has set
163 * the timer, it must call the timer service again either to disable or
164 * postpone the expiration. If the timer expires before being reset or
165 * disabled, then the hypervisor take a platform specific action leading
166 * to guest termination within a bounded time period. The platform action
167 * may include recovery actions such as reporting the expiration to a
168 * Service Processor, and/or automatically restarting the gues.
170 * The 'timeout' parameter is specified in milliseconds, however the
171 * implementated granularity is given by the 'watchdog-resolution'
172 * property in the 'platform' node of the guest's machine description.
173 * The largest allowed timeout value is specified by the
174 * 'watchdog-max-timeout' property of the 'platform' node.
176 * If the 'timeout' argument is not zero, the watchdog timer is set to
177 * expire after a minimum of 'timeout' milliseconds.
179 * If the 'timeout' argument is zero, the watchdog timer is disabled.
181 * If the 'timeout' value exceeds the value of the 'max-watchdog-timeout'
182 * property, the hypervisor leaves the watchdog timer state unchanged,
183 * and returns a status of EINVAL.
185 * The 'time remaining' return value is valid regardless of whether the
186 * return status is EOK or EINVAL. A non-zero return value indicates the
187 * number of milliseconds that were remaining until the timer was to expire.
188 * If less than one millisecond remains, the return value is '1'. If the
189 * watchdog timer was disabled at the time of the call, the return value is
192 * If the hypervisor cannot support the exact timeout value requested, but
193 * can support a larger timeout value, the hypervisor may round the actual
194 * timeout to a value larger than the requested timeout, consequently the
195 * 'time remaining' return value may be larger than the previously requested
198 * Any guest OS debugger should be aware that the watchdog service may be in
199 * use. Consequently, it is recommended that the watchdog service is
200 * disabled upon debugger entry (e.g. reaching a breakpoint), and then
201 * re-enabled upon returning to normal execution. The API has been designed
202 * with this in mind, and the 'time remaining' result of the disable call may
203 * be used directly as the timeout argument of the re-enable call.
205 #define HV_FAST_MACH_SET_WATCHDOG 0x05
208 unsigned long sun4v_mach_set_watchdog(unsigned long timeout,
209 unsigned long *orig_timeout);
214 * CPUs represent devices that can execute software threads. A single
215 * chip that contains multiple cores or strands is represented as
216 * multiple CPUs with unique CPU identifiers. CPUs are exported to
217 * OBP via the machine description (and to the OS via the OBP device
218 * tree). CPUs are always in one of three states: stopped, running,
221 * A CPU ID is a pre-assigned 16-bit value that uniquely identifies a
222 * CPU within a logical domain. Operations that are to be performed
223 * on multiple CPUs specify them via a CPU list. A CPU list is an
224 * array in real memory, of which each 16-bit word is a CPU ID. CPU
225 * lists are passed through the API as two arguments. The first is
226 * the number of entries (16-bit words) in the CPU list, and the
227 * second is the (real address) pointer to the CPU ID list.
232 * FUNCTION: HV_FAST_CPU_START
238 * ERRORS: ENOCPU Invalid CPU ID
239 * EINVAL Target CPU ID is not in the stopped state
240 * ENORADDR Invalid PC or RTBA real address
241 * EBADALIGN Unaligned PC or unaligned RTBA
242 * EWOULDBLOCK Starting resources are not available
244 * Start CPU with given CPU ID with PC in %pc and with a real trap
245 * base address value of RTBA. The indicated CPU must be in the
246 * stopped state. The supplied RTBA must be aligned on a 256 byte
247 * boundary. On successful completion, the specified CPU will be in
248 * the running state and will be supplied with "target ARG0" in %o0
251 #define HV_FAST_CPU_START 0x10
254 unsigned long sun4v_cpu_start(unsigned long cpuid,
262 * FUNCTION: HV_FAST_CPU_STOP
265 * ERRORS: ENOCPU Invalid CPU ID
266 * EINVAL Target CPU ID is the current cpu
267 * EINVAL Target CPU ID is not in the running state
268 * EWOULDBLOCK Stopping resources are not available
269 * ENOTSUPPORTED Not supported on this platform
271 * The specified CPU is stopped. The indicated CPU must be in the
272 * running state. On completion, it will be in the stopped state. It
273 * is not legal to stop the current CPU.
275 * Note: As this service cannot be used to stop the current cpu, this service
276 * may not be used to stop the last running CPU in a domain. To stop
277 * and exit a running domain, a guest must use the mach_exit() service.
279 #define HV_FAST_CPU_STOP 0x11
282 unsigned long sun4v_cpu_stop(unsigned long cpuid);
287 * FUNCTION: HV_FAST_CPU_YIELD
289 * ERRORS: No possible error.
291 * Suspend execution on the current CPU. Execution will resume when
292 * an interrupt (device, %stick_compare, or cross-call) is targeted to
293 * the CPU. On some CPUs, this API may be used by the hypervisor to
294 * save power by disabling hardware strands.
296 #define HV_FAST_CPU_YIELD 0x12
299 unsigned long sun4v_cpu_yield(void);
304 * FUNCTION: HV_FAST_CPU_POKE
306 * ERRORS: ENOCPU cpuid refers to a CPU that does not exist
307 * EINVAL cpuid is current CPU
309 * Poke CPU cpuid. If the target CPU is currently suspended having
310 * invoked the cpu-yield service, that vCPU will be resumed.
311 * Poke interrupts may only be sent to valid, non-local CPUs.
312 * It is not legal to poke the current vCPU.
314 #define HV_FAST_CPU_POKE 0x13
317 unsigned long sun4v_cpu_poke(unsigned long cpuid);
322 * FUNCTION: HV_FAST_CPU_QCONF
324 * ARG1: base real address
325 * ARG2: number of entries
327 * ERRORS: ENORADDR Invalid base real address
328 * EINVAL Invalid queue or number of entries is less
329 * than 2 or too large.
330 * EBADALIGN Base real address is not correctly aligned
333 * Configure the given queue to be placed at the given base real
334 * address, with the given number of entries. The number of entries
335 * must be a power of 2. The base real address must be aligned
336 * exactly to match the queue size. Each queue entry is 64 bytes
337 * long, so for example a 32 entry queue must be aligned on a 2048
338 * byte real address boundary.
340 * The specified queue is unconfigured if the number of entries is given
343 * For the current version of this API service, the argument queue is defined
347 * ----- -------------------------
348 * 0x3c cpu mondo queue
349 * 0x3d device mondo queue
350 * 0x3e resumable error queue
351 * 0x3f non-resumable error queue
353 * Note: The maximum number of entries for each queue for a specific cpu may
354 * be determined from the machine description.
356 #define HV_FAST_CPU_QCONF 0x14
357 #define HV_CPU_QUEUE_CPU_MONDO 0x3c
358 #define HV_CPU_QUEUE_DEVICE_MONDO 0x3d
359 #define HV_CPU_QUEUE_RES_ERROR 0x3e
360 #define HV_CPU_QUEUE_NONRES_ERROR 0x3f
363 unsigned long sun4v_cpu_qconf(unsigned long type,
364 unsigned long queue_paddr,
365 unsigned long num_queue_entries);
370 * FUNCTION: HV_FAST_CPU_QINFO
373 * RET1: base real address
374 * RET1: number of entries
375 * ERRORS: EINVAL Invalid queue
377 * Return the configuration info for the given queue. The base real
378 * address and number of entries of the defined queue are returned.
379 * The queue argument values are the same as for cpu_qconf() above.
381 * If the specified queue is a valid queue number, but no queue has
382 * been defined, the number of entries will be set to zero and the
383 * base real address returned is undefined.
385 #define HV_FAST_CPU_QINFO 0x15
389 * FUNCTION: HV_FAST_CPU_MONDO_SEND
391 * ARG2: data real address
393 * ERRORS: EBADALIGN Mondo data is not 64-byte aligned or CPU list
394 * is not 2-byte aligned.
395 * ENORADDR Invalid data mondo address, or invalid cpu list
397 * ENOCPU Invalid cpu in CPU list
398 * EWOULDBLOCK Some or all of the listed CPUs did not receive
400 * ECPUERROR One or more of the listed CPUs are in error
401 * state, use HV_FAST_CPU_STATE to see which ones
402 * EINVAL CPU list includes caller's CPU ID
404 * Send a mondo interrupt to the CPUs in the given CPU list with the
405 * 64-bytes at the given data real address. The data must be 64-byte
406 * aligned. The mondo data will be delivered to the cpu_mondo queues
407 * of the recipient CPUs.
409 * In all cases, error or not, the CPUs in the CPU list to which the
410 * mondo has been successfully delivered will be indicated by having
411 * their entry in CPU list updated with the value 0xffff.
413 #define HV_FAST_CPU_MONDO_SEND 0x42
416 unsigned long sun4v_cpu_mondo_send(unsigned long cpu_count,
417 unsigned long cpu_list_pa,
418 unsigned long mondo_block_pa);
423 * FUNCTION: HV_FAST_CPU_MYID
426 * ERRORS: No errors defined.
428 * Return the hypervisor ID handle for the current CPU. Use by a
429 * virtual CPU to discover it's own identity.
431 #define HV_FAST_CPU_MYID 0x16
435 * FUNCTION: HV_FAST_CPU_STATE
439 * ERRORS: ENOCPU Invalid CPU ID
441 * Retrieve the current state of the CPU with the given CPU ID.
443 #define HV_FAST_CPU_STATE 0x17
444 #define HV_CPU_STATE_STOPPED 0x01
445 #define HV_CPU_STATE_RUNNING 0x02
446 #define HV_CPU_STATE_ERROR 0x03
449 long sun4v_cpu_state(unsigned long cpuid);
454 * FUNCTION: HV_FAST_CPU_SET_RTBA
457 * RET1: previous RTBA
458 * ERRORS: ENORADDR Invalid RTBA real address
459 * EBADALIGN RTBA is incorrectly aligned for a trap table
461 * Set the real trap base address of the local cpu to the given RTBA.
462 * The supplied RTBA must be aligned on a 256 byte boundary. Upon
463 * success the previous value of the RTBA is returned in RET1.
465 * Note: This service does not affect %tba
467 #define HV_FAST_CPU_SET_RTBA 0x18
471 * FUNCTION: HV_FAST_CPU_GET_RTBA
473 * RET1: previous RTBA
474 * ERRORS: No possible error.
476 * Returns the current value of RTBA in RET1.
478 #define HV_FAST_CPU_GET_RTBA 0x19
482 * Layout of a TSB description for mmu_tsb_ctx{,non}0() calls.
485 struct hv_tsb_descr {
486 unsigned short pgsz_idx;
487 unsigned short assoc;
488 unsigned int num_ttes; /* in TTEs */
489 unsigned int ctx_idx;
490 unsigned int pgsz_mask;
491 unsigned long tsb_base;
495 #define HV_TSB_DESCR_PGSZ_IDX_OFFSET 0x00
496 #define HV_TSB_DESCR_ASSOC_OFFSET 0x02
497 #define HV_TSB_DESCR_NUM_TTES_OFFSET 0x04
498 #define HV_TSB_DESCR_CTX_IDX_OFFSET 0x08
499 #define HV_TSB_DESCR_PGSZ_MASK_OFFSET 0x0c
500 #define HV_TSB_DESCR_TSB_BASE_OFFSET 0x10
501 #define HV_TSB_DESCR_RESV_OFFSET 0x18
503 /* Page size bitmask. */
504 #define HV_PGSZ_MASK_8K (1 << 0)
505 #define HV_PGSZ_MASK_64K (1 << 1)
506 #define HV_PGSZ_MASK_512K (1 << 2)
507 #define HV_PGSZ_MASK_4MB (1 << 3)
508 #define HV_PGSZ_MASK_32MB (1 << 4)
509 #define HV_PGSZ_MASK_256MB (1 << 5)
510 #define HV_PGSZ_MASK_2GB (1 << 6)
511 #define HV_PGSZ_MASK_16GB (1 << 7)
513 /* Page size index. The value given in the TSB descriptor must correspond
514 * to the smallest page size specified in the pgsz_mask page size bitmask.
516 #define HV_PGSZ_IDX_8K 0
517 #define HV_PGSZ_IDX_64K 1
518 #define HV_PGSZ_IDX_512K 2
519 #define HV_PGSZ_IDX_4MB 3
520 #define HV_PGSZ_IDX_32MB 4
521 #define HV_PGSZ_IDX_256MB 5
522 #define HV_PGSZ_IDX_2GB 6
523 #define HV_PGSZ_IDX_16GB 7
525 /* MMU fault status area.
527 * MMU related faults have their status and fault address information
528 * placed into a memory region made available by privileged code. Each
529 * virtual processor must make a mmu_fault_area_conf() call to tell the
530 * hypervisor where that processor's fault status should be stored.
532 * The fault status block is a multiple of 64-bytes and must be aligned
533 * on a 64-byte boundary.
536 struct hv_fault_status {
537 unsigned long i_fault_type;
538 unsigned long i_fault_addr;
539 unsigned long i_fault_ctx;
540 unsigned long i_reserved[5];
541 unsigned long d_fault_type;
542 unsigned long d_fault_addr;
543 unsigned long d_fault_ctx;
544 unsigned long d_reserved[5];
547 #define HV_FAULT_I_TYPE_OFFSET 0x00
548 #define HV_FAULT_I_ADDR_OFFSET 0x08
549 #define HV_FAULT_I_CTX_OFFSET 0x10
550 #define HV_FAULT_D_TYPE_OFFSET 0x40
551 #define HV_FAULT_D_ADDR_OFFSET 0x48
552 #define HV_FAULT_D_CTX_OFFSET 0x50
554 #define HV_FAULT_TYPE_FAST_MISS 1
555 #define HV_FAULT_TYPE_FAST_PROT 2
556 #define HV_FAULT_TYPE_MMU_MISS 3
557 #define HV_FAULT_TYPE_INV_RA 4
558 #define HV_FAULT_TYPE_PRIV_VIOL 5
559 #define HV_FAULT_TYPE_PROT_VIOL 6
560 #define HV_FAULT_TYPE_NFO 7
561 #define HV_FAULT_TYPE_NFO_SEFF 8
562 #define HV_FAULT_TYPE_INV_VA 9
563 #define HV_FAULT_TYPE_INV_ASI 10
564 #define HV_FAULT_TYPE_NC_ATOMIC 11
565 #define HV_FAULT_TYPE_PRIV_ACT 12
566 #define HV_FAULT_TYPE_RESV1 13
567 #define HV_FAULT_TYPE_UNALIGNED 14
568 #define HV_FAULT_TYPE_INV_PGSZ 15
569 /* Values 16 --> -2 are reserved. */
570 #define HV_FAULT_TYPE_MULTIPLE -1
572 /* Flags argument for mmu_{map,unmap}_addr(), mmu_demap_{page,context,all}(),
573 * and mmu_{map,unmap}_perm_addr().
575 #define HV_MMU_DMMU 0x01
576 #define HV_MMU_IMMU 0x02
577 #define HV_MMU_ALL (HV_MMU_DMMU | HV_MMU_IMMU)
580 * TRAP: HV_MMU_MAP_ADDR_TRAP
581 * ARG0: virtual address
584 * ARG3: flags (HV_MMU_{IMMU,DMMU})
585 * ERRORS: EINVAL Invalid virtual address, mmu context, or flags
586 * EBADPGSZ Invalid page size value
587 * ENORADDR Invalid real address in TTE
589 * Create a non-permanent mapping using the given TTE, virtual
590 * address, and mmu context. The flags argument determines which
591 * (data, or instruction, or both) TLB the mapping gets loaded into.
593 * The behavior is undefined if the valid bit is clear in the TTE.
595 * Note: This API call is for privileged code to specify temporary translation
596 * mappings without the need to create and manage a TSB.
600 * TRAP: HV_MMU_UNMAP_ADDR_TRAP
601 * ARG0: virtual address
603 * ARG2: flags (HV_MMU_{IMMU,DMMU})
604 * ERRORS: EINVAL Invalid virtual address, mmu context, or flags
606 * Demaps the given virtual address in the given mmu context on this
607 * CPU. This function is intended to be used to demap pages mapped
608 * with mmu_map_addr. This service is equivalent to invoking
609 * mmu_demap_page() with only the current CPU in the CPU list. The
610 * flags argument determines which (data, or instruction, or both) TLB
611 * the mapping gets unmapped from.
613 * Attempting to perform an unmap operation for a previously defined
614 * permanent mapping will have undefined results.
619 * FUNCTION: HV_FAST_MMU_TSB_CTX0
620 * ARG0: number of TSB descriptions
621 * ARG1: TSB descriptions pointer
623 * ERRORS: ENORADDR Invalid TSB descriptions pointer or
624 * TSB base within a descriptor
625 * EBADALIGN TSB descriptions pointer is not aligned
626 * to an 8-byte boundary, or TSB base
627 * within a descriptor is not aligned for
629 * EBADPGSZ Invalid page size in a TSB descriptor
630 * EBADTSB Invalid associativity or size in a TSB
632 * EINVAL Invalid number of TSB descriptions, or
633 * invalid context index in a TSB
634 * descriptor, or index page size not
635 * equal to smallest page size in page
636 * size bitmask field.
638 * Configures the TSBs for the current CPU for virtual addresses with
639 * context zero. The TSB descriptions pointer is a pointer to an
640 * array of the given number of TSB descriptions.
642 * Note: The maximum number of TSBs available to a virtual CPU is given by the
643 * mmu-max-#tsbs property of the cpu's corresponding "cpu" node in the
644 * machine description.
646 #define HV_FAST_MMU_TSB_CTX0 0x20
649 unsigned long sun4v_mmu_tsb_ctx0(unsigned long num_descriptions,
650 unsigned long tsb_desc_ra);
655 * FUNCTION: HV_FAST_MMU_TSB_CTXNON0
656 * ARG0: number of TSB descriptions
657 * ARG1: TSB descriptions pointer
659 * ERRORS: Same as for mmu_tsb_ctx0() above.
661 * Configures the TSBs for the current CPU for virtual addresses with
662 * non-zero contexts. The TSB descriptions pointer is a pointer to an
663 * array of the given number of TSB descriptions.
665 * Note: A maximum of 16 TSBs may be specified in the TSB description list.
667 #define HV_FAST_MMU_TSB_CTXNON0 0x21
671 * FUNCTION: HV_FAST_MMU_DEMAP_PAGE
672 * ARG0: reserved, must be zero
673 * ARG1: reserved, must be zero
674 * ARG2: virtual address
676 * ARG4: flags (HV_MMU_{IMMU,DMMU})
678 * ERRORS: EINVAL Invalid virtual address, context, or
680 * ENOTSUPPORTED ARG0 or ARG1 is non-zero
682 * Demaps any page mapping of the given virtual address in the given
683 * mmu context for the current virtual CPU. Any virtually tagged
684 * caches are guaranteed to be kept consistent. The flags argument
685 * determines which TLB (instruction, or data, or both) participate in
688 * ARG0 and ARG1 are both reserved and must be set to zero.
690 #define HV_FAST_MMU_DEMAP_PAGE 0x22
694 * FUNCTION: HV_FAST_MMU_DEMAP_CTX
695 * ARG0: reserved, must be zero
696 * ARG1: reserved, must be zero
698 * ARG3: flags (HV_MMU_{IMMU,DMMU})
700 * ERRORS: EINVAL Invalid context or flags value
701 * ENOTSUPPORTED ARG0 or ARG1 is non-zero
703 * Demaps all non-permanent virtual page mappings previously specified
704 * for the given context for the current virtual CPU. Any virtual
705 * tagged caches are guaranteed to be kept consistent. The flags
706 * argument determines which TLB (instruction, or data, or both)
707 * participate in the operation.
709 * ARG0 and ARG1 are both reserved and must be set to zero.
711 #define HV_FAST_MMU_DEMAP_CTX 0x23
715 * FUNCTION: HV_FAST_MMU_DEMAP_ALL
716 * ARG0: reserved, must be zero
717 * ARG1: reserved, must be zero
718 * ARG2: flags (HV_MMU_{IMMU,DMMU})
720 * ERRORS: EINVAL Invalid flags value
721 * ENOTSUPPORTED ARG0 or ARG1 is non-zero
723 * Demaps all non-permanent virtual page mappings previously specified
724 * for the current virtual CPU. Any virtual tagged caches are
725 * guaranteed to be kept consistent. The flags argument determines
726 * which TLB (instruction, or data, or both) participate in the
729 * ARG0 and ARG1 are both reserved and must be set to zero.
731 #define HV_FAST_MMU_DEMAP_ALL 0x24
734 void sun4v_mmu_demap_all(void);
737 /* mmu_map_perm_addr()
739 * FUNCTION: HV_FAST_MMU_MAP_PERM_ADDR
740 * ARG0: virtual address
741 * ARG1: reserved, must be zero
743 * ARG3: flags (HV_MMU_{IMMU,DMMU})
745 * ERRORS: EINVAL Invalid virtual address or flags value
746 * EBADPGSZ Invalid page size value
747 * ENORADDR Invalid real address in TTE
748 * ETOOMANY Too many mappings (max of 8 reached)
750 * Create a permanent mapping using the given TTE and virtual address
751 * for context 0 on the calling virtual CPU. A maximum of 8 such
752 * permanent mappings may be specified by privileged code. Mappings
753 * may be removed with mmu_unmap_perm_addr().
755 * The behavior is undefined if a TTE with the valid bit clear is given.
757 * Note: This call is used to specify address space mappings for which
758 * privileged code does not expect to receive misses. For example,
759 * this mechanism can be used to map kernel nucleus code and data.
761 #define HV_FAST_MMU_MAP_PERM_ADDR 0x25
764 unsigned long sun4v_mmu_map_perm_addr(unsigned long vaddr,
765 unsigned long set_to_zero,
767 unsigned long flags);
770 /* mmu_fault_area_conf()
772 * FUNCTION: HV_FAST_MMU_FAULT_AREA_CONF
775 * RET1: previous mmu fault area real address
776 * ERRORS: ENORADDR Invalid real address
777 * EBADALIGN Invalid alignment for fault area
779 * Configure the MMU fault status area for the calling CPU. A 64-byte
780 * aligned real address specifies where MMU fault status information
781 * is placed. The return value is the previously specified area, or 0
782 * for the first invocation. Specifying a fault area at real address
785 #define HV_FAST_MMU_FAULT_AREA_CONF 0x26
789 * FUNCTION: HV_FAST_MMU_ENABLE
791 * ARG1: return target address
793 * ERRORS: ENORADDR Invalid real address when disabling
795 * EBADALIGN The return target address is not
796 * aligned to an instruction.
797 * EINVAL The enable flag request the current
798 * operating mode (e.g. disable if already
801 * Enable or disable virtual address translation for the calling CPU
802 * within the virtual machine domain. If the enable flag is zero,
803 * translation is disabled, any non-zero value will enable
806 * When this function returns, the newly selected translation mode
807 * will be active. If the mmu is being enabled, then the return
808 * target address is a virtual address else it is a real address.
810 * Upon successful completion, control will be returned to the given
811 * return target address (ie. the cpu will jump to that address). On
812 * failure, the previous mmu mode remains and the trap simply returns
813 * as normal with the appropriate error code in RET0.
815 #define HV_FAST_MMU_ENABLE 0x27
817 /* mmu_unmap_perm_addr()
819 * FUNCTION: HV_FAST_MMU_UNMAP_PERM_ADDR
820 * ARG0: virtual address
821 * ARG1: reserved, must be zero
822 * ARG2: flags (HV_MMU_{IMMU,DMMU})
824 * ERRORS: EINVAL Invalid virtual address or flags value
825 * ENOMAP Specified mapping was not found
827 * Demaps any permanent page mapping (established via
828 * mmu_map_perm_addr()) at the given virtual address for context 0 on
829 * the current virtual CPU. Any virtual tagged caches are guaranteed
830 * to be kept consistent.
832 #define HV_FAST_MMU_UNMAP_PERM_ADDR 0x28
834 /* mmu_tsb_ctx0_info()
836 * FUNCTION: HV_FAST_MMU_TSB_CTX0_INFO
838 * ARG1: buffer pointer
840 * RET1: number of TSBs
841 * ERRORS: EINVAL Supplied buffer is too small
842 * EBADALIGN The buffer pointer is badly aligned
843 * ENORADDR Invalid real address for buffer pointer
845 * Return the TSB configuration as previous defined by mmu_tsb_ctx0()
846 * into the provided buffer. The size of the buffer is given in ARG1
847 * in terms of the number of TSB description entries.
849 * Upon return, RET1 always contains the number of TSB descriptions
850 * previously configured. If zero TSBs were configured, EOK is
851 * returned with RET1 containing 0.
853 #define HV_FAST_MMU_TSB_CTX0_INFO 0x29
855 /* mmu_tsb_ctxnon0_info()
857 * FUNCTION: HV_FAST_MMU_TSB_CTXNON0_INFO
859 * ARG1: buffer pointer
861 * RET1: number of TSBs
862 * ERRORS: EINVAL Supplied buffer is too small
863 * EBADALIGN The buffer pointer is badly aligned
864 * ENORADDR Invalid real address for buffer pointer
866 * Return the TSB configuration as previous defined by
867 * mmu_tsb_ctxnon0() into the provided buffer. The size of the buffer
868 * is given in ARG1 in terms of the number of TSB description entries.
870 * Upon return, RET1 always contains the number of TSB descriptions
871 * previously configured. If zero TSBs were configured, EOK is
872 * returned with RET1 containing 0.
874 #define HV_FAST_MMU_TSB_CTXNON0_INFO 0x2a
876 /* mmu_fault_area_info()
878 * FUNCTION: HV_FAST_MMU_FAULT_AREA_INFO
880 * RET1: fault area real address
881 * ERRORS: No errors defined.
883 * Return the currently defined MMU fault status area for the current
884 * CPU. The real address of the fault status area is returned in
885 * RET1, or 0 is returned in RET1 if no fault status area is defined.
887 * Note: mmu_fault_area_conf() may be called with the return value (RET1)
888 * from this service if there is a need to save and restore the fault
891 #define HV_FAST_MMU_FAULT_AREA_INFO 0x2b
893 /* Cache and Memory services. */
897 * FUNCTION: HV_FAST_MEM_SCRUB
901 * RET1: length scrubbed
902 * ERRORS: ENORADDR Invalid real address
903 * EBADALIGN Start address or length are not correctly
905 * EINVAL Length is zero
907 * Zero the memory contents in the range real address to real address
908 * plus length minus 1. Also, valid ECC will be generated for that
909 * memory address range. Scrubbing is started at the given real
910 * address, but may not scrub the entire given length. The actual
911 * length scrubbed will be returned in RET1.
913 * The real address and length must be aligned on an 8K boundary, or
914 * contain the start address and length from a sun4v error report.
916 * Note: There are two uses for this function. The first use is to block clear
917 * and initialize memory and the second is to scrub an u ncorrectable
918 * error reported via a resumable or non-resumable trap. The second
919 * use requires the arguments to be equal to the real address and length
920 * provided in a sun4v memory error report.
922 #define HV_FAST_MEM_SCRUB 0x31
926 * FUNCTION: HV_FAST_MEM_SYNC
930 * RET1: length synced
931 * ERRORS: ENORADDR Invalid real address
932 * EBADALIGN Start address or length are not correctly
934 * EINVAL Length is zero
936 * Force the next access within the real address to real address plus
937 * length minus 1 to be fetches from main system memory. Less than
938 * the given length may be synced, the actual amount synced is
939 * returned in RET1. The real address and length must be aligned on
942 #define HV_FAST_MEM_SYNC 0x32
944 /* Time of day services.
946 * The hypervisor maintains the time of day on a per-domain basis.
947 * Changing the time of day in one domain does not affect the time of
948 * day on any other domain.
950 * Time is described by a single unsigned 64-bit word which is the
951 * number of seconds since the UNIX Epoch (00:00:00 UTC, January 1,
957 * FUNCTION: HV_FAST_TOD_GET
960 * ERRORS: EWOULDBLOCK TOD resource is temporarily unavailable
961 * ENOTSUPPORTED If TOD not supported on this platform
963 * Return the current time of day. May block if TOD access is
964 * temporarily not possible.
966 #define HV_FAST_TOD_GET 0x50
969 unsigned long sun4v_tod_get(unsigned long *time);
974 * FUNCTION: HV_FAST_TOD_SET
977 * ERRORS: EWOULDBLOCK TOD resource is temporarily unavailable
978 * ENOTSUPPORTED If TOD not supported on this platform
980 * The current time of day is set to the value specified in ARG0. May
981 * block if TOD access is temporarily not possible.
983 #define HV_FAST_TOD_SET 0x51
986 unsigned long sun4v_tod_set(unsigned long time);
989 /* Console services */
993 * FUNCTION: HV_FAST_CONS_GETCHAR
996 * ERRORS: EWOULDBLOCK No character available.
998 * Returns a character from the console device. If no character is
999 * available then an EWOULDBLOCK error is returned. If a character is
1000 * available, then the returned status is EOK and the character value
1003 * A virtual BREAK is represented by the 64-bit value -1.
1005 * A virtual HUP signal is represented by the 64-bit value -2.
1007 #define HV_FAST_CONS_GETCHAR 0x60
1010 * TRAP: HV_FAST_TRAP
1011 * FUNCTION: HV_FAST_CONS_PUTCHAR
1014 * ERRORS: EINVAL Illegal character
1015 * EWOULDBLOCK Output buffer currently full, would block
1017 * Send a character to the console device. Only character values
1018 * between 0 and 255 may be used. Values outside this range are
1019 * invalid except for the 64-bit value -1 which is used to send a
1022 #define HV_FAST_CONS_PUTCHAR 0x61
1025 * TRAP: HV_FAST_TRAP
1026 * FUNCTION: HV_FAST_CONS_READ
1027 * ARG0: buffer real address
1028 * ARG1: buffer size in bytes
1030 * RET1: bytes read or BREAK or HUP
1031 * ERRORS: EWOULDBLOCK No character available.
1033 * Reads characters into a buffer from the console device. If no
1034 * character is available then an EWOULDBLOCK error is returned.
1035 * If a character is available, then the returned status is EOK
1036 * and the number of bytes read into the given buffer is provided
1039 * A virtual BREAK is represented by the 64-bit RET1 value -1.
1041 * A virtual HUP signal is represented by the 64-bit RET1 value -2.
1043 * If BREAK or HUP are indicated, no bytes were read into buffer.
1045 #define HV_FAST_CONS_READ 0x62
1048 * TRAP: HV_FAST_TRAP
1049 * FUNCTION: HV_FAST_CONS_WRITE
1050 * ARG0: buffer real address
1051 * ARG1: buffer size in bytes
1053 * RET1: bytes written
1054 * ERRORS: EWOULDBLOCK Output buffer currently full, would block
1056 * Send a characters in buffer to the console device. Breaks must be
1057 * sent using con_putchar().
1059 #define HV_FAST_CONS_WRITE 0x63
1061 #ifndef __ASSEMBLY__
1062 long sun4v_con_getchar(long *status);
1063 long sun4v_con_putchar(long c);
1064 long sun4v_con_read(unsigned long buffer,
1066 unsigned long *bytes_read);
1067 unsigned long sun4v_con_write(unsigned long buffer,
1069 unsigned long *bytes_written);
1072 /* mach_set_soft_state()
1073 * TRAP: HV_FAST_TRAP
1074 * FUNCTION: HV_FAST_MACH_SET_SOFT_STATE
1075 * ARG0: software state
1076 * ARG1: software state description pointer
1078 * ERRORS: EINVAL software state not valid or software state
1079 * description is not NULL terminated
1080 * ENORADDR software state description pointer is not a
1081 * valid real address
1082 * EBADALIGNED software state description is not correctly
1085 * This allows the guest to report it's soft state to the hypervisor. There
1086 * are two primary components to this state. The first part states whether
1087 * the guest software is running or not. The second containts optional
1088 * details specific to the software.
1090 * The software state argument is defined below in HV_SOFT_STATE_*, and
1091 * indicates whether the guest is operating normally or in a transitional
1094 * The software state description argument is a real address of a data buffer
1095 * of size 32-bytes aligned on a 32-byte boundary. It is treated as a NULL
1096 * terminated 7-bit ASCII string of up to 31 characters not including the
1099 #define HV_FAST_MACH_SET_SOFT_STATE 0x70
1100 #define HV_SOFT_STATE_NORMAL 0x01
1101 #define HV_SOFT_STATE_TRANSITION 0x02
1103 #ifndef __ASSEMBLY__
1104 unsigned long sun4v_mach_set_soft_state(unsigned long soft_state,
1105 unsigned long msg_string_ra);
1108 /* mach_get_soft_state()
1109 * TRAP: HV_FAST_TRAP
1110 * FUNCTION: HV_FAST_MACH_GET_SOFT_STATE
1111 * ARG0: software state description pointer
1113 * RET1: software state
1114 * ERRORS: ENORADDR software state description pointer is not a
1115 * valid real address
1116 * EBADALIGNED software state description is not correctly
1119 * Retrieve the current value of the guest's software state. The rules
1120 * for the software state pointer are the same as for mach_set_soft_state()
1123 #define HV_FAST_MACH_GET_SOFT_STATE 0x71
1126 * TRAP: HV_FAST_TRAP
1127 * FUNCTION: HV_FAST_SVC_SEND
1129 * ARG1: buffer real address
1134 * Be careful, all output registers are clobbered by this operation,
1135 * so for example it is not possible to save away a value in %o4
1138 #define HV_FAST_SVC_SEND 0x80
1141 * TRAP: HV_FAST_TRAP
1142 * FUNCTION: HV_FAST_SVC_RECV
1144 * ARG1: buffer real address
1149 * Be careful, all output registers are clobbered by this operation,
1150 * so for example it is not possible to save away a value in %o4
1153 #define HV_FAST_SVC_RECV 0x81
1156 * TRAP: HV_FAST_TRAP
1157 * FUNCTION: HV_FAST_SVC_GETSTATUS
1162 #define HV_FAST_SVC_GETSTATUS 0x82
1165 * TRAP: HV_FAST_TRAP
1166 * FUNCTION: HV_FAST_SVC_SETSTATUS
1171 #define HV_FAST_SVC_SETSTATUS 0x83
1174 * TRAP: HV_FAST_TRAP
1175 * FUNCTION: HV_FAST_SVC_CLRSTATUS
1177 * ARG1: bits to clear
1180 #define HV_FAST_SVC_CLRSTATUS 0x84
1182 #ifndef __ASSEMBLY__
1183 unsigned long sun4v_svc_send(unsigned long svc_id,
1184 unsigned long buffer,
1185 unsigned long buffer_size,
1186 unsigned long *sent_bytes);
1187 unsigned long sun4v_svc_recv(unsigned long svc_id,
1188 unsigned long buffer,
1189 unsigned long buffer_size,
1190 unsigned long *recv_bytes);
1191 unsigned long sun4v_svc_getstatus(unsigned long svc_id,
1192 unsigned long *status_bits);
1193 unsigned long sun4v_svc_setstatus(unsigned long svc_id,
1194 unsigned long status_bits);
1195 unsigned long sun4v_svc_clrstatus(unsigned long svc_id,
1196 unsigned long status_bits);
1199 /* Trap trace services.
1201 * The hypervisor provides a trap tracing capability for privileged
1202 * code running on each virtual CPU. Privileged code provides a
1203 * round-robin trap trace queue within which the hypervisor writes
1204 * 64-byte entries detailing hyperprivileged traps taken n behalf of
1205 * privileged code. This is provided as a debugging capability for
1208 * The trap trace control structure is 64-bytes long and placed at the
1209 * start (offset 0) of the trap trace buffer, and is described as
1212 #ifndef __ASSEMBLY__
1213 struct hv_trap_trace_control {
1214 unsigned long head_offset;
1215 unsigned long tail_offset;
1216 unsigned long __reserved[0x30 / sizeof(unsigned long)];
1219 #define HV_TRAP_TRACE_CTRL_HEAD_OFFSET 0x00
1220 #define HV_TRAP_TRACE_CTRL_TAIL_OFFSET 0x08
1222 /* The head offset is the offset of the most recently completed entry
1223 * in the trap-trace buffer. The tail offset is the offset of the
1224 * next entry to be written. The control structure is owned and
1225 * modified by the hypervisor. A guest may not modify the control
1226 * structure contents. Attempts to do so will result in undefined
1227 * behavior for the guest.
1229 * Each trap trace buffer entry is laid out as follows:
1231 #ifndef __ASSEMBLY__
1232 struct hv_trap_trace_entry {
1233 unsigned char type; /* Hypervisor or guest entry? */
1234 unsigned char hpstate; /* Hyper-privileged state */
1235 unsigned char tl; /* Trap level */
1236 unsigned char gl; /* Global register level */
1237 unsigned short tt; /* Trap type */
1238 unsigned short tag; /* Extended trap identifier */
1239 unsigned long tstate; /* Trap state */
1240 unsigned long tick; /* Tick */
1241 unsigned long tpc; /* Trap PC */
1242 unsigned long f1; /* Entry specific */
1243 unsigned long f2; /* Entry specific */
1244 unsigned long f3; /* Entry specific */
1245 unsigned long f4; /* Entry specific */
1248 #define HV_TRAP_TRACE_ENTRY_TYPE 0x00
1249 #define HV_TRAP_TRACE_ENTRY_HPSTATE 0x01
1250 #define HV_TRAP_TRACE_ENTRY_TL 0x02
1251 #define HV_TRAP_TRACE_ENTRY_GL 0x03
1252 #define HV_TRAP_TRACE_ENTRY_TT 0x04
1253 #define HV_TRAP_TRACE_ENTRY_TAG 0x06
1254 #define HV_TRAP_TRACE_ENTRY_TSTATE 0x08
1255 #define HV_TRAP_TRACE_ENTRY_TICK 0x10
1256 #define HV_TRAP_TRACE_ENTRY_TPC 0x18
1257 #define HV_TRAP_TRACE_ENTRY_F1 0x20
1258 #define HV_TRAP_TRACE_ENTRY_F2 0x28
1259 #define HV_TRAP_TRACE_ENTRY_F3 0x30
1260 #define HV_TRAP_TRACE_ENTRY_F4 0x38
1262 /* The type field is encoded as follows. */
1263 #define HV_TRAP_TYPE_UNDEF 0x00 /* Entry content undefined */
1264 #define HV_TRAP_TYPE_HV 0x01 /* Hypervisor trap entry */
1265 #define HV_TRAP_TYPE_GUEST 0xff /* Added via ttrace_addentry() */
1267 /* ttrace_buf_conf()
1268 * TRAP: HV_FAST_TRAP
1269 * FUNCTION: HV_FAST_TTRACE_BUF_CONF
1270 * ARG0: real address
1271 * ARG1: number of entries
1273 * RET1: number of entries
1274 * ERRORS: ENORADDR Invalid real address
1275 * EINVAL Size is too small
1276 * EBADALIGN Real address not aligned on 64-byte boundary
1278 * Requests hypervisor trap tracing and declares a virtual CPU's trap
1279 * trace buffer to the hypervisor. The real address supplies the real
1280 * base address of the trap trace queue and must be 64-byte aligned.
1281 * Specifying a value of 0 for the number of entries disables trap
1282 * tracing for the calling virtual CPU. The buffer allocated must be
1283 * sized for a power of two number of 64-byte trap trace entries plus
1284 * an initial 64-byte control structure.
1286 * This may be invoked any number of times so that a virtual CPU may
1287 * relocate a trap trace buffer or create "snapshots" of information.
1289 * If the real address is illegal or badly aligned, then trap tracing
1290 * is disabled and an error is returned.
1292 * Upon failure with EINVAL, this service call returns in RET1 the
1293 * minimum number of buffer entries required. Upon other failures
1294 * RET1 is undefined.
1296 #define HV_FAST_TTRACE_BUF_CONF 0x90
1298 /* ttrace_buf_info()
1299 * TRAP: HV_FAST_TRAP
1300 * FUNCTION: HV_FAST_TTRACE_BUF_INFO
1302 * RET1: real address
1304 * ERRORS: None defined.
1306 * Returns the size and location of the previously declared trap-trace
1307 * buffer. In the event that no buffer was previously defined, or the
1308 * buffer is disabled, this call will return a size of zero bytes.
1310 #define HV_FAST_TTRACE_BUF_INFO 0x91
1313 * TRAP: HV_FAST_TRAP
1314 * FUNCTION: HV_FAST_TTRACE_ENABLE
1317 * RET1: previous enable state
1318 * ERRORS: EINVAL No trap trace buffer currently defined
1320 * Enable or disable trap tracing, and return the previous enabled
1321 * state in RET1. Future systems may define various flags for the
1322 * enable argument (ARG0), for the moment a guest should pass
1323 * "(uint64_t) -1" to enable, and "(uint64_t) 0" to disable all
1324 * tracing - which will ensure future compatibility.
1326 #define HV_FAST_TTRACE_ENABLE 0x92
1329 * TRAP: HV_FAST_TRAP
1330 * FUNCTION: HV_FAST_TTRACE_FREEZE
1333 * RET1: previous freeze state
1334 * ERRORS: EINVAL No trap trace buffer currently defined
1336 * Freeze or unfreeze trap tracing, returning the previous freeze
1337 * state in RET1. A guest should pass a non-zero value to freeze and
1338 * a zero value to unfreeze all tracing. The returned previous state
1339 * is 0 for not frozen and 1 for frozen.
1341 #define HV_FAST_TTRACE_FREEZE 0x93
1343 /* ttrace_addentry()
1344 * TRAP: HV_TTRACE_ADDENTRY_TRAP
1345 * ARG0: tag (16-bits)
1351 * ERRORS: EINVAL No trap trace buffer currently defined
1353 * Add an entry to the trap trace buffer. Upon return only ARG0/RET0
1354 * is modified - none of the other registers holding arguments are
1355 * volatile across this hypervisor service.
1358 /* Core dump services.
1360 * Since the hypervisor viraulizes and thus obscures a lot of the
1361 * physical machine layout and state, traditional OS crash dumps can
1362 * be difficult to diagnose especially when the problem is a
1363 * configuration error of some sort.
1365 * The dump services provide an opaque buffer into which the
1366 * hypervisor can place it's internal state in order to assist in
1367 * debugging such situations. The contents are opaque and extremely
1368 * platform and hypervisor implementation specific. The guest, during
1369 * a core dump, requests that the hypervisor update any information in
1370 * the dump buffer in preparation to being dumped as part of the
1371 * domain's memory image.
1374 /* dump_buf_update()
1375 * TRAP: HV_FAST_TRAP
1376 * FUNCTION: HV_FAST_DUMP_BUF_UPDATE
1377 * ARG0: real address
1380 * RET1: required size of dump buffer
1381 * ERRORS: ENORADDR Invalid real address
1382 * EBADALIGN Real address is not aligned on a 64-byte
1384 * EINVAL Size is non-zero but less than minimum size
1386 * ENOTSUPPORTED Operation not supported on current logical
1389 * Declare a domain dump buffer to the hypervisor. The real address
1390 * provided for the domain dump buffer must be 64-byte aligned. The
1391 * size specifies the size of the dump buffer and may be larger than
1392 * the minimum size specified in the machine description. The
1393 * hypervisor will fill the dump buffer with opaque data.
1395 * Note: A guest may elect to include dump buffer contents as part of a crash
1396 * dump to assist with debugging. This function may be called any number
1397 * of times so that a guest may relocate a dump buffer, or create
1398 * "snapshots" of any dump-buffer information. Each call to
1399 * dump_buf_update() atomically declares the new dump buffer to the
1402 * A specified size of 0 unconfigures the dump buffer. If the real
1403 * address is illegal or badly aligned, then any currently active dump
1404 * buffer is disabled and an error is returned.
1406 * In the event that the call fails with EINVAL, RET1 contains the
1407 * minimum size requires by the hypervisor for a valid dump buffer.
1409 #define HV_FAST_DUMP_BUF_UPDATE 0x94
1412 * TRAP: HV_FAST_TRAP
1413 * FUNCTION: HV_FAST_DUMP_BUF_INFO
1415 * RET1: real address of current dump buffer
1416 * RET2: size of current dump buffer
1417 * ERRORS: No errors defined.
1419 * Return the currently configures dump buffer description. A
1420 * returned size of 0 bytes indicates an undefined dump buffer. In
1421 * this case the return address in RET1 is undefined.
1423 #define HV_FAST_DUMP_BUF_INFO 0x95
1425 /* Device interrupt services.
1427 * Device interrupts are allocated to system bus bridges by the hypervisor,
1428 * and described to OBP in the machine description. OBP then describes
1429 * these interrupts to the OS via properties in the device tree.
1433 * cpuid Unique opaque value which represents a target cpu.
1435 * devhandle Device handle. It uniquely identifies a device, and
1436 * consistes of the lower 28-bits of the hi-cell of the
1437 * first entry of the device's "reg" property in the
1440 * devino Device interrupt number. Specifies the relative
1441 * interrupt number within the device. The unique
1442 * combination of devhandle and devino are used to
1443 * identify a specific device interrupt.
1445 * Note: The devino value is the same as the values in the
1446 * "interrupts" property or "interrupt-map" property
1447 * in the OBP device tree for that device.
1449 * sysino System interrupt number. A 64-bit unsigned interger
1450 * representing a unique interrupt within a virtual
1453 * intr_state A flag representing the interrupt state for a given
1454 * sysino. The state values are defined below.
1456 * intr_enabled A flag representing the 'enabled' state for a given
1457 * sysino. The enable values are defined below.
1460 #define HV_INTR_STATE_IDLE 0 /* Nothing pending */
1461 #define HV_INTR_STATE_RECEIVED 1 /* Interrupt received by hardware */
1462 #define HV_INTR_STATE_DELIVERED 2 /* Interrupt delivered to queue */
1464 #define HV_INTR_DISABLED 0 /* sysino not enabled */
1465 #define HV_INTR_ENABLED 1 /* sysino enabled */
1467 /* intr_devino_to_sysino()
1468 * TRAP: HV_FAST_TRAP
1469 * FUNCTION: HV_FAST_INTR_DEVINO2SYSINO
1474 * ERRORS: EINVAL Invalid devhandle/devino
1476 * Converts a device specific interrupt number of the given
1477 * devhandle/devino into a system specific ino (sysino).
1479 #define HV_FAST_INTR_DEVINO2SYSINO 0xa0
1481 #ifndef __ASSEMBLY__
1482 unsigned long sun4v_devino_to_sysino(unsigned long devhandle,
1483 unsigned long devino);
1486 /* intr_getenabled()
1487 * TRAP: HV_FAST_TRAP
1488 * FUNCTION: HV_FAST_INTR_GETENABLED
1491 * RET1: intr_enabled (HV_INTR_{DISABLED,ENABLED})
1492 * ERRORS: EINVAL Invalid sysino
1494 * Returns interrupt enabled state in RET1 for the interrupt defined
1495 * by the given sysino.
1497 #define HV_FAST_INTR_GETENABLED 0xa1
1499 #ifndef __ASSEMBLY__
1500 unsigned long sun4v_intr_getenabled(unsigned long sysino);
1503 /* intr_setenabled()
1504 * TRAP: HV_FAST_TRAP
1505 * FUNCTION: HV_FAST_INTR_SETENABLED
1507 * ARG1: intr_enabled (HV_INTR_{DISABLED,ENABLED})
1509 * ERRORS: EINVAL Invalid sysino or intr_enabled value
1511 * Set the 'enabled' state of the interrupt sysino.
1513 #define HV_FAST_INTR_SETENABLED 0xa2
1515 #ifndef __ASSEMBLY__
1516 unsigned long sun4v_intr_setenabled(unsigned long sysino,
1517 unsigned long intr_enabled);
1521 * TRAP: HV_FAST_TRAP
1522 * FUNCTION: HV_FAST_INTR_GETSTATE
1525 * RET1: intr_state (HV_INTR_STATE_*)
1526 * ERRORS: EINVAL Invalid sysino
1528 * Returns current state of the interrupt defined by the given sysino.
1530 #define HV_FAST_INTR_GETSTATE 0xa3
1532 #ifndef __ASSEMBLY__
1533 unsigned long sun4v_intr_getstate(unsigned long sysino);
1537 * TRAP: HV_FAST_TRAP
1538 * FUNCTION: HV_FAST_INTR_SETSTATE
1540 * ARG1: intr_state (HV_INTR_STATE_*)
1542 * ERRORS: EINVAL Invalid sysino or intr_state value
1544 * Sets the current state of the interrupt described by the given sysino
1547 * Note: Setting the state to HV_INTR_STATE_IDLE clears any pending
1548 * interrupt for sysino.
1550 #define HV_FAST_INTR_SETSTATE 0xa4
1552 #ifndef __ASSEMBLY__
1553 unsigned long sun4v_intr_setstate(unsigned long sysino, unsigned long intr_state);
1557 * TRAP: HV_FAST_TRAP
1558 * FUNCTION: HV_FAST_INTR_GETTARGET
1562 * ERRORS: EINVAL Invalid sysino
1564 * Returns CPU that is the current target of the interrupt defined by
1565 * the given sysino. The CPU value returned is undefined if the target
1566 * has not been set via intr_settarget().
1568 #define HV_FAST_INTR_GETTARGET 0xa5
1570 #ifndef __ASSEMBLY__
1571 unsigned long sun4v_intr_gettarget(unsigned long sysino);
1575 * TRAP: HV_FAST_TRAP
1576 * FUNCTION: HV_FAST_INTR_SETTARGET
1580 * ERRORS: EINVAL Invalid sysino
1581 * ENOCPU Invalid cpuid
1583 * Set the target CPU for the interrupt defined by the given sysino.
1585 #define HV_FAST_INTR_SETTARGET 0xa6
1587 #ifndef __ASSEMBLY__
1588 unsigned long sun4v_intr_settarget(unsigned long sysino, unsigned long cpuid);
1591 /* vintr_get_cookie()
1592 * TRAP: HV_FAST_TRAP
1593 * FUNCTION: HV_FAST_VINTR_GET_COOKIE
1594 * ARG0: device handle
1599 #define HV_FAST_VINTR_GET_COOKIE 0xa7
1601 /* vintr_set_cookie()
1602 * TRAP: HV_FAST_TRAP
1603 * FUNCTION: HV_FAST_VINTR_SET_COOKIE
1604 * ARG0: device handle
1609 #define HV_FAST_VINTR_SET_COOKIE 0xa8
1611 /* vintr_get_valid()
1612 * TRAP: HV_FAST_TRAP
1613 * FUNCTION: HV_FAST_VINTR_GET_VALID
1614 * ARG0: device handle
1619 #define HV_FAST_VINTR_GET_VALID 0xa9
1621 /* vintr_set_valid()
1622 * TRAP: HV_FAST_TRAP
1623 * FUNCTION: HV_FAST_VINTR_SET_VALID
1624 * ARG0: device handle
1629 #define HV_FAST_VINTR_SET_VALID 0xaa
1631 /* vintr_get_state()
1632 * TRAP: HV_FAST_TRAP
1633 * FUNCTION: HV_FAST_VINTR_GET_STATE
1634 * ARG0: device handle
1639 #define HV_FAST_VINTR_GET_STATE 0xab
1641 /* vintr_set_state()
1642 * TRAP: HV_FAST_TRAP
1643 * FUNCTION: HV_FAST_VINTR_SET_STATE
1644 * ARG0: device handle
1649 #define HV_FAST_VINTR_SET_STATE 0xac
1651 /* vintr_get_target()
1652 * TRAP: HV_FAST_TRAP
1653 * FUNCTION: HV_FAST_VINTR_GET_TARGET
1654 * ARG0: device handle
1659 #define HV_FAST_VINTR_GET_TARGET 0xad
1661 /* vintr_set_target()
1662 * TRAP: HV_FAST_TRAP
1663 * FUNCTION: HV_FAST_VINTR_SET_TARGET
1664 * ARG0: device handle
1669 #define HV_FAST_VINTR_SET_TARGET 0xae
1671 #ifndef __ASSEMBLY__
1672 unsigned long sun4v_vintr_get_cookie(unsigned long dev_handle,
1673 unsigned long dev_ino,
1674 unsigned long *cookie);
1675 unsigned long sun4v_vintr_set_cookie(unsigned long dev_handle,
1676 unsigned long dev_ino,
1677 unsigned long cookie);
1678 unsigned long sun4v_vintr_get_valid(unsigned long dev_handle,
1679 unsigned long dev_ino,
1680 unsigned long *valid);
1681 unsigned long sun4v_vintr_set_valid(unsigned long dev_handle,
1682 unsigned long dev_ino,
1683 unsigned long valid);
1684 unsigned long sun4v_vintr_get_state(unsigned long dev_handle,
1685 unsigned long dev_ino,
1686 unsigned long *state);
1687 unsigned long sun4v_vintr_set_state(unsigned long dev_handle,
1688 unsigned long dev_ino,
1689 unsigned long state);
1690 unsigned long sun4v_vintr_get_target(unsigned long dev_handle,
1691 unsigned long dev_ino,
1692 unsigned long *cpuid);
1693 unsigned long sun4v_vintr_set_target(unsigned long dev_handle,
1694 unsigned long dev_ino,
1695 unsigned long cpuid);
1700 * See the terminology descriptions in the device interrupt services
1701 * section above as those apply here too. Here are terminology
1702 * definitions specific to these PCI IO services:
1704 * tsbnum TSB number. Indentifies which io-tsb is used.
1705 * For this version of the specification, tsbnum
1708 * tsbindex TSB index. Identifies which entry in the TSB
1709 * is used. The first entry is zero.
1711 * tsbid A 64-bit aligned data structure which contains
1712 * a tsbnum and a tsbindex. Bits 63:32 contain the
1713 * tsbnum and bits 31:00 contain the tsbindex.
1715 * Use the HV_PCI_TSBID() macro to construct such
1718 * io_attributes IO attributes for IOMMU mappings. One of more
1719 * of the attritbute bits are stores in a 64-bit
1720 * value. The values are defined below.
1722 * r_addr 64-bit real address
1724 * pci_device PCI device address. A PCI device address identifies
1725 * a specific device on a specific PCI bus segment.
1726 * A PCI device address ia a 32-bit unsigned integer
1727 * with the following format:
1729 * 00000000.bbbbbbbb.dddddfff.00000000
1731 * Use the HV_PCI_DEVICE_BUILD() macro to construct
1735 * PCI configureation space offset. For conventional
1736 * PCI a value between 0 and 255. For extended
1737 * configuration space, a value between 0 and 4095.
1739 * Note: For PCI configuration space accesses, the offset
1740 * must be aligned to the access size.
1742 * error_flag A return value which specifies if the action succeeded
1743 * or failed. 0 means no error, non-0 means some error
1744 * occurred while performing the service.
1747 * Direction definition for pci_dma_sync(), defined
1748 * below in HV_PCI_SYNC_*.
1750 * io_page_list A list of io_page_addresses, an io_page_address is
1753 * io_page_list_p A pointer to an io_page_list.
1755 * "size based byte swap" - Some functions do size based byte swapping
1756 * which allows sw to access pointers and
1757 * counters in native form when the processor
1758 * operates in a different endianness than the
1759 * IO bus. Size-based byte swapping converts a
1760 * multi-byte field between big-endian and
1761 * little-endian format.
1764 #define HV_PCI_MAP_ATTR_READ 0x01
1765 #define HV_PCI_MAP_ATTR_WRITE 0x02
1766 #define HV_PCI_MAP_ATTR_RELAXED_ORDER 0x04
1768 #define HV_PCI_DEVICE_BUILD(b,d,f) \
1769 ((((b) & 0xff) << 16) | \
1770 (((d) & 0x1f) << 11) | \
1771 (((f) & 0x07) << 8))
1773 #define HV_PCI_TSBID(__tsb_num, __tsb_index) \
1774 ((((u64)(__tsb_num)) << 32UL) | ((u64)(__tsb_index)))
1776 #define HV_PCI_SYNC_FOR_DEVICE 0x01
1777 #define HV_PCI_SYNC_FOR_CPU 0x02
1780 * TRAP: HV_FAST_TRAP
1781 * FUNCTION: HV_FAST_PCI_IOMMU_MAP
1785 * ARG3: io_attributes
1786 * ARG4: io_page_list_p
1788 * RET1: #ttes mapped
1789 * ERRORS: EINVAL Invalid devhandle/tsbnum/tsbindex/io_attributes
1790 * EBADALIGN Improperly aligned real address
1791 * ENORADDR Invalid real address
1793 * Create IOMMU mappings in the sun4v device defined by the given
1794 * devhandle. The mappings are created in the TSB defined by the
1795 * tsbnum component of the given tsbid. The first mapping is created
1796 * in the TSB i ndex defined by the tsbindex component of the given tsbid.
1797 * The call creates up to #ttes mappings, the first one at tsbnum, tsbindex,
1798 * the second at tsbnum, tsbindex + 1, etc.
1800 * All mappings are created with the attributes defined by the io_attributes
1801 * argument. The page mapping addresses are described in the io_page_list
1802 * defined by the given io_page_list_p, which is a pointer to the io_page_list.
1803 * The first entry in the io_page_list is the address for the first iotte, the
1804 * 2nd for the 2nd iotte, and so on.
1806 * Each io_page_address in the io_page_list must be appropriately aligned.
1807 * #ttes must be greater than zero. For this version of the spec, the tsbnum
1808 * component of the given tsbid must be zero.
1810 * Returns the actual number of mappings creates, which may be less than
1811 * or equal to the argument #ttes. If the function returns a value which
1812 * is less than the #ttes, the caller may continus to call the function with
1813 * an updated tsbid, #ttes, io_page_list_p arguments until all pages are
1816 * Note: This function does not imply an iotte cache flush. The guest must
1817 * demap an entry before re-mapping it.
1819 #define HV_FAST_PCI_IOMMU_MAP 0xb0
1821 /* pci_iommu_demap()
1822 * TRAP: HV_FAST_TRAP
1823 * FUNCTION: HV_FAST_PCI_IOMMU_DEMAP
1828 * RET1: #ttes demapped
1829 * ERRORS: EINVAL Invalid devhandle/tsbnum/tsbindex
1831 * Demap and flush IOMMU mappings in the device defined by the given
1832 * devhandle. Demaps up to #ttes entries in the TSB defined by the tsbnum
1833 * component of the given tsbid, starting at the TSB index defined by the
1834 * tsbindex component of the given tsbid.
1836 * For this version of the spec, the tsbnum of the given tsbid must be zero.
1837 * #ttes must be greater than zero.
1839 * Returns the actual number of ttes demapped, which may be less than or equal
1840 * to the argument #ttes. If #ttes demapped is less than #ttes, the caller
1841 * may continue to call this function with updated tsbid and #ttes arguments
1842 * until all pages are demapped.
1844 * Note: Entries do not have to be mapped to be demapped. A demap of an
1845 * unmapped page will flush the entry from the tte cache.
1847 #define HV_FAST_PCI_IOMMU_DEMAP 0xb1
1849 /* pci_iommu_getmap()
1850 * TRAP: HV_FAST_TRAP
1851 * FUNCTION: HV_FAST_PCI_IOMMU_GETMAP
1855 * RET1: io_attributes
1856 * RET2: real address
1857 * ERRORS: EINVAL Invalid devhandle/tsbnum/tsbindex
1858 * ENOMAP Mapping is not valid, no translation exists
1860 * Read and return the mapping in the device described by the given devhandle
1861 * and tsbid. If successful, the io_attributes shall be returned in RET1
1862 * and the page address of the mapping shall be returned in RET2.
1864 * For this version of the spec, the tsbnum component of the given tsbid
1867 #define HV_FAST_PCI_IOMMU_GETMAP 0xb2
1869 /* pci_iommu_getbypass()
1870 * TRAP: HV_FAST_TRAP
1871 * FUNCTION: HV_FAST_PCI_IOMMU_GETBYPASS
1873 * ARG1: real address
1874 * ARG2: io_attributes
1877 * ERRORS: EINVAL Invalid devhandle/io_attributes
1878 * ENORADDR Invalid real address
1879 * ENOTSUPPORTED Function not supported in this implementation.
1881 * Create a "special" mapping in the device described by the given devhandle,
1882 * for the given real address and attributes. Return the IO address in RET1
1885 #define HV_FAST_PCI_IOMMU_GETBYPASS 0xb3
1888 * TRAP: HV_FAST_TRAP
1889 * FUNCTION: HV_FAST_PCI_CONFIG_GET
1892 * ARG2: pci_config_offset
1897 * ERRORS: EINVAL Invalid devhandle/pci_device/offset/size
1898 * EBADALIGN pci_config_offset not size aligned
1899 * ENOACCESS Access to this offset is not permitted
1901 * Read PCI configuration space for the adapter described by the given
1902 * devhandle. Read size (1, 2, or 4) bytes of data from the given
1903 * pci_device, at pci_config_offset from the beginning of the device's
1904 * configuration space. If there was no error, RET1 is set to zero and
1905 * RET2 is set to the data read. Insignificant bits in RET2 are not
1906 * guaranteed to have any specific value and therefore must be ignored.
1908 * The data returned in RET2 is size based byte swapped.
1910 * If an error occurs during the read, set RET1 to a non-zero value. The
1911 * given pci_config_offset must be 'size' aligned.
1913 #define HV_FAST_PCI_CONFIG_GET 0xb4
1916 * TRAP: HV_FAST_TRAP
1917 * FUNCTION: HV_FAST_PCI_CONFIG_PUT
1920 * ARG2: pci_config_offset
1925 * ERRORS: EINVAL Invalid devhandle/pci_device/offset/size
1926 * EBADALIGN pci_config_offset not size aligned
1927 * ENOACCESS Access to this offset is not permitted
1929 * Write PCI configuration space for the adapter described by the given
1930 * devhandle. Write size (1, 2, or 4) bytes of data in a single operation,
1931 * at pci_config_offset from the beginning of the device's configuration
1932 * space. The data argument contains the data to be written to configuration
1933 * space. Prior to writing, the data is size based byte swapped.
1935 * If an error occurs during the write access, do not generate an error
1936 * report, do set RET1 to a non-zero value. Otherwise RET1 is zero.
1937 * The given pci_config_offset must be 'size' aligned.
1939 * This function is permitted to read from offset zero in the configuration
1940 * space described by the given pci_device if necessary to ensure that the
1941 * write access to config space completes.
1943 #define HV_FAST_PCI_CONFIG_PUT 0xb5
1946 * TRAP: HV_FAST_TRAP
1947 * FUNCTION: HV_FAST_PCI_PEEK
1949 * ARG1: real address
1954 * ERRORS: EINVAL Invalid devhandle or size
1955 * EBADALIGN Improperly aligned real address
1956 * ENORADDR Bad real address
1957 * ENOACCESS Guest access prohibited
1959 * Attempt to read the IO address given by the given devhandle, real address,
1960 * and size. Size must be 1, 2, 4, or 8. The read is performed as a single
1961 * access operation using the given size. If an error occurs when reading
1962 * from the given location, do not generate an error report, but return a
1963 * non-zero value in RET1. If the read was successful, return zero in RET1
1964 * and return the actual data read in RET2. The data returned is size based
1967 * Non-significant bits in RET2 are not guaranteed to have any specific value
1968 * and therefore must be ignored. If RET1 is returned as non-zero, the data
1969 * value is not guaranteed to have any specific value and should be ignored.
1971 * The caller must have permission to read from the given devhandle, real
1972 * address, which must be an IO address. The argument real address must be a
1973 * size aligned address.
1975 * The hypervisor implementation of this function must block access to any
1976 * IO address that the guest does not have explicit permission to access.
1978 #define HV_FAST_PCI_PEEK 0xb6
1981 * TRAP: HV_FAST_TRAP
1982 * FUNCTION: HV_FAST_PCI_POKE
1984 * ARG1: real address
1990 * ERRORS: EINVAL Invalid devhandle, size, or pci_device
1991 * EBADALIGN Improperly aligned real address
1992 * ENORADDR Bad real address
1993 * ENOACCESS Guest access prohibited
1994 * ENOTSUPPORTED Function is not supported by implementation
1996 * Attempt to write data to the IO address given by the given devhandle,
1997 * real address, and size. Size must be 1, 2, 4, or 8. The write is
1998 * performed as a single access operation using the given size. Prior to
1999 * writing the data is size based swapped.
2001 * If an error occurs when writing to the given location, do not generate an
2002 * error report, but return a non-zero value in RET1. If the write was
2003 * successful, return zero in RET1.
2005 * pci_device describes the configuration address of the device being
2006 * written to. The implementation may safely read from offset 0 with
2007 * the configuration space of the device described by devhandle and
2008 * pci_device in order to guarantee that the write portion of the operation
2011 * Any error that occurs due to the read shall be reported using the normal
2012 * error reporting mechanisms .. the read error is not suppressed.
2014 * The caller must have permission to write to the given devhandle, real
2015 * address, which must be an IO address. The argument real address must be a
2016 * size aligned address. The caller must have permission to read from
2017 * the given devhandle, pci_device cofiguration space offset 0.
2019 * The hypervisor implementation of this function must block access to any
2020 * IO address that the guest does not have explicit permission to access.
2022 #define HV_FAST_PCI_POKE 0xb7
2025 * TRAP: HV_FAST_TRAP
2026 * FUNCTION: HV_FAST_PCI_DMA_SYNC
2028 * ARG1: real address
2030 * ARG3: io_sync_direction
2033 * ERRORS: EINVAL Invalid devhandle or io_sync_direction
2034 * ENORADDR Bad real address
2036 * Synchronize a memory region described by the given real address and size,
2037 * for the device defined by the given devhandle using the direction(s)
2038 * defined by the given io_sync_direction. The argument size is the size of
2039 * the memory region in bytes.
2041 * Return the actual number of bytes synchronized in the return value #synced,
2042 * which may be less than or equal to the argument size. If the return
2043 * value #synced is less than size, the caller must continue to call this
2044 * function with updated real address and size arguments until the entire
2045 * memory region is synchronized.
2047 #define HV_FAST_PCI_DMA_SYNC 0xb8
2049 /* PCI MSI services. */
2051 #define HV_MSITYPE_MSI32 0x00
2052 #define HV_MSITYPE_MSI64 0x01
2054 #define HV_MSIQSTATE_IDLE 0x00
2055 #define HV_MSIQSTATE_ERROR 0x01
2057 #define HV_MSIQ_INVALID 0x00
2058 #define HV_MSIQ_VALID 0x01
2060 #define HV_MSISTATE_IDLE 0x00
2061 #define HV_MSISTATE_DELIVERED 0x01
2063 #define HV_MSIVALID_INVALID 0x00
2064 #define HV_MSIVALID_VALID 0x01
2066 #define HV_PCIE_MSGTYPE_PME_MSG 0x18
2067 #define HV_PCIE_MSGTYPE_PME_ACK_MSG 0x1b
2068 #define HV_PCIE_MSGTYPE_CORR_MSG 0x30
2069 #define HV_PCIE_MSGTYPE_NONFATAL_MSG 0x31
2070 #define HV_PCIE_MSGTYPE_FATAL_MSG 0x33
2072 #define HV_MSG_INVALID 0x00
2073 #define HV_MSG_VALID 0x01
2076 * TRAP: HV_FAST_TRAP
2077 * FUNCTION: HV_FAST_PCI_MSIQ_CONF
2080 * ARG2: real address
2081 * ARG3: number of entries
2083 * ERRORS: EINVAL Invalid devhandle, msiqid or nentries
2084 * EBADALIGN Improperly aligned real address
2085 * ENORADDR Bad real address
2087 * Configure the MSI queue given by the devhandle and msiqid arguments,
2088 * and to be placed at the given real address and be of the given
2089 * number of entries. The real address must be aligned exactly to match
2090 * the queue size. Each queue entry is 64-bytes long, so f.e. a 32 entry
2091 * queue must be aligned on a 2048 byte real address boundary. The MSI-EQ
2092 * Head and Tail are initialized so that the MSI-EQ is 'empty'.
2094 * Implementation Note: Certain implementations have fixed sized queues. In
2095 * that case, number of entries must contain the correct
2098 #define HV_FAST_PCI_MSIQ_CONF 0xc0
2101 * TRAP: HV_FAST_TRAP
2102 * FUNCTION: HV_FAST_PCI_MSIQ_INFO
2106 * RET1: real address
2107 * RET2: number of entries
2108 * ERRORS: EINVAL Invalid devhandle or msiqid
2110 * Return the configuration information for the MSI queue described
2111 * by the given devhandle and msiqid. The base address of the queue
2112 * is returned in ARG1 and the number of entries is returned in ARG2.
2113 * If the queue is unconfigured, the real address is undefined and the
2114 * number of entries will be returned as zero.
2116 #define HV_FAST_PCI_MSIQ_INFO 0xc1
2118 /* pci_msiq_getvalid()
2119 * TRAP: HV_FAST_TRAP
2120 * FUNCTION: HV_FAST_PCI_MSIQ_GETVALID
2124 * RET1: msiqvalid (HV_MSIQ_VALID or HV_MSIQ_INVALID)
2125 * ERRORS: EINVAL Invalid devhandle or msiqid
2127 * Get the valid state of the MSI-EQ described by the given devhandle and
2130 #define HV_FAST_PCI_MSIQ_GETVALID 0xc2
2132 /* pci_msiq_setvalid()
2133 * TRAP: HV_FAST_TRAP
2134 * FUNCTION: HV_FAST_PCI_MSIQ_SETVALID
2137 * ARG2: msiqvalid (HV_MSIQ_VALID or HV_MSIQ_INVALID)
2139 * ERRORS: EINVAL Invalid devhandle or msiqid or msiqvalid
2140 * value or MSI EQ is uninitialized
2142 * Set the valid state of the MSI-EQ described by the given devhandle and
2143 * msiqid to the given msiqvalid.
2145 #define HV_FAST_PCI_MSIQ_SETVALID 0xc3
2147 /* pci_msiq_getstate()
2148 * TRAP: HV_FAST_TRAP
2149 * FUNCTION: HV_FAST_PCI_MSIQ_GETSTATE
2153 * RET1: msiqstate (HV_MSIQSTATE_IDLE or HV_MSIQSTATE_ERROR)
2154 * ERRORS: EINVAL Invalid devhandle or msiqid
2156 * Get the state of the MSI-EQ described by the given devhandle and
2159 #define HV_FAST_PCI_MSIQ_GETSTATE 0xc4
2161 /* pci_msiq_getvalid()
2162 * TRAP: HV_FAST_TRAP
2163 * FUNCTION: HV_FAST_PCI_MSIQ_GETVALID
2166 * ARG2: msiqstate (HV_MSIQSTATE_IDLE or HV_MSIQSTATE_ERROR)
2168 * ERRORS: EINVAL Invalid devhandle or msiqid or msiqstate
2169 * value or MSI EQ is uninitialized
2171 * Set the state of the MSI-EQ described by the given devhandle and
2172 * msiqid to the given msiqvalid.
2174 #define HV_FAST_PCI_MSIQ_SETSTATE 0xc5
2176 /* pci_msiq_gethead()
2177 * TRAP: HV_FAST_TRAP
2178 * FUNCTION: HV_FAST_PCI_MSIQ_GETHEAD
2183 * ERRORS: EINVAL Invalid devhandle or msiqid
2185 * Get the current MSI EQ queue head for the MSI-EQ described by the
2186 * given devhandle and msiqid.
2188 #define HV_FAST_PCI_MSIQ_GETHEAD 0xc6
2190 /* pci_msiq_sethead()
2191 * TRAP: HV_FAST_TRAP
2192 * FUNCTION: HV_FAST_PCI_MSIQ_SETHEAD
2197 * ERRORS: EINVAL Invalid devhandle or msiqid or msiqhead,
2198 * or MSI EQ is uninitialized
2200 * Set the current MSI EQ queue head for the MSI-EQ described by the
2201 * given devhandle and msiqid.
2203 #define HV_FAST_PCI_MSIQ_SETHEAD 0xc7
2205 /* pci_msiq_gettail()
2206 * TRAP: HV_FAST_TRAP
2207 * FUNCTION: HV_FAST_PCI_MSIQ_GETTAIL
2212 * ERRORS: EINVAL Invalid devhandle or msiqid
2214 * Get the current MSI EQ queue tail for the MSI-EQ described by the
2215 * given devhandle and msiqid.
2217 #define HV_FAST_PCI_MSIQ_GETTAIL 0xc8
2219 /* pci_msi_getvalid()
2220 * TRAP: HV_FAST_TRAP
2221 * FUNCTION: HV_FAST_PCI_MSI_GETVALID
2225 * RET1: msivalidstate
2226 * ERRORS: EINVAL Invalid devhandle or msinum
2228 * Get the current valid/enabled state for the MSI defined by the
2229 * given devhandle and msinum.
2231 #define HV_FAST_PCI_MSI_GETVALID 0xc9
2233 /* pci_msi_setvalid()
2234 * TRAP: HV_FAST_TRAP
2235 * FUNCTION: HV_FAST_PCI_MSI_SETVALID
2238 * ARG2: msivalidstate
2240 * ERRORS: EINVAL Invalid devhandle or msinum or msivalidstate
2242 * Set the current valid/enabled state for the MSI defined by the
2243 * given devhandle and msinum.
2245 #define HV_FAST_PCI_MSI_SETVALID 0xca
2247 /* pci_msi_getmsiq()
2248 * TRAP: HV_FAST_TRAP
2249 * FUNCTION: HV_FAST_PCI_MSI_GETMSIQ
2254 * ERRORS: EINVAL Invalid devhandle or msinum or MSI is unbound
2256 * Get the MSI EQ that the MSI defined by the given devhandle and
2257 * msinum is bound to.
2259 #define HV_FAST_PCI_MSI_GETMSIQ 0xcb
2261 /* pci_msi_setmsiq()
2262 * TRAP: HV_FAST_TRAP
2263 * FUNCTION: HV_FAST_PCI_MSI_SETMSIQ
2269 * ERRORS: EINVAL Invalid devhandle or msinum or msiqid
2271 * Set the MSI EQ that the MSI defined by the given devhandle and
2272 * msinum is bound to.
2274 #define HV_FAST_PCI_MSI_SETMSIQ 0xcc
2276 /* pci_msi_getstate()
2277 * TRAP: HV_FAST_TRAP
2278 * FUNCTION: HV_FAST_PCI_MSI_GETSTATE
2283 * ERRORS: EINVAL Invalid devhandle or msinum
2285 * Get the state of the MSI defined by the given devhandle and msinum.
2286 * If not initialized, return HV_MSISTATE_IDLE.
2288 #define HV_FAST_PCI_MSI_GETSTATE 0xcd
2290 /* pci_msi_setstate()
2291 * TRAP: HV_FAST_TRAP
2292 * FUNCTION: HV_FAST_PCI_MSI_SETSTATE
2297 * ERRORS: EINVAL Invalid devhandle or msinum or msistate
2299 * Set the state of the MSI defined by the given devhandle and msinum.
2301 #define HV_FAST_PCI_MSI_SETSTATE 0xce
2303 /* pci_msg_getmsiq()
2304 * TRAP: HV_FAST_TRAP
2305 * FUNCTION: HV_FAST_PCI_MSG_GETMSIQ
2310 * ERRORS: EINVAL Invalid devhandle or msgtype
2312 * Get the MSI EQ of the MSG defined by the given devhandle and msgtype.
2314 #define HV_FAST_PCI_MSG_GETMSIQ 0xd0
2316 /* pci_msg_setmsiq()
2317 * TRAP: HV_FAST_TRAP
2318 * FUNCTION: HV_FAST_PCI_MSG_SETMSIQ
2323 * ERRORS: EINVAL Invalid devhandle, msgtype, or msiqid
2325 * Set the MSI EQ of the MSG defined by the given devhandle and msgtype.
2327 #define HV_FAST_PCI_MSG_SETMSIQ 0xd1
2329 /* pci_msg_getvalid()
2330 * TRAP: HV_FAST_TRAP
2331 * FUNCTION: HV_FAST_PCI_MSG_GETVALID
2335 * RET1: msgvalidstate
2336 * ERRORS: EINVAL Invalid devhandle or msgtype
2338 * Get the valid/enabled state of the MSG defined by the given
2339 * devhandle and msgtype.
2341 #define HV_FAST_PCI_MSG_GETVALID 0xd2
2343 /* pci_msg_setvalid()
2344 * TRAP: HV_FAST_TRAP
2345 * FUNCTION: HV_FAST_PCI_MSG_SETVALID
2348 * ARG2: msgvalidstate
2350 * ERRORS: EINVAL Invalid devhandle or msgtype or msgvalidstate
2352 * Set the valid/enabled state of the MSG defined by the given
2353 * devhandle and msgtype.
2355 #define HV_FAST_PCI_MSG_SETVALID 0xd3
2357 /* PCI IOMMU v2 definitions and services
2359 * While the PCI IO definitions above is valid IOMMU v2 adds new PCI IO
2360 * definitions and services.
2362 * CTE Clump Table Entry. First level table entry in the ATU.
2365 * A 32-bit aligned list of pci_devices.
2368 * real address of a pci_device_list. 32-bit aligned.
2370 * iotte IOMMU translation table entry.
2373 * IO Attributes for IOMMU v2 mappings. In addition to
2374 * read, write IOMMU v2 supports relax ordering
2376 * io_page_list A 64-bit aligned list of real addresses. Each real
2377 * address in an io_page_list must be properly aligned
2378 * to the pagesize of the given IOTSB.
2380 * io_page_list_p Real address of an io_page_list, 64-bit aligned.
2382 * IOTSB IO Translation Storage Buffer. An aligned table of
2383 * IOTTEs. Each IOTSB has a pagesize, table size, and
2384 * virtual address associated with it that must match
2385 * a pagesize and table size supported by the un-derlying
2386 * hardware implementation. The alignment requirements
2387 * for an IOTSB depend on the pagesize used for that IOTSB.
2388 * Each IOTTE in an IOTSB maps one pagesize-sized page.
2389 * The size of the IOTSB dictates how large of a virtual
2390 * address space the IOTSB is capable of mapping.
2392 * iotsb_handle An opaque identifier for an IOTSB. A devhandle plus
2393 * iotsb_handle represents a binding of an IOTSB to a
2396 * iotsb_index Zero-based IOTTE number within an IOTSB.
2399 /* The index_count argument consists of two fields:
2400 * bits 63:48 #iottes and bits 47:0 iotsb_index
2402 #define HV_PCI_IOTSB_INDEX_COUNT(__iottes, __iotsb_index) \
2403 (((u64)(__iottes) << 48UL) | ((u64)(__iotsb_index)))
2406 * TRAP: HV_FAST_TRAP
2407 * FUNCTION: HV_FAST_PCI_IOTSB_CONF
2414 * RET1: iotsb_handle
2415 * ERRORS: EINVAL Invalid devhandle, size, iova, or pagesize
2416 * EBADALIGN r_addr is not properly aligned
2417 * ENORADDR r_addr is not a valid real address
2418 * ETOOMANY No further IOTSBs may be configured
2419 * EBUSY Duplicate devhandle, raddir, iova combination
2421 * Create an IOTSB suitable for the PCI root complex identified by devhandle,
2422 * for the DMA virtual address defined by the argument iova.
2424 * r_addr is the properly aligned base address of the IOTSB and size is the
2425 * IOTSB (table) size in bytes.The IOTSB is required to be zeroed prior to
2426 * being configured. If it contains any values other than zeros then the
2427 * behavior is undefined.
2429 * pagesize is the size of each page in the IOTSB. Note that the combination of
2430 * size (table size) and pagesize must be valid.
2432 * virt is the DMA virtual address this IOTSB will map.
2434 * If successful, the opaque 64-bit handle iotsb_handle is returned in ret1.
2435 * Once configured, privileged access to the IOTSB memory is prohibited and
2436 * creates undefined behavior. The only permitted access is indirect via these
2439 #define HV_FAST_PCI_IOTSB_CONF 0x190
2442 * TRAP: HV_FAST_TRAP
2443 * FUNCTION: HV_FAST_PCI_IOTSB_INFO
2445 * ARG1: iotsb_handle
2452 * ERRORS: EINVAL Invalid devhandle or iotsb_handle
2454 * This service returns configuration information about an IOTSB previously
2455 * created with pci_iotsb_conf.
2457 * iotsb_handle value 0 may be used with this service to inquire about the
2458 * legacy IOTSB that may or may not exist. If the service succeeds, the return
2459 * values describe the legacy IOTSB and I/O virtual addresses mapped by that
2460 * table. However, the table base address r_addr may contain the value -1 which
2461 * indicates a memory range that cannot be accessed or be reclaimed.
2463 * The return value #bound contains the number of PCI devices that iotsb_handle
2464 * is currently bound to.
2466 #define HV_FAST_PCI_IOTSB_INFO 0x191
2468 /* pci_iotsb_unconf()
2469 * TRAP: HV_FAST_TRAP
2470 * FUNCTION: HV_FAST_PCI_IOTSB_UNCONF
2472 * ARG1: iotsb_handle
2474 * ERRORS: EINVAL Invalid devhandle or iotsb_handle
2475 * EBUSY The IOTSB is bound and may not be unconfigured
2477 * This service unconfigures the IOTSB identified by the devhandle and
2478 * iotsb_handle arguments, previously created with pci_iotsb_conf.
2479 * The IOTSB must not be currently bound to any device or the service will fail
2481 * If the call succeeds, iotsb_handle is no longer valid.
2483 #define HV_FAST_PCI_IOTSB_UNCONF 0x192
2486 * TRAP: HV_FAST_TRAP
2487 * FUNCTION: HV_FAST_PCI_IOTSB_BIND
2489 * ARG1: iotsb_handle
2492 * ERRORS: EINVAL Invalid devhandle, iotsb_handle, or pci_device
2493 * EBUSY A PCI function is already bound to an IOTSB at the same
2494 * address range as specified by devhandle, iotsb_handle.
2496 * This service binds the PCI function specified by the argument pci_device to
2497 * the IOTSB specified by the arguments devhandle and iotsb_handle.
2499 * The PCI device function is bound to the specified IOTSB with the IOVA range
2500 * specified when the IOTSB was configured via pci_iotsb_conf. If the function
2501 * is already bound then it is unbound first.
2503 #define HV_FAST_PCI_IOTSB_BIND 0x193
2505 /* pci_iotsb_unbind()
2506 * TRAP: HV_FAST_TRAP
2507 * FUNCTION: HV_FAST_PCI_IOTSB_UNBIND
2509 * ARG1: iotsb_handle
2512 * ERRORS: EINVAL Invalid devhandle, iotsb_handle, or pci_device
2513 * ENOMAP The PCI function was not bound to the specified IOTSB
2515 * This service unbinds the PCI device specified by the argument pci_device
2516 * from the IOTSB identified * by the arguments devhandle and iotsb_handle.
2518 * If the PCI device is not bound to the specified IOTSB then this service will
2519 * fail with status ENOMAP
2521 #define HV_FAST_PCI_IOTSB_UNBIND 0x194
2523 /* pci_iotsb_get_binding()
2524 * TRAP: HV_FAST_TRAP
2525 * FUNCTION: HV_FAST_PCI_IOTSB_GET_BINDING
2527 * ARG1: iotsb_handle
2530 * RET1: iotsb_handle
2531 * ERRORS: EINVAL Invalid devhandle, pci_device, or iova
2532 * ENOMAP The PCI function is not bound to an IOTSB at iova
2534 * This service returns the IOTSB binding, iotsb_handle, for a given pci_device
2535 * and DMA virtual address, iova.
2537 * iova must be the base address of a DMA virtual address range as defined by
2538 * the iommu-address-ranges property in the root complex device node defined
2539 * by the argument devhandle.
2541 #define HV_FAST_PCI_IOTSB_GET_BINDING 0x195
2544 * TRAP: HV_FAST_TRAP
2545 * FUNCTION: HV_FAST_PCI_IOTSB_MAP
2547 * ARG1: iotsb_handle
2549 * ARG3: iotte_attributes
2550 * ARG4: io_page_list_p
2553 * ERRORS: EINVAL Invalid devhandle, iotsb_handle, #iottes,
2554 * iotsb_index or iotte_attributes
2555 * EBADALIGN Improperly aligned io_page_list_p or I/O page
2556 * address in the I/O page list.
2557 * ENORADDR Invalid io_page_list_p or I/O page address in
2558 * the I/O page list.
2560 * This service creates and flushes mappings in the IOTSB defined by the
2561 * arguments devhandle, iotsb.
2563 * The index_count argument consists of two fields. Bits 63:48 contain #iotte
2564 * and bits 47:0 contain iotsb_index
2566 * The first mapping is created in the IOTSB index specified by iotsb_index.
2567 * Subsequent mappings are created at iotsb_index+1 and so on.
2569 * The attributes of each mapping are defined by the argument iotte_attributes.
2571 * The io_page_list_p specifies the real address of the 64-bit-aligned list of
2572 * #iottes I/O page addresses. Each page address must be a properly aligned
2573 * real address of a page to be mapped in the IOTSB. The first entry in the I/O
2574 * page list contains the real address of the first page, the 2nd entry for the
2575 * 2nd page, and so on.
2577 * #iottes must be greater than zero.
2579 * The return value #mapped is the actual number of mappings created, which may
2580 * be less than or equal to the argument #iottes. If the function returns
2581 * successfully with a #mapped value less than the requested #iottes then the
2582 * caller should continue to invoke the service with updated iotsb_index,
2583 * #iottes, and io_page_list_p arguments until all pages are mapped.
2585 * This service must not be used to demap a mapping. In other words, all
2586 * mappings must be valid and have one or both of the RW attribute bits set.
2589 * It is implementation-defined whether I/O page real address validity checking
2590 * is done at time mappings are established or deferred until they are
2593 #define HV_FAST_PCI_IOTSB_MAP 0x196
2595 /* pci_iotsb_map_one()
2596 * TRAP: HV_FAST_TRAP
2597 * FUNCTION: HV_FAST_PCI_IOTSB_MAP_ONE
2599 * ARG1: iotsb_handle
2601 * ARG3: iotte_attributes
2604 * ERRORS: EINVAL Invalid devhandle,iotsb_handle, iotsb_index
2605 * or iotte_attributes
2606 * EBADALIGN Improperly aligned r_addr
2607 * ENORADDR Invalid r_addr
2609 * This service creates and flushes a single mapping in the IOTSB defined by the
2610 * arguments devhandle, iotsb.
2612 * The mapping for the page at r_addr is created at the IOTSB index specified by
2613 * iotsb_index with the attributes iotte_attributes.
2615 * This service must not be used to demap a mapping. In other words, the mapping
2616 * must be valid and have one or both of the RW attribute bits set.
2619 * It is implementation-defined whether I/O page real address validity checking
2620 * is done at time mappings are established or deferred until they are
2623 #define HV_FAST_PCI_IOTSB_MAP_ONE 0x197
2625 /* pci_iotsb_demap()
2626 * TRAP: HV_FAST_TRAP
2627 * FUNCTION: HV_FAST_PCI_IOTSB_DEMAP
2629 * ARG1: iotsb_handle
2634 * ERRORS: EINVAL Invalid devhandle, iotsb_handle, iotsb_index or #iottes
2636 * This service unmaps and flushes up to #iottes mappings starting at index
2637 * iotsb_index from the IOTSB defined by the arguments devhandle, iotsb.
2639 * #iottes must be greater than zero.
2641 * The actual number of IOTTEs unmapped is returned in #unmapped and may be less
2642 * than or equal to the requested number of IOTTEs, #iottes.
2644 * If #unmapped is less than #iottes, the caller should continue to invoke this
2645 * service with updated iotsb_index and #iottes arguments until all pages are
2648 #define HV_FAST_PCI_IOTSB_DEMAP 0x198
2650 /* pci_iotsb_getmap()
2651 * TRAP: HV_FAST_TRAP
2652 * FUNCTION: HV_FAST_PCI_IOTSB_GETMAP
2654 * ARG1: iotsb_handle
2658 * RET2: iotte_attributes
2659 * ERRORS: EINVAL Invalid devhandle, iotsb_handle, or iotsb_index
2660 * ENOMAP No mapping was found
2662 * This service returns the mapping specified by index iotsb_index from the
2663 * IOTSB defined by the arguments devhandle, iotsb.
2665 * Upon success, the real address of the mapping shall be returned in
2666 * r_addr and thethe IOTTE mapping attributes shall be returned in
2669 * The return value iotte_attributes may not include optional features used in
2670 * the call to create the mapping.
2672 #define HV_FAST_PCI_IOTSB_GETMAP 0x199
2674 /* pci_iotsb_sync_mappings()
2675 * TRAP: HV_FAST_TRAP
2676 * FUNCTION: HV_FAST_PCI_IOTSB_SYNC_MAPPINGS
2678 * ARG1: iotsb_handle
2683 * ERROS: EINVAL Invalid devhandle, iotsb_handle, iotsb_index, or #iottes
2685 * This service synchronizes #iottes mappings starting at index iotsb_index in
2686 * the IOTSB defined by the arguments devhandle, iotsb.
2688 * #iottes must be greater than zero.
2690 * The actual number of IOTTEs synchronized is returned in #synced, which may
2691 * be less than or equal to the requested number, #iottes.
2693 * Upon a successful return, #synced is less than #iottes, the caller should
2694 * continue to invoke this service with updated iotsb_index and #iottes
2695 * arguments until all pages are synchronized.
2697 #define HV_FAST_PCI_IOTSB_SYNC_MAPPINGS 0x19a
2699 /* Logical Domain Channel services. */
2701 #define LDC_CHANNEL_DOWN 0
2702 #define LDC_CHANNEL_UP 1
2703 #define LDC_CHANNEL_RESETTING 2
2706 * TRAP: HV_FAST_TRAP
2707 * FUNCTION: HV_FAST_LDC_TX_QCONF
2709 * ARG1: real address base of queue
2710 * ARG2: num entries in queue
2713 * Configure transmit queue for the LDC endpoint specified by the
2714 * given channel ID, to be placed at the given real address, and
2715 * be of the given num entries. Num entries must be a power of two.
2716 * The real address base of the queue must be aligned on the queue
2717 * size. Each queue entry is 64-bytes, so for example, a 32 entry
2718 * queue must be aligned on a 2048 byte real address boundary.
2720 * Upon configuration of a valid transmit queue the head and tail
2721 * pointers are set to a hypervisor specific identical value indicating
2722 * that the queue initially is empty.
2724 * The endpoint's transmit queue is un-configured if num entries is zero.
2726 * The maximum number of entries for each queue for a specific cpu may be
2727 * determined from the machine description. A transmit queue may be
2728 * specified even in the event that the LDC is down (peer endpoint has no
2729 * receive queue specified). Transmission will begin as soon as the peer
2730 * endpoint defines a receive queue.
2732 * It is recommended that a guest wait for a transmit queue to empty prior
2733 * to reconfiguring it, or un-configuring it. Re or un-configuring of a
2734 * non-empty transmit queue behaves exactly as defined above, however it
2735 * is undefined as to how many of the pending entries in the original queue
2736 * will be delivered prior to the re-configuration taking effect.
2737 * Furthermore, as the queue configuration causes a reset of the head and
2738 * tail pointers there is no way for a guest to determine how many entries
2739 * have been sent after the configuration operation.
2741 #define HV_FAST_LDC_TX_QCONF 0xe0
2744 * TRAP: HV_FAST_TRAP
2745 * FUNCTION: HV_FAST_LDC_TX_QINFO
2748 * RET1: real address base of queue
2749 * RET2: num entries in queue
2751 * Return the configuration info for the transmit queue of LDC endpoint
2752 * defined by the given channel ID. The real address is the currently
2753 * defined real address base of the defined queue, and num entries is the
2754 * size of the queue in terms of number of entries.
2756 * If the specified channel ID is a valid endpoint number, but no transmit
2757 * queue has been defined this service will return success, but with num
2758 * entries set to zero and the real address will have an undefined value.
2760 #define HV_FAST_LDC_TX_QINFO 0xe1
2762 /* ldc_tx_get_state()
2763 * TRAP: HV_FAST_TRAP
2764 * FUNCTION: HV_FAST_LDC_TX_GET_STATE
2769 * RET3: channel state
2771 * Return the transmit state, and the head and tail queue pointers, for
2772 * the transmit queue of the LDC endpoint defined by the given channel ID.
2773 * The head and tail values are the byte offset of the head and tail
2774 * positions of the transmit queue for the specified endpoint.
2776 #define HV_FAST_LDC_TX_GET_STATE 0xe2
2778 /* ldc_tx_set_qtail()
2779 * TRAP: HV_FAST_TRAP
2780 * FUNCTION: HV_FAST_LDC_TX_SET_QTAIL
2785 * Update the tail pointer for the transmit queue associated with the LDC
2786 * endpoint defined by the given channel ID. The tail offset specified
2787 * must be aligned on a 64 byte boundary, and calculated so as to increase
2788 * the number of pending entries on the transmit queue. Any attempt to
2789 * decrease the number of pending transmit queue entires is considered
2790 * an invalid tail offset and will result in an EINVAL error.
2792 * Since the tail of the transmit queue may not be moved backwards, the
2793 * transmit queue may be flushed by configuring a new transmit queue,
2794 * whereupon the hypervisor will configure the initial transmit head and
2795 * tail pointers to be equal.
2797 #define HV_FAST_LDC_TX_SET_QTAIL 0xe3
2800 * TRAP: HV_FAST_TRAP
2801 * FUNCTION: HV_FAST_LDC_RX_QCONF
2803 * ARG1: real address base of queue
2804 * ARG2: num entries in queue
2807 * Configure receive queue for the LDC endpoint specified by the
2808 * given channel ID, to be placed at the given real address, and
2809 * be of the given num entries. Num entries must be a power of two.
2810 * The real address base of the queue must be aligned on the queue
2811 * size. Each queue entry is 64-bytes, so for example, a 32 entry
2812 * queue must be aligned on a 2048 byte real address boundary.
2814 * The endpoint's transmit queue is un-configured if num entries is zero.
2816 * If a valid receive queue is specified for a local endpoint the LDC is
2817 * in the up state for the purpose of transmission to this endpoint.
2819 * The maximum number of entries for each queue for a specific cpu may be
2820 * determined from the machine description.
2822 * As receive queue configuration causes a reset of the queue's head and
2823 * tail pointers there is no way for a gues to determine how many entries
2824 * have been received between a preceding ldc_get_rx_state() API call
2825 * and the completion of the configuration operation. It should be noted
2826 * that datagram delivery is not guaranteed via domain channels anyway,
2827 * and therefore any higher protocol should be resilient to datagram
2828 * loss if necessary. However, to overcome this specific race potential
2829 * it is recommended, for example, that a higher level protocol be employed
2830 * to ensure either retransmission, or ensure that no datagrams are pending
2831 * on the peer endpoint's transmit queue prior to the configuration process.
2833 #define HV_FAST_LDC_RX_QCONF 0xe4
2836 * TRAP: HV_FAST_TRAP
2837 * FUNCTION: HV_FAST_LDC_RX_QINFO
2840 * RET1: real address base of queue
2841 * RET2: num entries in queue
2843 * Return the configuration info for the receive queue of LDC endpoint
2844 * defined by the given channel ID. The real address is the currently
2845 * defined real address base of the defined queue, and num entries is the
2846 * size of the queue in terms of number of entries.
2848 * If the specified channel ID is a valid endpoint number, but no receive
2849 * queue has been defined this service will return success, but with num
2850 * entries set to zero and the real address will have an undefined value.
2852 #define HV_FAST_LDC_RX_QINFO 0xe5
2854 /* ldc_rx_get_state()
2855 * TRAP: HV_FAST_TRAP
2856 * FUNCTION: HV_FAST_LDC_RX_GET_STATE
2861 * RET3: channel state
2863 * Return the receive state, and the head and tail queue pointers, for
2864 * the receive queue of the LDC endpoint defined by the given channel ID.
2865 * The head and tail values are the byte offset of the head and tail
2866 * positions of the receive queue for the specified endpoint.
2868 #define HV_FAST_LDC_RX_GET_STATE 0xe6
2870 /* ldc_rx_set_qhead()
2871 * TRAP: HV_FAST_TRAP
2872 * FUNCTION: HV_FAST_LDC_RX_SET_QHEAD
2877 * Update the head pointer for the receive queue associated with the LDC
2878 * endpoint defined by the given channel ID. The head offset specified
2879 * must be aligned on a 64 byte boundary, and calculated so as to decrease
2880 * the number of pending entries on the receive queue. Any attempt to
2881 * increase the number of pending receive queue entires is considered
2882 * an invalid head offset and will result in an EINVAL error.
2884 * The receive queue may be flushed by setting the head offset equal
2885 * to the current tail offset.
2887 #define HV_FAST_LDC_RX_SET_QHEAD 0xe7
2889 /* LDC Map Table Entry. Each slot is defined by a translation table
2890 * entry, as specified by the LDC_MTE_* bits below, and a 64-bit
2891 * hypervisor invalidation cookie.
2893 #define LDC_MTE_PADDR 0x0fffffffffffe000 /* pa[55:13] */
2894 #define LDC_MTE_COPY_W 0x0000000000000400 /* copy write access */
2895 #define LDC_MTE_COPY_R 0x0000000000000200 /* copy read access */
2896 #define LDC_MTE_IOMMU_W 0x0000000000000100 /* IOMMU write access */
2897 #define LDC_MTE_IOMMU_R 0x0000000000000080 /* IOMMU read access */
2898 #define LDC_MTE_EXEC 0x0000000000000040 /* execute */
2899 #define LDC_MTE_WRITE 0x0000000000000020 /* read */
2900 #define LDC_MTE_READ 0x0000000000000010 /* write */
2901 #define LDC_MTE_SZALL 0x000000000000000f /* page size bits */
2902 #define LDC_MTE_SZ16GB 0x0000000000000007 /* 16GB page */
2903 #define LDC_MTE_SZ2GB 0x0000000000000006 /* 2GB page */
2904 #define LDC_MTE_SZ256MB 0x0000000000000005 /* 256MB page */
2905 #define LDC_MTE_SZ32MB 0x0000000000000004 /* 32MB page */
2906 #define LDC_MTE_SZ4MB 0x0000000000000003 /* 4MB page */
2907 #define LDC_MTE_SZ512K 0x0000000000000002 /* 512K page */
2908 #define LDC_MTE_SZ64K 0x0000000000000001 /* 64K page */
2909 #define LDC_MTE_SZ8K 0x0000000000000000 /* 8K page */
2911 #ifndef __ASSEMBLY__
2912 struct ldc_mtable_entry {
2914 unsigned long cookie;
2918 /* ldc_set_map_table()
2919 * TRAP: HV_FAST_TRAP
2920 * FUNCTION: HV_FAST_LDC_SET_MAP_TABLE
2922 * ARG1: table real address
2926 * Register the MTE table at the given table real address, with the
2927 * specified num entries, for the LDC indicated by the given channel
2930 #define HV_FAST_LDC_SET_MAP_TABLE 0xea
2932 /* ldc_get_map_table()
2933 * TRAP: HV_FAST_TRAP
2934 * FUNCTION: HV_FAST_LDC_GET_MAP_TABLE
2937 * RET1: table real address
2940 * Return the configuration of the current mapping table registered
2941 * for the given channel ID.
2943 #define HV_FAST_LDC_GET_MAP_TABLE 0xeb
2945 #define LDC_COPY_IN 0
2946 #define LDC_COPY_OUT 1
2949 * TRAP: HV_FAST_TRAP
2950 * FUNCTION: HV_FAST_LDC_COPY
2952 * ARG1: LDC_COPY_* direction code
2953 * ARG2: target real address
2954 * ARG3: local real address
2955 * ARG4: length in bytes
2957 * RET1: actual length in bytes
2959 #define HV_FAST_LDC_COPY 0xec
2961 #define LDC_MEM_READ 1
2962 #define LDC_MEM_WRITE 2
2963 #define LDC_MEM_EXEC 4
2966 * TRAP: HV_FAST_TRAP
2967 * FUNCTION: HV_FAST_LDC_MAPIN
2971 * RET1: real address
2972 * RET2: LDC_MEM_* permissions
2974 #define HV_FAST_LDC_MAPIN 0xed
2977 * TRAP: HV_FAST_TRAP
2978 * FUNCTION: HV_FAST_LDC_UNMAP
2979 * ARG0: real address
2982 #define HV_FAST_LDC_UNMAP 0xee
2985 * TRAP: HV_FAST_TRAP
2986 * FUNCTION: HV_FAST_LDC_REVOKE
2989 * ARG2: ldc_mtable_entry cookie
2992 #define HV_FAST_LDC_REVOKE 0xef
2994 #ifndef __ASSEMBLY__
2995 unsigned long sun4v_ldc_tx_qconf(unsigned long channel,
2997 unsigned long num_entries);
2998 unsigned long sun4v_ldc_tx_qinfo(unsigned long channel,
3000 unsigned long *num_entries);
3001 unsigned long sun4v_ldc_tx_get_state(unsigned long channel,
3002 unsigned long *head_off,
3003 unsigned long *tail_off,
3004 unsigned long *chan_state);
3005 unsigned long sun4v_ldc_tx_set_qtail(unsigned long channel,
3006 unsigned long tail_off);
3007 unsigned long sun4v_ldc_rx_qconf(unsigned long channel,
3009 unsigned long num_entries);
3010 unsigned long sun4v_ldc_rx_qinfo(unsigned long channel,
3012 unsigned long *num_entries);
3013 unsigned long sun4v_ldc_rx_get_state(unsigned long channel,
3014 unsigned long *head_off,
3015 unsigned long *tail_off,
3016 unsigned long *chan_state);
3017 unsigned long sun4v_ldc_rx_set_qhead(unsigned long channel,
3018 unsigned long head_off);
3019 unsigned long sun4v_ldc_set_map_table(unsigned long channel,
3021 unsigned long num_entries);
3022 unsigned long sun4v_ldc_get_map_table(unsigned long channel,
3024 unsigned long *num_entries);
3025 unsigned long sun4v_ldc_copy(unsigned long channel,
3026 unsigned long dir_code,
3027 unsigned long tgt_raddr,
3028 unsigned long lcl_raddr,
3030 unsigned long *actual_len);
3031 unsigned long sun4v_ldc_mapin(unsigned long channel,
3032 unsigned long cookie,
3034 unsigned long *perm);
3035 unsigned long sun4v_ldc_unmap(unsigned long ra);
3036 unsigned long sun4v_ldc_revoke(unsigned long channel,
3037 unsigned long cookie,
3038 unsigned long mte_cookie);
3041 /* Performance counter services. */
3043 #define HV_PERF_JBUS_PERF_CTRL_REG 0x00
3044 #define HV_PERF_JBUS_PERF_CNT_REG 0x01
3045 #define HV_PERF_DRAM_PERF_CTRL_REG_0 0x02
3046 #define HV_PERF_DRAM_PERF_CNT_REG_0 0x03
3047 #define HV_PERF_DRAM_PERF_CTRL_REG_1 0x04
3048 #define HV_PERF_DRAM_PERF_CNT_REG_1 0x05
3049 #define HV_PERF_DRAM_PERF_CTRL_REG_2 0x06
3050 #define HV_PERF_DRAM_PERF_CNT_REG_2 0x07
3051 #define HV_PERF_DRAM_PERF_CTRL_REG_3 0x08
3052 #define HV_PERF_DRAM_PERF_CNT_REG_3 0x09
3055 * TRAP: HV_FAST_TRAP
3056 * FUNCTION: HV_FAST_GET_PERFREG
3057 * ARG0: performance reg number
3059 * RET1: performance reg value
3060 * ERRORS: EINVAL Invalid performance register number
3061 * ENOACCESS No access allowed to performance counters
3063 * Read the value of the given DRAM/JBUS performance counter/control register.
3065 #define HV_FAST_GET_PERFREG 0x100
3068 * TRAP: HV_FAST_TRAP
3069 * FUNCTION: HV_FAST_SET_PERFREG
3070 * ARG0: performance reg number
3071 * ARG1: performance reg value
3073 * ERRORS: EINVAL Invalid performance register number
3074 * ENOACCESS No access allowed to performance counters
3076 * Write the given performance reg value to the given DRAM/JBUS
3077 * performance counter/control register.
3079 #define HV_FAST_SET_PERFREG 0x101
3081 #define HV_N2_PERF_SPARC_CTL 0x0
3082 #define HV_N2_PERF_DRAM_CTL0 0x1
3083 #define HV_N2_PERF_DRAM_CNT0 0x2
3084 #define HV_N2_PERF_DRAM_CTL1 0x3
3085 #define HV_N2_PERF_DRAM_CNT1 0x4
3086 #define HV_N2_PERF_DRAM_CTL2 0x5
3087 #define HV_N2_PERF_DRAM_CNT2 0x6
3088 #define HV_N2_PERF_DRAM_CTL3 0x7
3089 #define HV_N2_PERF_DRAM_CNT3 0x8
3091 #define HV_FAST_N2_GET_PERFREG 0x104
3092 #define HV_FAST_N2_SET_PERFREG 0x105
3094 #ifndef __ASSEMBLY__
3095 unsigned long sun4v_niagara_getperf(unsigned long reg,
3096 unsigned long *val);
3097 unsigned long sun4v_niagara_setperf(unsigned long reg,
3099 unsigned long sun4v_niagara2_getperf(unsigned long reg,
3100 unsigned long *val);
3101 unsigned long sun4v_niagara2_setperf(unsigned long reg,
3105 /* MMU statistics services.
3107 * The hypervisor maintains MMU statistics and privileged code provides
3108 * a buffer where these statistics can be collected. It is continually
3109 * updated once configured. The layout is as follows:
3111 #ifndef __ASSEMBLY__
3112 struct hv_mmu_statistics {
3113 unsigned long immu_tsb_hits_ctx0_8k_tte;
3114 unsigned long immu_tsb_ticks_ctx0_8k_tte;
3115 unsigned long immu_tsb_hits_ctx0_64k_tte;
3116 unsigned long immu_tsb_ticks_ctx0_64k_tte;
3117 unsigned long __reserved1[2];
3118 unsigned long immu_tsb_hits_ctx0_4mb_tte;
3119 unsigned long immu_tsb_ticks_ctx0_4mb_tte;
3120 unsigned long __reserved2[2];
3121 unsigned long immu_tsb_hits_ctx0_256mb_tte;
3122 unsigned long immu_tsb_ticks_ctx0_256mb_tte;
3123 unsigned long __reserved3[4];
3124 unsigned long immu_tsb_hits_ctxnon0_8k_tte;
3125 unsigned long immu_tsb_ticks_ctxnon0_8k_tte;
3126 unsigned long immu_tsb_hits_ctxnon0_64k_tte;
3127 unsigned long immu_tsb_ticks_ctxnon0_64k_tte;
3128 unsigned long __reserved4[2];
3129 unsigned long immu_tsb_hits_ctxnon0_4mb_tte;
3130 unsigned long immu_tsb_ticks_ctxnon0_4mb_tte;
3131 unsigned long __reserved5[2];
3132 unsigned long immu_tsb_hits_ctxnon0_256mb_tte;
3133 unsigned long immu_tsb_ticks_ctxnon0_256mb_tte;
3134 unsigned long __reserved6[4];
3135 unsigned long dmmu_tsb_hits_ctx0_8k_tte;
3136 unsigned long dmmu_tsb_ticks_ctx0_8k_tte;
3137 unsigned long dmmu_tsb_hits_ctx0_64k_tte;
3138 unsigned long dmmu_tsb_ticks_ctx0_64k_tte;
3139 unsigned long __reserved7[2];
3140 unsigned long dmmu_tsb_hits_ctx0_4mb_tte;
3141 unsigned long dmmu_tsb_ticks_ctx0_4mb_tte;
3142 unsigned long __reserved8[2];
3143 unsigned long dmmu_tsb_hits_ctx0_256mb_tte;
3144 unsigned long dmmu_tsb_ticks_ctx0_256mb_tte;
3145 unsigned long __reserved9[4];
3146 unsigned long dmmu_tsb_hits_ctxnon0_8k_tte;
3147 unsigned long dmmu_tsb_ticks_ctxnon0_8k_tte;
3148 unsigned long dmmu_tsb_hits_ctxnon0_64k_tte;
3149 unsigned long dmmu_tsb_ticks_ctxnon0_64k_tte;
3150 unsigned long __reserved10[2];
3151 unsigned long dmmu_tsb_hits_ctxnon0_4mb_tte;
3152 unsigned long dmmu_tsb_ticks_ctxnon0_4mb_tte;
3153 unsigned long __reserved11[2];
3154 unsigned long dmmu_tsb_hits_ctxnon0_256mb_tte;
3155 unsigned long dmmu_tsb_ticks_ctxnon0_256mb_tte;
3156 unsigned long __reserved12[4];
3161 * TRAP: HV_FAST_TRAP
3162 * FUNCTION: HV_FAST_MMUSTAT_CONF
3163 * ARG0: real address
3165 * RET1: real address
3166 * ERRORS: ENORADDR Invalid real address
3167 * EBADALIGN Real address not aligned on 64-byte boundary
3168 * EBADTRAP API not supported on this processor
3170 * Enable MMU statistic gathering using the buffer at the given real
3171 * address on the current virtual CPU. The new buffer real address
3172 * is given in ARG1, and the previously specified buffer real address
3173 * is returned in RET1, or is returned as zero for the first invocation.
3175 * If the passed in real address argument is zero, this will disable
3176 * MMU statistic collection on the current virtual CPU. If an error is
3177 * returned then no statistics are collected.
3179 * The buffer contents should be initialized to all zeros before being
3180 * given to the hypervisor or else the statistics will be meaningless.
3182 #define HV_FAST_MMUSTAT_CONF 0x102
3185 * TRAP: HV_FAST_TRAP
3186 * FUNCTION: HV_FAST_MMUSTAT_INFO
3188 * RET1: real address
3189 * ERRORS: EBADTRAP API not supported on this processor
3191 * Return the current state and real address of the currently configured
3192 * MMU statistics buffer on the current virtual CPU.
3194 #define HV_FAST_MMUSTAT_INFO 0x103
3196 #ifndef __ASSEMBLY__
3197 unsigned long sun4v_mmustat_conf(unsigned long ra, unsigned long *orig_ra);
3198 unsigned long sun4v_mmustat_info(unsigned long *ra);
3201 /* NCS crypto services */
3203 /* ncs_request() sub-function numbers */
3204 #define HV_NCS_QCONF 0x01
3205 #define HV_NCS_QTAIL_UPDATE 0x02
3207 #ifndef __ASSEMBLY__
3208 struct hv_ncs_queue_entry {
3209 /* MAU Control Register */
3210 unsigned long mau_control;
3211 #define MAU_CONTROL_INV_PARITY 0x0000000000002000
3212 #define MAU_CONTROL_STRAND 0x0000000000001800
3213 #define MAU_CONTROL_BUSY 0x0000000000000400
3214 #define MAU_CONTROL_INT 0x0000000000000200
3215 #define MAU_CONTROL_OP 0x00000000000001c0
3216 #define MAU_CONTROL_OP_SHIFT 6
3217 #define MAU_OP_LOAD_MA_MEMORY 0x0
3218 #define MAU_OP_STORE_MA_MEMORY 0x1
3219 #define MAU_OP_MODULAR_MULT 0x2
3220 #define MAU_OP_MODULAR_REDUCE 0x3
3221 #define MAU_OP_MODULAR_EXP_LOOP 0x4
3222 #define MAU_CONTROL_LEN 0x000000000000003f
3223 #define MAU_CONTROL_LEN_SHIFT 0
3225 /* Real address of bytes to load or store bytes
3226 * into/out-of the MAU.
3228 unsigned long mau_mpa;
3230 /* Modular Arithmetic MA Offset Register. */
3231 unsigned long mau_ma;
3233 /* Modular Arithmetic N Prime Register. */
3234 unsigned long mau_np;
3237 struct hv_ncs_qconf_arg {
3238 unsigned long mid; /* MAU ID, 1 per core on Niagara */
3239 unsigned long base; /* Real address base of queue */
3240 unsigned long end; /* Real address end of queue */
3241 unsigned long num_ents; /* Number of entries in queue */
3244 struct hv_ncs_qtail_update_arg {
3245 unsigned long mid; /* MAU ID, 1 per core on Niagara */
3246 unsigned long tail; /* New tail index to use */
3247 unsigned long syncflag; /* only SYNCFLAG_SYNC is implemented */
3248 #define HV_NCS_SYNCFLAG_SYNC 0x00
3249 #define HV_NCS_SYNCFLAG_ASYNC 0x01
3254 * TRAP: HV_FAST_TRAP
3255 * FUNCTION: HV_FAST_NCS_REQUEST
3256 * ARG0: NCS sub-function
3257 * ARG1: sub-function argument real address
3258 * ARG2: size in bytes of sub-function argument
3261 * The MAU chip of the Niagara processor is not directly accessible
3262 * to privileged code, instead it is programmed indirectly via this
3265 * The interfaces defines a queue of MAU operations to perform.
3266 * Privileged code registers a queue with the hypervisor by invoking
3267 * this HVAPI with the HV_NCS_QCONF sub-function, which defines the
3268 * base, end, and number of entries of the queue. Each queue entry
3269 * contains a MAU register struct block.
3271 * The privileged code then proceeds to add entries to the queue and
3272 * then invoke the HV_NCS_QTAIL_UPDATE sub-function. Since only
3273 * synchronous operations are supported by the current hypervisor,
3274 * HV_NCS_QTAIL_UPDATE will run all the pending queue entries to
3275 * completion and return HV_EOK, or return an error code.
3277 * The real address of the sub-function argument must be aligned on at
3278 * least an 8-byte boundary.
3280 * The tail argument of HV_NCS_QTAIL_UPDATE is an index, not a byte
3281 * offset, into the queue and must be less than or equal the 'num_ents'
3282 * argument given in the HV_NCS_QCONF call.
3284 #define HV_FAST_NCS_REQUEST 0x110
3286 #ifndef __ASSEMBLY__
3287 unsigned long sun4v_ncs_request(unsigned long request,
3288 unsigned long arg_ra,
3289 unsigned long arg_size);
3292 #define HV_FAST_FIRE_GET_PERFREG 0x120
3293 #define HV_FAST_FIRE_SET_PERFREG 0x121
3295 #define HV_FAST_REBOOT_DATA_SET 0x172
3297 #ifndef __ASSEMBLY__
3298 unsigned long sun4v_reboot_data_set(unsigned long ra,
3302 #define HV_FAST_VT_GET_PERFREG 0x184
3303 #define HV_FAST_VT_SET_PERFREG 0x185
3305 #ifndef __ASSEMBLY__
3306 unsigned long sun4v_vt_get_perfreg(unsigned long reg_num,
3307 unsigned long *reg_val);
3308 unsigned long sun4v_vt_set_perfreg(unsigned long reg_num,
3309 unsigned long reg_val);
3312 #define HV_FAST_T5_GET_PERFREG 0x1a8
3313 #define HV_FAST_T5_SET_PERFREG 0x1a9
3315 #ifndef __ASSEMBLY__
3316 unsigned long sun4v_t5_get_perfreg(unsigned long reg_num,
3317 unsigned long *reg_val);
3318 unsigned long sun4v_t5_set_perfreg(unsigned long reg_num,
3319 unsigned long reg_val);
3323 #define HV_FAST_M7_GET_PERFREG 0x43
3324 #define HV_FAST_M7_SET_PERFREG 0x44
3326 #ifndef __ASSEMBLY__
3327 unsigned long sun4v_m7_get_perfreg(unsigned long reg_num,
3328 unsigned long *reg_val);
3329 unsigned long sun4v_m7_set_perfreg(unsigned long reg_num,
3330 unsigned long reg_val);
3333 /* Function numbers for HV_CORE_TRAP. */
3334 #define HV_CORE_SET_VER 0x00
3335 #define HV_CORE_PUTCHAR 0x01
3336 #define HV_CORE_EXIT 0x02
3337 #define HV_CORE_GET_VER 0x03
3339 /* Hypervisor API groups for use with HV_CORE_SET_VER and
3342 #define HV_GRP_SUN4V 0x0000
3343 #define HV_GRP_CORE 0x0001
3344 #define HV_GRP_INTR 0x0002
3345 #define HV_GRP_SOFT_STATE 0x0003
3346 #define HV_GRP_TM 0x0080
3347 #define HV_GRP_PCI 0x0100
3348 #define HV_GRP_LDOM 0x0101
3349 #define HV_GRP_SVC_CHAN 0x0102
3350 #define HV_GRP_NCS 0x0103
3351 #define HV_GRP_RNG 0x0104
3352 #define HV_GRP_PBOOT 0x0105
3353 #define HV_GRP_TPM 0x0107
3354 #define HV_GRP_SDIO 0x0108
3355 #define HV_GRP_SDIO_ERR 0x0109
3356 #define HV_GRP_REBOOT_DATA 0x0110
3357 #define HV_GRP_ATU 0x0111
3358 #define HV_GRP_M7_PERF 0x0114
3359 #define HV_GRP_NIAG_PERF 0x0200
3360 #define HV_GRP_FIRE_PERF 0x0201
3361 #define HV_GRP_N2_CPU 0x0202
3362 #define HV_GRP_NIU 0x0204
3363 #define HV_GRP_VF_CPU 0x0205
3364 #define HV_GRP_KT_CPU 0x0209
3365 #define HV_GRP_VT_CPU 0x020c
3366 #define HV_GRP_T5_CPU 0x0211
3367 #define HV_GRP_DIAG 0x0300
3369 #ifndef __ASSEMBLY__
3370 unsigned long sun4v_get_version(unsigned long group,
3371 unsigned long *major,
3372 unsigned long *minor);
3373 unsigned long sun4v_set_version(unsigned long group,
3374 unsigned long major,
3375 unsigned long minor,
3376 unsigned long *actual_minor);
3378 int sun4v_hvapi_register(unsigned long group, unsigned long major,
3379 unsigned long *minor);
3380 void sun4v_hvapi_unregister(unsigned long group);
3381 int sun4v_hvapi_get(unsigned long group,
3382 unsigned long *major,
3383 unsigned long *minor);
3384 void sun4v_hvapi_init(void);
3387 #endif /* !(_SPARC64_HYPERVISOR_H) */
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