1 # SPDX-License-Identifier: GPL-2.0
2 menu "Memory management options"
5 bool "Support for memory management hardware"
9 Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to
10 boot on these systems, this option must not be set.
12 On other systems (such as the SH-3 and 4) where an MMU exists,
13 turning this off will boot the kernel on these machines with the
14 MMU implicitly switched off.
18 default "0x80000000" if MMU
21 config ARCH_FORCE_MAX_ORDER
22 int "Order of maximal physically contiguous allocations"
23 default "8" if PAGE_SIZE_16KB
24 default "6" if PAGE_SIZE_64KB
28 The kernel page allocator limits the size of maximal physically
29 contiguous allocations. The limit is called MAX_PAGE:_ORDER and it
30 defines the maximal power of two of number of pages that can be
31 allocated as a single contiguous block. This option allows
32 overriding the default setting when ability to allocate very
33 large blocks of physically contiguous memory is required.
35 The page size is not necessarily 4KB. Keep this in mind when
36 choosing a value for this option.
38 Don't change if unsure.
41 hex "Physical memory start address"
44 Computers built with Hitachi SuperH processors always
45 map the ROM starting at address zero. But the processor
46 does not specify the range that RAM takes.
48 The physical memory (RAM) start address will be automatically
49 set to 08000000. Other platforms, such as the Solution Engine
50 boards typically map RAM at 0C000000.
52 Tweak this only when porting to a new machine which does not
53 already have a defconfig. Changing it from the known correct
54 value on any of the known systems will only lead to disaster.
57 hex "Physical memory size"
60 This sets the default memory size assumed by your SH kernel. It can
61 be overridden as normal by the 'mem=' argument on the kernel command
62 line. If unsure, consult your board specifications or just leave it
63 as 0x04000000 which was the default value before this became
66 # Physical addressing modes
70 select UNCACHED_MAPPING
77 bool "Support 32-bit physical addressing through PMB"
78 depends on MMU && CPU_SH4A && !CPU_SH4AL_DSP
80 select UNCACHED_MAPPING
82 If you say Y here, physical addressing will be extended to
83 32-bits through the SH-4A PMB. If this is not set, legacy
84 29-bit physical addressing will be used.
88 depends on (CPU_SHX2 || CPU_SHX3) && MMU
91 bool "Support vsyscall page"
92 depends on MMU && (CPU_SH3 || CPU_SH4)
95 This will enable support for the kernel mapping a vDSO page
96 in process space, and subsequently handing down the entry point
97 to the libc through the ELF auxiliary vector.
99 From the kernel side this is used for the signal trampoline.
100 For systems with an MMU that can afford to give up a page,
101 (the default value) say Y.
104 bool "Non-Uniform Memory Access (NUMA) Support"
105 depends on MMU && SYS_SUPPORTS_NUMA
106 select ARCH_WANT_NUMA_VARIABLE_LOCALITY
109 Some SH systems have many various memories scattered around
110 the address space, each with varying latencies. This enables
111 support for these blocks by binding them to nodes and allowing
112 memory policies to be used for prioritizing and controlling
113 allocation behaviour.
117 default "3" if CPU_SUBTYPE_SHX3
121 config ARCH_FLATMEM_ENABLE
125 config ARCH_SPARSEMEM_ENABLE
127 select SPARSEMEM_STATIC
129 config ARCH_SPARSEMEM_DEFAULT
132 config ARCH_SELECT_MEMORY_MODEL
135 config ARCH_MEMORY_PROBE
137 depends on MEMORY_HOTPLUG
143 config UNCACHED_MAPPING
146 config HAVE_SRAM_POOL
148 select GENERIC_ALLOCATOR
151 prompt "Kernel page size"
152 default PAGE_SIZE_4KB
157 This is the default page size used by all SuperH CPUs.
161 depends on !MMU || X2TLB
163 This enables 8kB pages as supported by SH-X2 and later MMUs.
165 config PAGE_SIZE_16KB
169 This enables 16kB pages on MMU-less SH systems.
171 config PAGE_SIZE_64KB
173 depends on !MMU || CPU_SH4
175 This enables support for 64kB pages, possible on all SH-4
181 prompt "HugeTLB page size"
182 depends on HUGETLB_PAGE
183 default HUGETLB_PAGE_SIZE_1MB if PAGE_SIZE_64KB
184 default HUGETLB_PAGE_SIZE_64K
186 config HUGETLB_PAGE_SIZE_64K
188 depends on !PAGE_SIZE_64KB
190 config HUGETLB_PAGE_SIZE_256K
194 config HUGETLB_PAGE_SIZE_1MB
197 config HUGETLB_PAGE_SIZE_4MB
201 config HUGETLB_PAGE_SIZE_64MB
208 bool "Multi-core scheduler support"
212 Multi-core scheduler support improves the CPU scheduler's decision
213 making when dealing with multi-core CPU chips at a cost of slightly
214 increased overhead in some places. If unsure say N here.
218 menu "Cache configuration"
220 config SH7705_CACHE_32KB
221 bool "Enable 32KB cache size for SH7705"
222 depends on CPU_SUBTYPE_SH7705
227 default CACHE_WRITEBACK if CPU_SH2A || CPU_SH3 || CPU_SH4
228 default CACHE_WRITETHROUGH if (CPU_SH2 && !CPU_SH2A)
230 config CACHE_WRITEBACK
233 config CACHE_WRITETHROUGH
236 Selecting this option will configure the caches in write-through
237 mode, as opposed to the default write-back configuration.
239 Since there's sill some aliasing issues on SH-4, this option will
240 unfortunately still require the majority of flushing functions to
241 be implemented to deal with aliasing.