1 /* SPDX-License-Identifier: GPL-2.0+ WITH GCC-exception-2.0
3 Copyright (C) 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
5 Free Software Foundation, Inc.
8 !! libgcc routines for the Renesas / SuperH SH CPUs.
9 !! Contributed by Steve Chamberlain.
12 !! ashiftrt_r4_x, ___ashrsi3, ___ashlsi3, ___lshrsi3 routines
13 !! recoded in assembly by Toshiyasu Morita
16 /* SH2 optimizations for ___ashrsi3, ___ashlsi3, ___lshrsi3 and
17 ELF local label prefixes by J"orn Rennecke
20 /* This code used shld, thus is not suitable for SH1 / SH2. */
22 /* Signed / unsigned division without use of FPU, optimized for SH4.
23 Uses a lookup table for divisors in the range -128 .. +128, and
24 div1 with case distinction for larger divisors in three more ranges.
25 The code is lumped together with the table to allow the use of mova. */
26 #ifdef CONFIG_CPU_LITTLE_ENDIAN
39 .set __udivsi3_i4, __udivsi3_i4i
40 .type __udivsi3_i4i, @function
121 mov.b r0,@(L_LSWMSB,r15)
155 .global __sdivsi3_i4i
158 .set __sdivsi3_i4, __sdivsi3_i4i
159 .set __sdivsi3, __sdivsi3_i4i
160 .type __sdivsi3_i4i, @function
161 /* This is link-compatible with a __sdivsi3 call,
162 but we effectively clobber only r1. */
195 mov.b r0,@(L_MSWLSB,r15)
201 mov.b r0,@(L_LSWMSB,r15)
206 mov.l @r15+,r4 ! zero-extension and swap using LS unit.
218 mova div_table_inv,r0
221 mova div_table_clz,r0
255 mov.b r0,@(L_MSWLSB,r15)
261 mov.b r0,@(L_LSWMSB,r15)
266 mov.l @r15+,r4 ! zero-extension and swap using LS unit.
288 mov.b r0,@(L_LSWMSB,r15)
291 bra div_ge64k_neg_end
313 /* This table has been generated by divtab-sh4.c. */
444 /* Lookup table translating positive divisor to index into table of
445 normalized inverse. N.B. the '0' entry is also the last entry of the
446 previous table, and causes an unaligned access for division by zero. */
577 /* 1/64 .. 1/127, normalized. There is an implicit leading 1 in bit 32. */
645 /* maximum error: 0.987342 scaled: 0.921875*/