2 * Disassemble SuperH instructions.
4 * Copyright (C) 1999 kaz Kojima
5 * Copyright (C) 2008 Paul Mundt
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
11 #include <linux/kernel.h>
12 #include <linux/string.h>
13 #include <linux/uaccess.h>
15 #include <asm/ptrace.h>
18 * Format of an instruction in memory.
21 HEX_0, HEX_1, HEX_2, HEX_3, HEX_4, HEX_5, HEX_6, HEX_7,
22 HEX_8, HEX_9, HEX_A, HEX_B, HEX_C, HEX_D, HEX_E, HEX_F,
23 REG_N, REG_M, REG_NM, REG_B,
26 IMM_4, IMM_4BY2, IMM_4BY4, PCRELIMM_8BY2, PCRELIMM_8BY4,
27 IMM_8, IMM_8BY2, IMM_8BY4,
31 A_END, A_BDISP12, A_BDISP8,
33 A_DISP_GBR, A_DISP_PC, A_DISP_REG_M, A_DISP_REG_N,
37 A_IND_M, A_IND_N, A_IND_R0_REG_M, A_IND_R0_REG_N,
39 A_PR, A_R0, A_R0_GBR, A_REG_M, A_REG_N, A_REG_B,
40 A_SR, A_VBR, A_SSR, A_SPC, A_SGR, A_DBR,
41 F_REG_N, F_REG_M, D_REG_N, D_REG_M,
42 X_REG_N, /* Only used for argument parsing */
43 X_REG_M, /* Only used for argument parsing */
44 DX_REG_N, DX_REG_M, V_REG_N, V_REG_M,
48 FPUL_N, FPUL_M, FPSCR_N, FPSCR_M,
51 static struct sh_opcode_info {
54 sh_nibble_type nibbles[4];
56 {"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM_8}},
57 {"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}},
58 {"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}},
59 {"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}},
60 {"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM_8}},
61 {"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}},
62 {"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM_8}},
63 {"bra",{A_BDISP12},{HEX_A,BRANCH_12}},
64 {"bsr",{A_BDISP12},{HEX_B,BRANCH_12}},
65 {"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}},
66 {"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}},
67 {"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}},
68 {"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}},
69 {"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}},
70 {"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}},
71 {"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}},
72 {"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}},
73 {"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}},
74 {"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM_8}},
75 {"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}},
76 {"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}},
77 {"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}},
78 {"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}},
79 {"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}},
80 {"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}},
81 {"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}},
82 {"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}},
83 {"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}},
84 {"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}},
85 {"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}},
86 {"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}},
87 {"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}},
88 {"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}},
89 {"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}},
90 {"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}},
91 {"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}},
92 {"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}},
93 {"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}},
94 {"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}},
95 {"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}},
96 {"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}},
97 {"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_7,HEX_E}},
98 {"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}},
99 {"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}},
100 {"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}},
101 {"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}},
102 {"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}},
103 {"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}},
104 {"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_7,HEX_7}},
105 {"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}},
106 {"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}},
107 {"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}},
108 {"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}},
109 {"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}},
110 {"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}},
111 {"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}},
112 {"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}},
113 {"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}},
114 {"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}},
115 {"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}},
116 {"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}},
117 {"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}},
118 {"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM_8}},
119 {"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}},
120 {"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}},
121 {"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}},
122 {"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}},
123 {"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM_4}},
124 {"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM_8}},
125 {"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}},
126 {"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}},
127 {"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}},
128 {"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM_4}},
129 {"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM_8}},
130 {"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM_4BY4}},
131 {"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}},
132 {"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}},
133 {"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}},
134 {"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM_4BY4}},
135 {"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM_8BY4}},
136 {"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}},
137 {"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}},
138 {"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}},
139 {"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}},
140 {"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM_8BY4}},
141 {"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}},
142 {"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}},
143 {"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}},
144 {"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM_4BY2}},
145 {"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM_8BY2}},
146 {"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}},
147 {"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}},
148 {"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}},
149 {"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}},
150 {"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM_4BY2}},
151 {"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM_8BY2}},
152 {"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}},
153 {"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}},
154 {"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}},
155 {"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}},
156 {"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}},
157 {"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}},
158 {"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}},
159 {"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}},
160 {"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}},
161 {"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}},
162 {"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}},
163 {"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}},
164 {"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}},
165 {"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM_8}},
166 {"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}},
167 {"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM_8}},
168 {"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}},
169 {"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}},
170 {"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}},
171 {"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}},
172 {"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}},
173 {"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}},
174 {"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}},
175 {"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}},
176 {"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}},
177 {"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}},
178 {"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}},
179 {"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}},
180 {"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}},
181 {"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}},
182 {"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}},
183 {"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}},
184 {"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}},
185 {"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}},
186 {"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}},
187 {"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}},
188 {"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}},
189 {"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}},
190 {"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}},
191 {"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}},
192 {"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}},
193 {"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}},
194 {"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}},
195 {"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_2}},
196 {"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_7,HEX_2}},
197 {"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}},
198 {"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}},
199 {"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}},
200 {"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}},
201 {"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}},
202 {"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}},
203 {"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_3}},
204 {"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_3}},
205 {"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}},
206 {"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}},
207 {"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}},
208 {"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}},
209 {"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}},
210 {"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}},
211 {"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}},
212 {"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}},
213 {"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}},
214 {"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}},
215 {"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}},
216 {"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}},
217 {"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}},
218 {"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}},
219 {"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}},
220 {"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}},
221 {"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}},
222 {"trapa",{A_IMM},{HEX_C,HEX_3,IMM_8}},
223 {"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM_8}},
224 {"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}},
225 {"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM_8}},
226 {"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM_8}},
227 {"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}},
228 {"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM_8}},
229 {"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}},
230 {"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}},
231 {"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}},
232 {"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}},
233 {"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}},
234 {"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}},
235 {"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}},
236 {"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}},
237 {"fabs",{FD_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}},
238 {"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}},
239 {"fadd",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_0}},
240 {"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}},
241 {"fcmp/eq",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_4}},
242 {"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}},
243 {"fcmp/gt",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_5}},
244 {"fcnvds",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_B,HEX_D}},
245 {"fcnvsd",{FPUL_M,D_REG_N},{HEX_F,REG_N,HEX_A,HEX_D}},
246 {"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}},
247 {"fdiv",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_3}},
248 {"fipr",{V_REG_M,V_REG_N},{HEX_F,REG_NM,HEX_E,HEX_D}},
249 {"fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,HEX_D}},
250 {"fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,HEX_D}},
251 {"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}},
252 {"float",{FPUL_M,FD_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}},
253 {"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}},
254 {"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}},
255 {"fmov",{DX_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_C}},
256 {"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}},
257 {"fmov",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}},
258 {"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}},
259 {"fmov",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}},
260 {"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}},
261 {"fmov",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}},
262 {"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}},
263 {"fmov",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}},
264 {"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}},
265 {"fmov",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}},
266 {"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}},
267 {"fmov",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}},
268 {"fmov.d",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}},
269 {"fmov.d",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}},
270 {"fmov.d",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}},
271 {"fmov.d",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}},
272 {"fmov.d",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}},
273 {"fmov.d",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}},
274 {"fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}},
275 {"fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}},
276 {"fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}},
277 {"fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}},
278 {"fmov.s",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}},
279 {"fmov.s",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}},
280 {"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}},
281 {"fmul",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_2}},
282 {"fneg",{FD_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}},
283 {"frchg",{0},{HEX_F,HEX_B,HEX_F,HEX_D}},
284 {"fschg",{0},{HEX_F,HEX_3,HEX_F,HEX_D}},
285 {"fsqrt",{FD_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}},
286 {"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}},
287 {"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}},
288 {"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}},
289 {"ftrc",{FD_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}},
290 {"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_NM,HEX_F,HEX_D}},
294 static void print_sh_insn(u32 memaddr, u16 insn)
297 int nibs[4] = { (insn >> 12) & 0xf, (insn >> 8) & 0xf, (insn >> 4) & 0xf, insn & 0xf};
299 struct sh_opcode_info *op = sh_table;
301 for (; op->name; op++) {
308 int disp_pc_addr = 0;
310 for (n = 0; n < 4; n++) {
311 int i = op->nibbles[n];
320 imm = (nibs[2] << 4) | (nibs[3]);
323 imm = ((char)imm) * 2 + 4 ;
326 imm = ((nibs[1]) << 8) | (nibs[2] << 4) | (nibs[3]);
341 imm = (nibs[2] << 4) | nibs[3];
344 imm = ((nibs[2] << 4) | nibs[3]) <<1;
348 imm = ((nibs[2] << 4) | nibs[3]) <<2;
352 imm = ((nibs[2] << 4) | nibs[3]) <<1;
355 imm = ((nibs[2] << 4) | nibs[3]) <<2;
358 imm = (nibs[2] << 4) | (nibs[3]);
370 rn = (nibs[n] & 0xc) >> 2;
371 rm = (nibs[n] & 0x3);
382 printk("%-8s ", op->name);
383 lastsp = (op->arg[0] == A_END);
385 for (n = 0; n < 6 && op->arg[n] != A_END; n++) {
386 if (n && op->arg[1] != A_END)
388 switch (op->arg[n]) {
390 printk("#%d", (char)(imm));
408 printk("@(%d,r%d)", imm, rn);
423 printk("@(%d,r%d)", imm, rm);
426 printk("r%d_bank", rb);
430 disp_pc_addr = imm + 4 + (memaddr & relmask);
431 printk("%08x <%pS>", disp_pc_addr,
432 (void *)disp_pc_addr);
435 printk("@(r0,r%d)", rn);
438 printk("@(r0,r%d)", rm);
441 printk("@(%d,gbr)",imm);
448 printk("%08x", imm + memaddr);
491 printk("xd%d", rn & ~1);
500 printk("xd%d", rm & ~1);
518 printk("fv%d", rn*4);
521 printk("fv%d", rm*4);
531 if (disp_pc && strcmp(op->name, "mova") != 0) {
535 __get_user(val, (u16 *)disp_pc_addr);
537 __get_user(val, (u32 *)disp_pc_addr);
539 printk(" ! %08x <%pS>", val, (void *)val);
548 printk(".word 0x%x%x%x%x", nibs[0], nibs[1], nibs[2], nibs[3]);
551 void show_code(struct pt_regs *regs)
553 unsigned short *pc = (unsigned short *)regs->pc;
561 for (i = -3 ; i < 6 ; i++) {
564 if (__get_user(insn, pc + i)) {
565 printk(" (Bad address in pc)\n");
569 printk("%s%08lx: ", (i ? " ": "->"), (unsigned long)(pc + i));
570 print_sh_insn((unsigned long)(pc + i), insn);