4 * Copyright (C) 2007 Paul Mundt
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
10 #include <linux/platform_device.h>
11 #include <linux/init.h>
12 #include <linux/serial.h>
13 #include <linux/serial_sci.h>
16 #include <linux/sh_dma.h>
17 #include <linux/sh_timer.h>
18 #include <linux/sh_intc.h>
19 #include <asm/mmzone.h>
20 #include <cpu/dma-register.h>
22 static struct plat_sci_port scif0_platform_data = {
23 .scscr = SCSCR_REIE | SCSCR_CKE1,
25 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
28 static struct resource scif0_resources[] = {
29 DEFINE_RES_MEM(0xffea0000, 0x100),
30 DEFINE_RES_IRQ(evt2irq(0x700)),
33 static struct platform_device scif0_device = {
36 .resource = scif0_resources,
37 .num_resources = ARRAY_SIZE(scif0_resources),
39 .platform_data = &scif0_platform_data,
43 static struct plat_sci_port scif1_platform_data = {
44 .scscr = SCSCR_REIE | SCSCR_CKE1,
46 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
49 static struct resource scif1_resources[] = {
50 DEFINE_RES_MEM(0xffeb0000, 0x100),
51 DEFINE_RES_IRQ(evt2irq(0x780)),
54 static struct platform_device scif1_device = {
57 .resource = scif1_resources,
58 .num_resources = ARRAY_SIZE(scif1_resources),
60 .platform_data = &scif1_platform_data,
64 static struct plat_sci_port scif2_platform_data = {
65 .scscr = SCSCR_REIE | SCSCR_CKE1,
67 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
70 static struct resource scif2_resources[] = {
71 DEFINE_RES_MEM(0xffec0000, 0x100),
72 DEFINE_RES_IRQ(evt2irq(0x980)),
75 static struct platform_device scif2_device = {
78 .resource = scif2_resources,
79 .num_resources = ARRAY_SIZE(scif2_resources),
81 .platform_data = &scif2_platform_data,
85 static struct plat_sci_port scif3_platform_data = {
86 .scscr = SCSCR_REIE | SCSCR_CKE1,
88 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
91 static struct resource scif3_resources[] = {
92 DEFINE_RES_MEM(0xffed0000, 0x100),
93 DEFINE_RES_IRQ(evt2irq(0x9a0)),
96 static struct platform_device scif3_device = {
99 .resource = scif3_resources,
100 .num_resources = ARRAY_SIZE(scif3_resources),
102 .platform_data = &scif3_platform_data,
106 static struct plat_sci_port scif4_platform_data = {
107 .scscr = SCSCR_REIE | SCSCR_CKE1,
109 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
112 static struct resource scif4_resources[] = {
113 DEFINE_RES_MEM(0xffee0000, 0x100),
114 DEFINE_RES_IRQ(evt2irq(0x9c0)),
117 static struct platform_device scif4_device = {
120 .resource = scif4_resources,
121 .num_resources = ARRAY_SIZE(scif4_resources),
123 .platform_data = &scif4_platform_data,
127 static struct plat_sci_port scif5_platform_data = {
128 .scscr = SCSCR_REIE | SCSCR_CKE1,
130 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
133 static struct resource scif5_resources[] = {
134 DEFINE_RES_MEM(0xffef0000, 0x100),
135 DEFINE_RES_IRQ(evt2irq(0x9e0)),
138 static struct platform_device scif5_device = {
141 .resource = scif5_resources,
142 .num_resources = ARRAY_SIZE(scif5_resources),
144 .platform_data = &scif5_platform_data,
148 static struct sh_timer_config tmu0_platform_data = {
152 static struct resource tmu0_resources[] = {
153 DEFINE_RES_MEM(0xffd80000, 0x30),
154 DEFINE_RES_IRQ(evt2irq(0x580)),
155 DEFINE_RES_IRQ(evt2irq(0x5a0)),
156 DEFINE_RES_IRQ(evt2irq(0x5c0)),
159 static struct platform_device tmu0_device = {
163 .platform_data = &tmu0_platform_data,
165 .resource = tmu0_resources,
166 .num_resources = ARRAY_SIZE(tmu0_resources),
169 static struct sh_timer_config tmu1_platform_data = {
173 static struct resource tmu1_resources[] = {
174 DEFINE_RES_MEM(0xffdc0000, 0x2c),
175 DEFINE_RES_IRQ(evt2irq(0xe00)),
176 DEFINE_RES_IRQ(evt2irq(0xe20)),
177 DEFINE_RES_IRQ(evt2irq(0xe40)),
180 static struct platform_device tmu1_device = {
184 .platform_data = &tmu1_platform_data,
186 .resource = tmu1_resources,
187 .num_resources = ARRAY_SIZE(tmu1_resources),
191 static const struct sh_dmae_channel sh7785_dmae0_channels[] = {
219 static const struct sh_dmae_channel sh7785_dmae1_channels[] = {
235 static const unsigned int ts_shift[] = TS_SHIFT;
237 static struct sh_dmae_pdata dma0_platform_data = {
238 .channel = sh7785_dmae0_channels,
239 .channel_num = ARRAY_SIZE(sh7785_dmae0_channels),
240 .ts_low_shift = CHCR_TS_LOW_SHIFT,
241 .ts_low_mask = CHCR_TS_LOW_MASK,
242 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
243 .ts_high_mask = CHCR_TS_HIGH_MASK,
244 .ts_shift = ts_shift,
245 .ts_shift_num = ARRAY_SIZE(ts_shift),
246 .dmaor_init = DMAOR_INIT,
249 static struct sh_dmae_pdata dma1_platform_data = {
250 .channel = sh7785_dmae1_channels,
251 .channel_num = ARRAY_SIZE(sh7785_dmae1_channels),
252 .ts_low_shift = CHCR_TS_LOW_SHIFT,
253 .ts_low_mask = CHCR_TS_LOW_MASK,
254 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
255 .ts_high_mask = CHCR_TS_HIGH_MASK,
256 .ts_shift = ts_shift,
257 .ts_shift_num = ARRAY_SIZE(ts_shift),
258 .dmaor_init = DMAOR_INIT,
261 static struct resource sh7785_dmae0_resources[] = {
263 /* Channel registers and DMAOR */
266 .flags = IORESOURCE_MEM,
272 .flags = IORESOURCE_MEM,
276 * Real DMA error vector is 0x6e0, and channel
277 * vectors are 0x620-0x6c0
280 .start = evt2irq(0x620),
281 .end = evt2irq(0x620),
282 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
286 static struct resource sh7785_dmae1_resources[] = {
288 /* Channel registers and DMAOR */
291 .flags = IORESOURCE_MEM,
293 /* DMAC1 has no DMARS */
296 * Real DMA error vector is 0x940, and channel
297 * vectors are 0x880-0x920
300 .start = evt2irq(0x880),
301 .end = evt2irq(0x880),
302 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
306 static struct platform_device dma0_device = {
307 .name = "sh-dma-engine",
309 .resource = sh7785_dmae0_resources,
310 .num_resources = ARRAY_SIZE(sh7785_dmae0_resources),
312 .platform_data = &dma0_platform_data,
316 static struct platform_device dma1_device = {
317 .name = "sh-dma-engine",
319 .resource = sh7785_dmae1_resources,
320 .num_resources = ARRAY_SIZE(sh7785_dmae1_resources),
322 .platform_data = &dma1_platform_data,
326 static struct platform_device *sh7785_devices[] __initdata = {
339 static int __init sh7785_devices_setup(void)
341 return platform_add_devices(sh7785_devices,
342 ARRAY_SIZE(sh7785_devices));
344 arch_initcall(sh7785_devices_setup);
346 static struct platform_device *sh7785_early_devices[] __initdata = {
357 void __init plat_early_device_setup(void)
359 early_platform_add_devices(sh7785_early_devices,
360 ARRAY_SIZE(sh7785_early_devices));
366 /* interrupt sources */
368 IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
369 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
370 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
371 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
373 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
374 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
375 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
376 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
378 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
379 WDT, TMU0, TMU1, TMU2, TMU2_TICPI,
380 HUDI, DMAC0, SCIF0, SCIF1, DMAC1, HSPI,
381 SCIF2, SCIF3, SCIF4, SCIF5,
382 PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD, PCIC5,
383 SIOF, MMCIF, DU, GDTA,
389 /* interrupt groups */
394 static struct intc_vect vectors[] __initdata = {
395 INTC_VECT(WDT, 0x560),
396 INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
397 INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
398 INTC_VECT(HUDI, 0x600),
399 INTC_VECT(DMAC0, 0x620), INTC_VECT(DMAC0, 0x640),
400 INTC_VECT(DMAC0, 0x660), INTC_VECT(DMAC0, 0x680),
401 INTC_VECT(DMAC0, 0x6a0), INTC_VECT(DMAC0, 0x6c0),
402 INTC_VECT(DMAC0, 0x6e0),
403 INTC_VECT(SCIF0, 0x700), INTC_VECT(SCIF0, 0x720),
404 INTC_VECT(SCIF0, 0x740), INTC_VECT(SCIF0, 0x760),
405 INTC_VECT(SCIF1, 0x780), INTC_VECT(SCIF1, 0x7a0),
406 INTC_VECT(SCIF1, 0x7c0), INTC_VECT(SCIF1, 0x7e0),
407 INTC_VECT(DMAC1, 0x880), INTC_VECT(DMAC1, 0x8a0),
408 INTC_VECT(DMAC1, 0x8c0), INTC_VECT(DMAC1, 0x8e0),
409 INTC_VECT(DMAC1, 0x900), INTC_VECT(DMAC1, 0x920),
410 INTC_VECT(DMAC1, 0x940),
411 INTC_VECT(HSPI, 0x960),
412 INTC_VECT(SCIF2, 0x980), INTC_VECT(SCIF3, 0x9a0),
413 INTC_VECT(SCIF4, 0x9c0), INTC_VECT(SCIF5, 0x9e0),
414 INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20),
415 INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60),
416 INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIC5, 0xaa0),
417 INTC_VECT(PCIC5, 0xac0), INTC_VECT(PCIC5, 0xae0),
418 INTC_VECT(PCIC5, 0xb00), INTC_VECT(PCIC5, 0xb20),
419 INTC_VECT(SIOF, 0xc00),
420 INTC_VECT(MMCIF, 0xd00), INTC_VECT(MMCIF, 0xd20),
421 INTC_VECT(MMCIF, 0xd40), INTC_VECT(MMCIF, 0xd60),
422 INTC_VECT(DU, 0xd80),
423 INTC_VECT(GDTA, 0xda0), INTC_VECT(GDTA, 0xdc0),
424 INTC_VECT(GDTA, 0xde0),
425 INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
426 INTC_VECT(TMU5, 0xe40),
427 INTC_VECT(SSI0, 0xe80), INTC_VECT(SSI1, 0xea0),
428 INTC_VECT(HAC0, 0xec0), INTC_VECT(HAC1, 0xee0),
429 INTC_VECT(FLCTL, 0xf00), INTC_VECT(FLCTL, 0xf20),
430 INTC_VECT(FLCTL, 0xf40), INTC_VECT(FLCTL, 0xf60),
431 INTC_VECT(GPIO, 0xf80), INTC_VECT(GPIO, 0xfa0),
432 INTC_VECT(GPIO, 0xfc0), INTC_VECT(GPIO, 0xfe0),
435 static struct intc_group groups[] __initdata = {
436 INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
437 INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
440 static struct intc_mask_reg mask_registers[] __initdata = {
441 { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
442 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
444 { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
445 { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
446 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
447 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
448 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
449 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
450 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
451 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
452 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
454 { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
455 { 0, 0, 0, GDTA, DU, SSI0, SSI1, GPIO,
456 FLCTL, MMCIF, HSPI, SIOF, PCIC5, PCIINTD, PCIINTC, PCIINTB,
457 PCIINTA, PCISERR, HAC1, HAC0, DMAC1, DMAC0, HUDI, WDT,
458 SCIF5, SCIF4, SCIF3, SCIF2, SCIF1, SCIF0, TMU345, TMU012 } },
461 static struct intc_prio_reg prio_registers[] __initdata = {
462 { 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
463 IRQ4, IRQ5, IRQ6, IRQ7 } },
464 { 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1,
465 TMU2, TMU2_TICPI } },
466 { 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, } },
467 { 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1,
469 { 0xffd4000c, 0, 32, 8, /* INT2PRI3 */ { SCIF4, SCIF5, WDT, } },
470 { 0xffd40010, 0, 32, 8, /* INT2PRI4 */ { HUDI, DMAC0, DMAC1, } },
471 { 0xffd40014, 0, 32, 8, /* INT2PRI5 */ { HAC0, HAC1,
472 PCISERR, PCIINTA } },
473 { 0xffd40018, 0, 32, 8, /* INT2PRI6 */ { PCIINTB, PCIINTC,
475 { 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { SIOF, HSPI, MMCIF, } },
476 { 0xffd40020, 0, 32, 8, /* INT2PRI8 */ { FLCTL, GPIO, SSI0, SSI1, } },
477 { 0xffd40024, 0, 32, 8, /* INT2PRI9 */ { DU, GDTA, } },
480 static DECLARE_INTC_DESC(intc_desc, "sh7785", vectors, groups,
481 mask_registers, prio_registers, NULL);
483 /* Support for external interrupt pins in IRQ mode */
485 static struct intc_vect vectors_irq0123[] __initdata = {
486 INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
487 INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
490 static struct intc_vect vectors_irq4567[] __initdata = {
491 INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
492 INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
495 static struct intc_sense_reg sense_registers[] __initdata = {
496 { 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3,
497 IRQ4, IRQ5, IRQ6, IRQ7 } },
500 static struct intc_mask_reg ack_registers[] __initdata = {
501 { 0xffd00024, 0, 32, /* INTREQ */
502 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
505 static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7785-irq0123",
506 vectors_irq0123, NULL, mask_registers,
507 prio_registers, sense_registers, ack_registers);
509 static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7785-irq4567",
510 vectors_irq4567, NULL, mask_registers,
511 prio_registers, sense_registers, ack_registers);
513 /* External interrupt pins in IRL mode */
515 static struct intc_vect vectors_irl0123[] __initdata = {
516 INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
517 INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
518 INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
519 INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
520 INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
521 INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
522 INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
523 INTC_VECT(IRL0_HHHL, 0x3c0),
526 static struct intc_vect vectors_irl4567[] __initdata = {
527 INTC_VECT(IRL4_LLLL, 0xb00), INTC_VECT(IRL4_LLLH, 0xb20),
528 INTC_VECT(IRL4_LLHL, 0xb40), INTC_VECT(IRL4_LLHH, 0xb60),
529 INTC_VECT(IRL4_LHLL, 0xb80), INTC_VECT(IRL4_LHLH, 0xba0),
530 INTC_VECT(IRL4_LHHL, 0xbc0), INTC_VECT(IRL4_LHHH, 0xbe0),
531 INTC_VECT(IRL4_HLLL, 0xc00), INTC_VECT(IRL4_HLLH, 0xc20),
532 INTC_VECT(IRL4_HLHL, 0xc40), INTC_VECT(IRL4_HLHH, 0xc60),
533 INTC_VECT(IRL4_HHLL, 0xc80), INTC_VECT(IRL4_HHLH, 0xca0),
534 INTC_VECT(IRL4_HHHL, 0xcc0),
537 static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7785-irl0123", vectors_irl0123,
538 NULL, mask_registers, NULL, NULL);
540 static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7785-irl4567", vectors_irl4567,
541 NULL, mask_registers, NULL, NULL);
543 #define INTC_ICR0 0xffd00000
544 #define INTC_INTMSK0 0xffd00044
545 #define INTC_INTMSK1 0xffd00048
546 #define INTC_INTMSK2 0xffd40080
547 #define INTC_INTMSKCLR1 0xffd00068
548 #define INTC_INTMSKCLR2 0xffd40084
550 void __init plat_irq_setup(void)
552 /* disable IRQ3-0 + IRQ7-4 */
553 __raw_writel(0xff000000, INTC_INTMSK0);
555 /* disable IRL3-0 + IRL7-4 */
556 __raw_writel(0xc0000000, INTC_INTMSK1);
557 __raw_writel(0xfffefffe, INTC_INTMSK2);
559 /* select IRL mode for IRL3-0 + IRL7-4 */
560 __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
562 /* disable holding function, ie enable "SH-4 Mode" */
563 __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
565 register_intc_controller(&intc_desc);
568 void __init plat_irq_setup_pins(int mode)
571 case IRQ_MODE_IRQ7654:
572 /* select IRQ mode for IRL7-4 */
573 __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0);
574 register_intc_controller(&intc_desc_irq4567);
576 case IRQ_MODE_IRQ3210:
577 /* select IRQ mode for IRL3-0 */
578 __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
579 register_intc_controller(&intc_desc_irq0123);
581 case IRQ_MODE_IRL7654:
582 /* enable IRL7-4 but don't provide any masking */
583 __raw_writel(0x40000000, INTC_INTMSKCLR1);
584 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
586 case IRQ_MODE_IRL3210:
587 /* enable IRL0-3 but don't provide any masking */
588 __raw_writel(0x80000000, INTC_INTMSKCLR1);
589 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
591 case IRQ_MODE_IRL7654_MASK:
592 /* enable IRL7-4 and mask using cpu intc controller */
593 __raw_writel(0x40000000, INTC_INTMSKCLR1);
594 register_intc_controller(&intc_desc_irl4567);
596 case IRQ_MODE_IRL3210_MASK:
597 /* enable IRL0-3 and mask using cpu intc controller */
598 __raw_writel(0x80000000, INTC_INTMSKCLR1);
599 register_intc_controller(&intc_desc_irl0123);
606 void __init plat_mem_setup(void)
608 /* Register the URAM space as Node 1 */
609 setup_bootmem_node(1, 0xe55f0000, 0xe5610000);