arch/sh/kernel/cpu/sh4a/setup-sh7770.c

   1 /*
   2  * SH7770 Setup
   3  *
   4  *  Copyright (C) 2006 - 2008  Paul Mundt
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License.  See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  */
  10 #include <linux/platform_device.h>
  11 #include <linux/init.h>
  12 #include <linux/serial.h>
  13 #include <linux/serial_sci.h>
  14 #include <linux/sh_timer.h>
  15 #include <linux/sh_intc.h>
  16 #include <linux/io.h>
  17
  18 static struct plat_sci_port scif0_platform_data = {
  19         .scscr          = SCSCR_REIE | SCSCR_TOIE,
  20         .type           = PORT_SCIF,
  21 };
  22
  23 static struct resource scif0_resources[] = {
  24         DEFINE_RES_MEM(0xff923000, 0x100),
  25         DEFINE_RES_IRQ(evt2irq(0x9a0)),
  26 };
  27
  28 static struct platform_device scif0_device = {
  29         .name           = "sh-sci",
  30         .id             = 0,
  31         .resource       = scif0_resources,
  32         .num_resources  = ARRAY_SIZE(scif0_resources),
  33         .dev            = {
  34                 .platform_data  = &scif0_platform_data,
  35         },
  36 };
  37
  38 static struct plat_sci_port scif1_platform_data = {
  39         .scscr          = SCSCR_REIE | SCSCR_TOIE,
  40         .type           = PORT_SCIF,
  41 };
  42
  43 static struct resource scif1_resources[] = {
  44         DEFINE_RES_MEM(0xff924000, 0x100),
  45         DEFINE_RES_IRQ(evt2irq(0x9c0)),
  46 };
  47
  48 static struct platform_device scif1_device = {
  49         .name           = "sh-sci",
  50         .id             = 1,
  51         .resource       = scif1_resources,
  52         .num_resources  = ARRAY_SIZE(scif1_resources),
  53         .dev            = {
  54                 .platform_data  = &scif1_platform_data,
  55         },
  56 };
  57
  58 static struct plat_sci_port scif2_platform_data = {
  59         .scscr          = SCSCR_REIE | SCSCR_TOIE,
  60         .type           = PORT_SCIF,
  61 };
  62
  63 static struct resource scif2_resources[] = {
  64         DEFINE_RES_MEM(0xff925000, 0x100),
  65         DEFINE_RES_IRQ(evt2irq(0x9e0)),
  66 };
  67
  68 static struct platform_device scif2_device = {
  69         .name           = "sh-sci",
  70         .id             = 2,
  71         .resource       = scif2_resources,
  72         .num_resources  = ARRAY_SIZE(scif2_resources),
  73         .dev            = {
  74                 .platform_data  = &scif2_platform_data,
  75         },
  76 };
  77
  78 static struct plat_sci_port scif3_platform_data = {
  79         .scscr          = SCSCR_REIE | SCSCR_TOIE,
  80         .type           = PORT_SCIF,
  81 };
  82
  83 static struct resource scif3_resources[] = {
  84         DEFINE_RES_MEM(0xff926000, 0x100),
  85         DEFINE_RES_IRQ(evt2irq(0xa00)),
  86 };
  87
  88 static struct platform_device scif3_device = {
  89         .name           = "sh-sci",
  90         .id             = 3,
  91         .resource       = scif3_resources,
  92         .num_resources  = ARRAY_SIZE(scif3_resources),
  93         .dev            = {
  94                 .platform_data  = &scif3_platform_data,
  95         },
  96 };
  97
  98 static struct plat_sci_port scif4_platform_data = {
  99         .scscr          = SCSCR_REIE | SCSCR_TOIE,
 100         .type           = PORT_SCIF,
 101 };
 102
 103 static struct resource scif4_resources[] = {
 104         DEFINE_RES_MEM(0xff927000, 0x100),
 105         DEFINE_RES_IRQ(evt2irq(0xa20)),
 106 };
 107
 108 static struct platform_device scif4_device = {
 109         .name           = "sh-sci",
 110         .id             = 4,
 111         .resource       = scif4_resources,
 112         .num_resources  = ARRAY_SIZE(scif4_resources),
 113         .dev            = {
 114                 .platform_data  = &scif4_platform_data,
 115         },
 116 };
 117
 118 static struct plat_sci_port scif5_platform_data = {
 119         .scscr          = SCSCR_REIE | SCSCR_TOIE,
 120         .type           = PORT_SCIF,
 121 };
 122
 123 static struct resource scif5_resources[] = {
 124         DEFINE_RES_MEM(0xff928000, 0x100),
 125         DEFINE_RES_IRQ(evt2irq(0xa40)),
 126 };
 127
 128 static struct platform_device scif5_device = {
 129         .name           = "sh-sci",
 130         .id             = 5,
 131         .resource       = scif5_resources,
 132         .num_resources  = ARRAY_SIZE(scif5_resources),
 133         .dev            = {
 134                 .platform_data  = &scif5_platform_data,
 135         },
 136 };
 137
 138 static struct plat_sci_port scif6_platform_data = {
 139         .scscr          = SCSCR_REIE | SCSCR_TOIE,
 140         .type           = PORT_SCIF,
 141 };
 142
 143 static struct resource scif6_resources[] = {
 144         DEFINE_RES_MEM(0xff929000, 0x100),
 145         DEFINE_RES_IRQ(evt2irq(0xa60)),
 146 };
 147
 148 static struct platform_device scif6_device = {
 149         .name           = "sh-sci",
 150         .id             = 6,
 151         .resource       = scif6_resources,
 152         .num_resources  = ARRAY_SIZE(scif6_resources),
 153         .dev            = {
 154                 .platform_data  = &scif6_platform_data,
 155         },
 156 };
 157
 158 static struct plat_sci_port scif7_platform_data = {
 159         .scscr          = SCSCR_REIE | SCSCR_TOIE,
 160         .type           = PORT_SCIF,
 161 };
 162
 163 static struct resource scif7_resources[] = {
 164         DEFINE_RES_MEM(0xff92a000, 0x100),
 165         DEFINE_RES_IRQ(evt2irq(0xa80)),
 166 };
 167
 168 static struct platform_device scif7_device = {
 169         .name           = "sh-sci",
 170         .id             = 7,
 171         .resource       = scif7_resources,
 172         .num_resources  = ARRAY_SIZE(scif7_resources),
 173         .dev            = {
 174                 .platform_data  = &scif7_platform_data,
 175         },
 176 };
 177
 178 static struct plat_sci_port scif8_platform_data = {
 179         .scscr          = SCSCR_REIE | SCSCR_TOIE,
 180         .type           = PORT_SCIF,
 181 };
 182
 183 static struct resource scif8_resources[] = {
 184         DEFINE_RES_MEM(0xff92b000, 0x100),
 185         DEFINE_RES_IRQ(evt2irq(0xaa0)),
 186 };
 187
 188 static struct platform_device scif8_device = {
 189         .name           = "sh-sci",
 190         .id             = 8,
 191         .resource       = scif8_resources,
 192         .num_resources  = ARRAY_SIZE(scif8_resources),
 193         .dev            = {
 194                 .platform_data  = &scif8_platform_data,
 195         },
 196 };
 197
 198 static struct plat_sci_port scif9_platform_data = {
 199         .scscr          = SCSCR_REIE | SCSCR_TOIE,
 200         .type           = PORT_SCIF,
 201 };
 202
 203 static struct resource scif9_resources[] = {
 204         DEFINE_RES_MEM(0xff92c000, 0x100),
 205         DEFINE_RES_IRQ(evt2irq(0xac0)),
 206 };
 207
 208 static struct platform_device scif9_device = {
 209         .name           = "sh-sci",
 210         .id             = 9,
 211         .resource       = scif9_resources,
 212         .num_resources  = ARRAY_SIZE(scif9_resources),
 213         .dev            = {
 214                 .platform_data  = &scif9_platform_data,
 215         },
 216 };
 217
 218 static struct sh_timer_config tmu0_platform_data = {
 219         .channels_mask = 7,
 220 };
 221
 222 static struct resource tmu0_resources[] = {
 223         DEFINE_RES_MEM(0xffd80000, 0x30),
 224         DEFINE_RES_IRQ(evt2irq(0x400)),
 225         DEFINE_RES_IRQ(evt2irq(0x420)),
 226         DEFINE_RES_IRQ(evt2irq(0x440)),
 227 };
 228
 229 static struct platform_device tmu0_device = {
 230         .name           = "sh-tmu",
 231         .id             = 0,
 232         .dev = {
 233                 .platform_data  = &tmu0_platform_data,
 234         },
 235         .resource       = tmu0_resources,
 236         .num_resources  = ARRAY_SIZE(tmu0_resources),
 237 };
 238
 239 static struct sh_timer_config tmu1_platform_data = {
 240         .channels_mask = 7,
 241 };
 242
 243 static struct resource tmu1_resources[] = {
 244         DEFINE_RES_MEM(0xffd81000, 0x30),
 245         DEFINE_RES_IRQ(evt2irq(0x460)),
 246         DEFINE_RES_IRQ(evt2irq(0x480)),
 247         DEFINE_RES_IRQ(evt2irq(0x4a0)),
 248 };
 249
 250 static struct platform_device tmu1_device = {
 251         .name           = "sh-tmu",
 252         .id             = 1,
 253         .dev = {
 254                 .platform_data  = &tmu1_platform_data,
 255         },
 256         .resource       = tmu1_resources,
 257         .num_resources  = ARRAY_SIZE(tmu1_resources),
 258 };
 259
 260 static struct sh_timer_config tmu2_platform_data = {
 261         .channels_mask = 7,
 262 };
 263
 264 static struct resource tmu2_resources[] = {
 265         DEFINE_RES_MEM(0xffd82000, 0x2c),
 266         DEFINE_RES_IRQ(evt2irq(0x4c0)),
 267         DEFINE_RES_IRQ(evt2irq(0x4e0)),
 268         DEFINE_RES_IRQ(evt2irq(0x500)),
 269 };
 270
 271 static struct platform_device tmu2_device = {
 272         .name           = "sh-tmu",
 273         .id             = 2,
 274         .dev = {
 275                 .platform_data  = &tmu2_platform_data,
 276         },
 277         .resource       = tmu2_resources,
 278         .num_resources  = ARRAY_SIZE(tmu2_resources),
 279 };
 280
 281 static struct platform_device *sh7770_devices[] __initdata = {
 282         &scif0_device,
 283         &scif1_device,
 284         &scif2_device,
 285         &scif3_device,
 286         &scif4_device,
 287         &scif5_device,
 288         &scif6_device,
 289         &scif7_device,
 290         &scif8_device,
 291         &scif9_device,
 292         &tmu0_device,
 293         &tmu1_device,
 294         &tmu2_device,
 295 };
 296
 297 static int __init sh7770_devices_setup(void)
 298 {
 299         return platform_add_devices(sh7770_devices,
 300                                     ARRAY_SIZE(sh7770_devices));
 301 }
 302 arch_initcall(sh7770_devices_setup);
 303
 304 static struct platform_device *sh7770_early_devices[] __initdata = {
 305         &scif0_device,
 306         &scif1_device,
 307         &scif2_device,
 308         &scif3_device,
 309         &scif4_device,
 310         &scif5_device,
 311         &scif6_device,
 312         &scif7_device,
 313         &scif8_device,
 314         &scif9_device,
 315         &tmu0_device,
 316         &tmu1_device,
 317         &tmu2_device,
 318 };
 319
 320 void __init plat_early_device_setup(void)
 321 {
 322         early_platform_add_devices(sh7770_early_devices,
 323                                    ARRAY_SIZE(sh7770_early_devices));
 324 }
 325
 326 enum {
 327         UNUSED = 0,
 328
 329         /* interrupt sources */
 330         IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
 331         IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
 332         IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
 333         IRL_HHLL, IRL_HHLH, IRL_HHHL,
 334
 335         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5,
 336
 337         GPIO,
 338         TMU0, TMU1, TMU2, TMU2_TICPI,
 339         TMU3, TMU4, TMU5, TMU5_TICPI,
 340         TMU6, TMU7, TMU8,
 341         HAC, IPI, SPDIF, HUDI, I2C,
 342         DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2,
 343         I2S0, I2S1, I2S2, I2S3,
 344         SRC_RX, SRC_TX, SRC_SPDIF,
 345         DU, VIDEO_IN, REMOTE, YUV, USB, ATAPI, CAN, GPS, GFX2D,
 346         GFX3D_MBX, GFX3D_DMAC,
 347         EXBUS_ATA,
 348         SPI0, SPI1,
 349         SCIF089, SCIF1234, SCIF567,
 350         ADC,
 351         BBDMAC_0_3, BBDMAC_4_7, BBDMAC_8_10, BBDMAC_11_14,
 352         BBDMAC_15_18, BBDMAC_19_22, BBDMAC_23_26, BBDMAC_27,
 353         BBDMAC_28, BBDMAC_29, BBDMAC_30, BBDMAC_31,
 354
 355         /* interrupt groups */
 356         TMU, DMAC, I2S, SRC, GFX3D, SPI, SCIF, BBDMAC,
 357 };
 358
 359 static struct intc_vect vectors[] __initdata = {
 360         INTC_VECT(GPIO, 0x3e0),
 361         INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
 362         INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2_TICPI, 0x460),
 363         INTC_VECT(TMU3, 0x480), INTC_VECT(TMU4, 0x4a0),
 364         INTC_VECT(TMU5, 0x4c0), INTC_VECT(TMU5_TICPI, 0x4e0),
 365         INTC_VECT(TMU6, 0x500), INTC_VECT(TMU7, 0x520),
 366         INTC_VECT(TMU8, 0x540),
 367         INTC_VECT(HAC, 0x580), INTC_VECT(IPI, 0x5c0),
 368         INTC_VECT(SPDIF, 0x5e0),
 369         INTC_VECT(HUDI, 0x600), INTC_VECT(I2C, 0x620),
 370         INTC_VECT(DMAC0_DMINT0, 0x640), INTC_VECT(DMAC0_DMINT1, 0x660),
 371         INTC_VECT(DMAC0_DMINT2, 0x680),
 372         INTC_VECT(I2S0, 0x6a0), INTC_VECT(I2S1, 0x6c0),
 373         INTC_VECT(I2S2, 0x6e0), INTC_VECT(I2S3, 0x700),
 374         INTC_VECT(SRC_RX, 0x720), INTC_VECT(SRC_TX, 0x740),
 375         INTC_VECT(SRC_SPDIF, 0x760),
 376         INTC_VECT(DU, 0x780), INTC_VECT(VIDEO_IN, 0x7a0),
 377         INTC_VECT(REMOTE, 0x7c0), INTC_VECT(YUV, 0x7e0),
 378         INTC_VECT(USB, 0x840), INTC_VECT(ATAPI, 0x860),
 379         INTC_VECT(CAN, 0x880), INTC_VECT(GPS, 0x8a0),
 380         INTC_VECT(GFX2D, 0x8c0),
 381         INTC_VECT(GFX3D_MBX, 0x900), INTC_VECT(GFX3D_DMAC, 0x920),
 382         INTC_VECT(EXBUS_ATA, 0x940),
 383         INTC_VECT(SPI0, 0x960), INTC_VECT(SPI1, 0x980),
 384         INTC_VECT(SCIF089, 0x9a0), INTC_VECT(SCIF1234, 0x9c0),
 385         INTC_VECT(SCIF1234, 0x9e0), INTC_VECT(SCIF1234, 0xa00),
 386         INTC_VECT(SCIF1234, 0xa20), INTC_VECT(SCIF567, 0xa40),
 387         INTC_VECT(SCIF567, 0xa60), INTC_VECT(SCIF567, 0xa80),
 388         INTC_VECT(SCIF089, 0xaa0), INTC_VECT(SCIF089, 0xac0),
 389         INTC_VECT(ADC, 0xb20),
 390         INTC_VECT(BBDMAC_0_3, 0xba0), INTC_VECT(BBDMAC_0_3, 0xbc0),
 391         INTC_VECT(BBDMAC_0_3, 0xbe0), INTC_VECT(BBDMAC_0_3, 0xc00),
 392         INTC_VECT(BBDMAC_4_7, 0xc20), INTC_VECT(BBDMAC_4_7, 0xc40),
 393         INTC_VECT(BBDMAC_4_7, 0xc60), INTC_VECT(BBDMAC_4_7, 0xc80),
 394         INTC_VECT(BBDMAC_8_10, 0xca0), INTC_VECT(BBDMAC_8_10, 0xcc0),
 395         INTC_VECT(BBDMAC_8_10, 0xce0), INTC_VECT(BBDMAC_11_14, 0xd00),
 396         INTC_VECT(BBDMAC_11_14, 0xd20), INTC_VECT(BBDMAC_11_14, 0xd40),
 397         INTC_VECT(BBDMAC_11_14, 0xd60), INTC_VECT(BBDMAC_15_18, 0xd80),
 398         INTC_VECT(BBDMAC_15_18, 0xda0), INTC_VECT(BBDMAC_15_18, 0xdc0),
 399         INTC_VECT(BBDMAC_15_18, 0xde0), INTC_VECT(BBDMAC_19_22, 0xe00),
 400         INTC_VECT(BBDMAC_19_22, 0xe20), INTC_VECT(BBDMAC_19_22, 0xe40),
 401         INTC_VECT(BBDMAC_19_22, 0xe60), INTC_VECT(BBDMAC_23_26, 0xe80),
 402         INTC_VECT(BBDMAC_23_26, 0xea0), INTC_VECT(BBDMAC_23_26, 0xec0),
 403         INTC_VECT(BBDMAC_23_26, 0xee0), INTC_VECT(BBDMAC_27, 0xf00),
 404         INTC_VECT(BBDMAC_28, 0xf20), INTC_VECT(BBDMAC_29, 0xf40),
 405         INTC_VECT(BBDMAC_30, 0xf60), INTC_VECT(BBDMAC_31, 0xf80),
 406 };
 407
 408 static struct intc_group groups[] __initdata = {
 409         INTC_GROUP(TMU, TMU0, TMU1, TMU2, TMU2_TICPI, TMU3, TMU4, TMU5,
 410                    TMU5_TICPI, TMU6, TMU7, TMU8),
 411         INTC_GROUP(DMAC, DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2),
 412         INTC_GROUP(I2S, I2S0, I2S1, I2S2, I2S3),
 413         INTC_GROUP(SRC, SRC_RX, SRC_TX, SRC_SPDIF),
 414         INTC_GROUP(GFX3D, GFX3D_MBX, GFX3D_DMAC),
 415         INTC_GROUP(SPI, SPI0, SPI1),
 416         INTC_GROUP(SCIF, SCIF089, SCIF1234, SCIF567),
 417         INTC_GROUP(BBDMAC,
 418                    BBDMAC_0_3, BBDMAC_4_7, BBDMAC_8_10, BBDMAC_11_14,
 419                    BBDMAC_15_18, BBDMAC_19_22, BBDMAC_23_26, BBDMAC_27,
 420                    BBDMAC_28, BBDMAC_29, BBDMAC_30, BBDMAC_31),
 421 };
 422
 423 static struct intc_mask_reg mask_registers[] __initdata = {
 424         { 0xffe00040, 0xffe00044, 32, /* INT2MSKR / INT2MSKCR */
 425           { 0, BBDMAC, ADC, SCIF, SPI, EXBUS_ATA, GFX3D, GFX2D,
 426             GPS, CAN, ATAPI, USB, YUV, REMOTE, VIDEO_IN, DU, SRC, I2S,
 427             DMAC, I2C, HUDI, SPDIF, IPI, HAC, TMU, GPIO } },
 428 };
 429
 430 static struct intc_prio_reg prio_registers[] __initdata = {
 431         { 0xffe00000, 0, 32, 8, /* INT2PRI0 */ { GPIO, TMU0, 0, HAC } },
 432         { 0xffe00004, 0, 32, 8, /* INT2PRI1 */ { IPI, SPDIF, HUDI, I2C } },
 433         { 0xffe00008, 0, 32, 8, /* INT2PRI2 */ { DMAC, I2S, SRC, DU } },
 434         { 0xffe0000c, 0, 32, 8, /* INT2PRI3 */ { VIDEO_IN, REMOTE, YUV, USB } },
 435         { 0xffe00010, 0, 32, 8, /* INT2PRI4 */ { ATAPI, CAN, GPS, GFX2D } },
 436         { 0xffe00014, 0, 32, 8, /* INT2PRI5 */ { 0, GFX3D, EXBUS_ATA, SPI } },
 437         { 0xffe00018, 0, 32, 8, /* INT2PRI6 */ { SCIF1234, SCIF567, SCIF089 } },
 438         { 0xffe0001c, 0, 32, 8, /* INT2PRI7 */ { ADC, 0, 0, BBDMAC_0_3 } },
 439         { 0xffe00020, 0, 32, 8, /* INT2PRI8 */
 440           { BBDMAC_4_7, BBDMAC_8_10, BBDMAC_11_14, BBDMAC_15_18 } },
 441         { 0xffe00024, 0, 32, 8, /* INT2PRI9 */
 442           { BBDMAC_19_22, BBDMAC_23_26, BBDMAC_27, BBDMAC_28 } },
 443         { 0xffe00028, 0, 32, 8, /* INT2PRI10 */
 444           { BBDMAC_29, BBDMAC_30, BBDMAC_31 } },
 445         { 0xffe0002c, 0, 32, 8, /* INT2PRI11 */
 446           { TMU1, TMU2, TMU2_TICPI, TMU3 } },
 447         { 0xffe00030, 0, 32, 8, /* INT2PRI12 */
 448           { TMU4, TMU5, TMU5_TICPI, TMU6 } },
 449         { 0xffe00034, 0, 32, 8, /* INT2PRI13 */
 450           { TMU7, TMU8 } },
 451 };
 452
 453 static DECLARE_INTC_DESC(intc_desc, "sh7770", vectors, groups,
 454                          mask_registers, prio_registers, NULL);
 455
 456 /* Support for external interrupt pins in IRQ mode */
 457 static struct intc_vect irq_vectors[] __initdata = {
 458         INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
 459         INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
 460         INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
 461 };
 462
 463 static struct intc_mask_reg irq_mask_registers[] __initdata = {
 464         { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
 465           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, } },
 466 };
 467
 468 static struct intc_prio_reg irq_prio_registers[] __initdata = {
 469         { 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
 470                                                IRQ4, IRQ5, } },
 471 };
 472
 473 static struct intc_sense_reg irq_sense_registers[] __initdata = {
 474         { 0xffd0001c, 32, 2, /* ICR1 */   { IRQ0, IRQ1, IRQ2, IRQ3,
 475                                             IRQ4, IRQ5, } },
 476 };
 477
 478 static DECLARE_INTC_DESC(intc_irq_desc, "sh7770-irq", irq_vectors,
 479                          NULL, irq_mask_registers, irq_prio_registers,
 480                          irq_sense_registers);
 481
 482 /* External interrupt pins in IRL mode */
 483 static struct intc_vect irl_vectors[] __initdata = {
 484         INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220),
 485         INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260),
 486         INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0),
 487         INTC_VECT(IRL_LHHL, 0x2c0), INTC_VECT(IRL_LHHH, 0x2e0),
 488         INTC_VECT(IRL_HLLL, 0x300), INTC_VECT(IRL_HLLH, 0x320),
 489         INTC_VECT(IRL_HLHL, 0x340), INTC_VECT(IRL_HLHH, 0x360),
 490         INTC_VECT(IRL_HHLL, 0x380), INTC_VECT(IRL_HHLH, 0x3a0),
 491         INTC_VECT(IRL_HHHL, 0x3c0),
 492 };
 493
 494 static struct intc_mask_reg irl3210_mask_registers[] __initdata = {
 495         { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
 496           { IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
 497             IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
 498             IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
 499             IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
 500 };
 501
 502 static struct intc_mask_reg irl7654_mask_registers[] __initdata = {
 503         { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
 504           { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 505             IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
 506             IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
 507             IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
 508             IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
 509 };
 510
 511 static DECLARE_INTC_DESC(intc_irl7654_desc, "sh7780-irl7654", irl_vectors,
 512                          NULL, irl7654_mask_registers, NULL, NULL);
 513
 514 static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7780-irl3210", irl_vectors,
 515                          NULL, irl3210_mask_registers, NULL, NULL);
 516
 517 #define INTC_ICR0       0xffd00000
 518 #define INTC_INTMSK0    0xffd00044
 519 #define INTC_INTMSK1    0xffd00048
 520 #define INTC_INTMSK2    0xffd40080
 521 #define INTC_INTMSKCLR1 0xffd00068
 522 #define INTC_INTMSKCLR2 0xffd40084
 523
 524 void __init plat_irq_setup(void)
 525 {
 526         /* disable IRQ7-0 */
 527         __raw_writel(0xff000000, INTC_INTMSK0);
 528
 529         /* disable IRL3-0 + IRL7-4 */
 530         __raw_writel(0xc0000000, INTC_INTMSK1);
 531         __raw_writel(0xfffefffe, INTC_INTMSK2);
 532
 533         /* select IRL mode for IRL3-0 + IRL7-4 */
 534         __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
 535
 536         /* disable holding function, ie enable "SH-4 Mode" */
 537         __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
 538
 539         register_intc_controller(&intc_desc);
 540 }
 541
 542 void __init plat_irq_setup_pins(int mode)
 543 {
 544         switch (mode) {
 545         case IRQ_MODE_IRQ:
 546                 /* select IRQ mode for IRL3-0 + IRL7-4 */
 547                 __raw_writel(__raw_readl(INTC_ICR0) | 0x00c00000, INTC_ICR0);
 548                 register_intc_controller(&intc_irq_desc);
 549                 break;
 550         case IRQ_MODE_IRL7654:
 551                 /* enable IRL7-4 but don't provide any masking */
 552                 __raw_writel(0x40000000, INTC_INTMSKCLR1);
 553                 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
 554                 break;
 555         case IRQ_MODE_IRL3210:
 556                 /* enable IRL0-3 but don't provide any masking */
 557                 __raw_writel(0x80000000, INTC_INTMSKCLR1);
 558                 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
 559                 break;
 560         case IRQ_MODE_IRL7654_MASK:
 561                 /* enable IRL7-4 and mask using cpu intc controller */
 562                 __raw_writel(0x40000000, INTC_INTMSKCLR1);
 563                 register_intc_controller(&intc_irl7654_desc);
 564                 break;
 565         case IRQ_MODE_IRL3210_MASK:
 566                 /* enable IRL0-3 and mask using cpu intc controller */
 567                 __raw_writel(0x80000000, INTC_INTMSKCLR1);
 568                 register_intc_controller(&intc_irl3210_desc);
 569                 break;
 570         default:
 571                 BUG();
 572         }
 573 }