arch/sh/kernel/cpu/sh4a/setup-sh7757.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * SH7757 Setup
   4  *
   5  * Copyright (C) 2009, 2011  Renesas Solutions Corp.
   6  *
   7  *  based on setup-sh7785.c : Copyright (C) 2007  Paul Mundt
   8  */
   9 #include <linux/platform_device.h>
  10 #include <linux/init.h>
  11 #include <linux/serial.h>
  12 #include <linux/serial_sci.h>
  13 #include <linux/io.h>
  14 #include <linux/mm.h>
  15 #include <linux/dma-mapping.h>
  16 #include <linux/sh_timer.h>
  17 #include <linux/sh_dma.h>
  18 #include <linux/sh_intc.h>
  19 #include <linux/usb/ohci_pdriver.h>
  20 #include <cpu/dma-register.h>
  21 #include <cpu/sh7757.h>
  22 #include <asm/platform_early.h>
  23
  24 static struct plat_sci_port scif2_platform_data = {
  25         .scscr          = SCSCR_REIE,
  26         .type           = PORT_SCIF,
  27 };
  28
  29 static struct resource scif2_resources[] = {
  30         DEFINE_RES_MEM(0xfe4b0000, 0x100),              /* SCIF2 */
  31         DEFINE_RES_IRQ(evt2irq(0x700)),
  32 };
  33
  34 static struct platform_device scif2_device = {
  35         .name           = "sh-sci",
  36         .id             = 0,
  37         .resource       = scif2_resources,
  38         .num_resources  = ARRAY_SIZE(scif2_resources),
  39         .dev            = {
  40                 .platform_data  = &scif2_platform_data,
  41         },
  42 };
  43
  44 static struct plat_sci_port scif3_platform_data = {
  45         .scscr          = SCSCR_REIE,
  46         .type           = PORT_SCIF,
  47 };
  48
  49 static struct resource scif3_resources[] = {
  50         DEFINE_RES_MEM(0xfe4c0000, 0x100),              /* SCIF3 */
  51         DEFINE_RES_IRQ(evt2irq(0xb80)),
  52 };
  53
  54 static struct platform_device scif3_device = {
  55         .name           = "sh-sci",
  56         .id             = 1,
  57         .resource       = scif3_resources,
  58         .num_resources  = ARRAY_SIZE(scif3_resources),
  59         .dev            = {
  60                 .platform_data  = &scif3_platform_data,
  61         },
  62 };
  63
  64 static struct plat_sci_port scif4_platform_data = {
  65         .scscr          = SCSCR_REIE,
  66         .type           = PORT_SCIF,
  67 };
  68
  69 static struct resource scif4_resources[] = {
  70         DEFINE_RES_MEM(0xfe4d0000, 0x100),              /* SCIF4 */
  71         DEFINE_RES_IRQ(evt2irq(0xf00)),
  72 };
  73
  74 static struct platform_device scif4_device = {
  75         .name           = "sh-sci",
  76         .id             = 2,
  77         .resource       = scif4_resources,
  78         .num_resources  = ARRAY_SIZE(scif4_resources),
  79         .dev            = {
  80                 .platform_data  = &scif4_platform_data,
  81         },
  82 };
  83
  84 static struct sh_timer_config tmu0_platform_data = {
  85         .channels_mask = 3,
  86 };
  87
  88 static struct resource tmu0_resources[] = {
  89         DEFINE_RES_MEM(0xfe430000, 0x20),
  90         DEFINE_RES_IRQ(evt2irq(0x580)),
  91         DEFINE_RES_IRQ(evt2irq(0x5a0)),
  92 };
  93
  94 static struct platform_device tmu0_device = {
  95         .name           = "sh-tmu",
  96         .id             = 0,
  97         .dev = {
  98                 .platform_data  = &tmu0_platform_data,
  99         },
 100         .resource       = tmu0_resources,
 101         .num_resources  = ARRAY_SIZE(tmu0_resources),
 102 };
 103
 104 static struct resource spi0_resources[] = {
 105         [0] = {
 106                 .start  = 0xfe002000,
 107                 .end    = 0xfe0020ff,
 108                 .flags  = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
 109         },
 110         [1] = {
 111                 .start  = evt2irq(0xcc0),
 112                 .flags  = IORESOURCE_IRQ,
 113         },
 114 };
 115
 116 /* DMA */
 117 static const struct sh_dmae_slave_config sh7757_dmae0_slaves[] = {
 118         {
 119                 .slave_id       = SHDMA_SLAVE_SDHI_TX,
 120                 .addr           = 0x1fe50030,
 121                 .chcr           = SM_INC | RS_ERS | 0x40000000 |
 122                                   TS_INDEX2VAL(XMIT_SZ_16BIT),
 123                 .mid_rid        = 0xc5,
 124         },
 125         {
 126                 .slave_id       = SHDMA_SLAVE_SDHI_RX,
 127                 .addr           = 0x1fe50030,
 128                 .chcr           = DM_INC | RS_ERS | 0x40000000 |
 129                                   TS_INDEX2VAL(XMIT_SZ_16BIT),
 130                 .mid_rid        = 0xc6,
 131         },
 132         {
 133                 .slave_id       = SHDMA_SLAVE_MMCIF_TX,
 134                 .addr           = 0x1fcb0034,
 135                 .chcr           = SM_INC | RS_ERS | 0x40000000 |
 136                                   TS_INDEX2VAL(XMIT_SZ_32BIT),
 137                 .mid_rid        = 0xd3,
 138         },
 139         {
 140                 .slave_id       = SHDMA_SLAVE_MMCIF_RX,
 141                 .addr           = 0x1fcb0034,
 142                 .chcr           = DM_INC | RS_ERS | 0x40000000 |
 143                                   TS_INDEX2VAL(XMIT_SZ_32BIT),
 144                 .mid_rid        = 0xd7,
 145         },
 146 };
 147
 148 static const struct sh_dmae_slave_config sh7757_dmae1_slaves[] = {
 149         {
 150                 .slave_id       = SHDMA_SLAVE_SCIF2_TX,
 151                 .addr           = 0x1f4b000c,
 152                 .chcr           = SM_INC | RS_ERS | 0x40000000 |
 153                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 154                 .mid_rid        = 0x21,
 155         },
 156         {
 157                 .slave_id       = SHDMA_SLAVE_SCIF2_RX,
 158                 .addr           = 0x1f4b0014,
 159                 .chcr           = DM_INC | RS_ERS | 0x40000000 |
 160                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 161                 .mid_rid        = 0x22,
 162         },
 163         {
 164                 .slave_id       = SHDMA_SLAVE_SCIF3_TX,
 165                 .addr           = 0x1f4c000c,
 166                 .chcr           = SM_INC | RS_ERS | 0x40000000 |
 167                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 168                 .mid_rid        = 0x29,
 169         },
 170         {
 171                 .slave_id       = SHDMA_SLAVE_SCIF3_RX,
 172                 .addr           = 0x1f4c0014,
 173                 .chcr           = DM_INC | RS_ERS | 0x40000000 |
 174                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 175                 .mid_rid        = 0x2a,
 176         },
 177         {
 178                 .slave_id       = SHDMA_SLAVE_SCIF4_TX,
 179                 .addr           = 0x1f4d000c,
 180                 .chcr           = SM_INC | RS_ERS | 0x40000000 |
 181                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 182                 .mid_rid        = 0x41,
 183         },
 184         {
 185                 .slave_id       = SHDMA_SLAVE_SCIF4_RX,
 186                 .addr           = 0x1f4d0014,
 187                 .chcr           = DM_INC | RS_ERS | 0x40000000 |
 188                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 189                 .mid_rid        = 0x42,
 190         },
 191         {
 192                 .slave_id       = SHDMA_SLAVE_RSPI_TX,
 193                 .addr           = 0xfe480004,
 194                 .chcr           = SM_INC | RS_ERS | 0x40000000 |
 195                                   TS_INDEX2VAL(XMIT_SZ_16BIT),
 196                 .mid_rid        = 0xc1,
 197         },
 198         {
 199                 .slave_id       = SHDMA_SLAVE_RSPI_RX,
 200                 .addr           = 0xfe480004,
 201                 .chcr           = DM_INC | RS_ERS | 0x40000000 |
 202                                   TS_INDEX2VAL(XMIT_SZ_16BIT),
 203                 .mid_rid        = 0xc2,
 204         },
 205 };
 206
 207 static const struct sh_dmae_slave_config sh7757_dmae2_slaves[] = {
 208         {
 209                 .slave_id       = SHDMA_SLAVE_RIIC0_TX,
 210                 .addr           = 0x1e500012,
 211                 .chcr           = SM_INC | RS_ERS | 0x40000000 |
 212                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 213                 .mid_rid        = 0x21,
 214         },
 215         {
 216                 .slave_id       = SHDMA_SLAVE_RIIC0_RX,
 217                 .addr           = 0x1e500013,
 218                 .chcr           = DM_INC | RS_ERS | 0x40000000 |
 219                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 220                 .mid_rid        = 0x22,
 221         },
 222         {
 223                 .slave_id       = SHDMA_SLAVE_RIIC1_TX,
 224                 .addr           = 0x1e510012,
 225                 .chcr           = SM_INC | RS_ERS | 0x40000000 |
 226                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 227                 .mid_rid        = 0x29,
 228         },
 229         {
 230                 .slave_id       = SHDMA_SLAVE_RIIC1_RX,
 231                 .addr           = 0x1e510013,
 232                 .chcr           = DM_INC | RS_ERS | 0x40000000 |
 233                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 234                 .mid_rid        = 0x2a,
 235         },
 236         {
 237                 .slave_id       = SHDMA_SLAVE_RIIC2_TX,
 238                 .addr           = 0x1e520012,
 239                 .chcr           = SM_INC | RS_ERS | 0x40000000 |
 240                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 241                 .mid_rid        = 0xa1,
 242         },
 243         {
 244                 .slave_id       = SHDMA_SLAVE_RIIC2_RX,
 245                 .addr           = 0x1e520013,
 246                 .chcr           = DM_INC | RS_ERS | 0x40000000 |
 247                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 248                 .mid_rid        = 0xa2,
 249         },
 250         {
 251                 .slave_id       = SHDMA_SLAVE_RIIC3_TX,
 252                 .addr           = 0x1e530012,
 253                 .chcr           = SM_INC | RS_ERS | 0x40000000 |
 254                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 255                 .mid_rid        = 0xa9,
 256         },
 257         {
 258                 .slave_id       = SHDMA_SLAVE_RIIC3_RX,
 259                 .addr           = 0x1e530013,
 260                 .chcr           = DM_INC | RS_ERS | 0x40000000 |
 261                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 262                 .mid_rid        = 0xaf,
 263         },
 264         {
 265                 .slave_id       = SHDMA_SLAVE_RIIC4_TX,
 266                 .addr           = 0x1e540012,
 267                 .chcr           = SM_INC | RS_ERS | 0x40000000 |
 268                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 269                 .mid_rid        = 0xc5,
 270         },
 271         {
 272                 .slave_id       = SHDMA_SLAVE_RIIC4_RX,
 273                 .addr           = 0x1e540013,
 274                 .chcr           = DM_INC | RS_ERS | 0x40000000 |
 275                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 276                 .mid_rid        = 0xc6,
 277         },
 278 };
 279
 280 static const struct sh_dmae_slave_config sh7757_dmae3_slaves[] = {
 281         {
 282                 .slave_id       = SHDMA_SLAVE_RIIC5_TX,
 283                 .addr           = 0x1e550012,
 284                 .chcr           = SM_INC | RS_ERS | 0x40000000 |
 285                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 286                 .mid_rid        = 0x21,
 287         },
 288         {
 289                 .slave_id       = SHDMA_SLAVE_RIIC5_RX,
 290                 .addr           = 0x1e550013,
 291                 .chcr           = DM_INC | RS_ERS | 0x40000000 |
 292                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 293                 .mid_rid        = 0x22,
 294         },
 295         {
 296                 .slave_id       = SHDMA_SLAVE_RIIC6_TX,
 297                 .addr           = 0x1e560012,
 298                 .chcr           = SM_INC | RS_ERS | 0x40000000 |
 299                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 300                 .mid_rid        = 0x29,
 301         },
 302         {
 303                 .slave_id       = SHDMA_SLAVE_RIIC6_RX,
 304                 .addr           = 0x1e560013,
 305                 .chcr           = DM_INC | RS_ERS | 0x40000000 |
 306                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 307                 .mid_rid        = 0x2a,
 308         },
 309         {
 310                 .slave_id       = SHDMA_SLAVE_RIIC7_TX,
 311                 .addr           = 0x1e570012,
 312                 .chcr           = SM_INC | RS_ERS | 0x40000000 |
 313                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 314                 .mid_rid        = 0x41,
 315         },
 316         {
 317                 .slave_id       = SHDMA_SLAVE_RIIC7_RX,
 318                 .addr           = 0x1e570013,
 319                 .chcr           = DM_INC | RS_ERS | 0x40000000 |
 320                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 321                 .mid_rid        = 0x42,
 322         },
 323         {
 324                 .slave_id       = SHDMA_SLAVE_RIIC8_TX,
 325                 .addr           = 0x1e580012,
 326                 .chcr           = SM_INC | RS_ERS | 0x40000000 |
 327                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 328                 .mid_rid        = 0x45,
 329         },
 330         {
 331                 .slave_id       = SHDMA_SLAVE_RIIC8_RX,
 332                 .addr           = 0x1e580013,
 333                 .chcr           = DM_INC | RS_ERS | 0x40000000 |
 334                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 335                 .mid_rid        = 0x46,
 336         },
 337         {
 338                 .slave_id       = SHDMA_SLAVE_RIIC9_TX,
 339                 .addr           = 0x1e590012,
 340                 .chcr           = SM_INC | RS_ERS | 0x40000000 |
 341                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 342                 .mid_rid        = 0x51,
 343         },
 344         {
 345                 .slave_id       = SHDMA_SLAVE_RIIC9_RX,
 346                 .addr           = 0x1e590013,
 347                 .chcr           = DM_INC | RS_ERS | 0x40000000 |
 348                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 349                 .mid_rid        = 0x52,
 350         },
 351 };
 352
 353 static const struct sh_dmae_channel sh7757_dmae_channels[] = {
 354         {
 355                 .offset = 0,
 356                 .dmars = 0,
 357                 .dmars_bit = 0,
 358         }, {
 359                 .offset = 0x10,
 360                 .dmars = 0,
 361                 .dmars_bit = 8,
 362         }, {
 363                 .offset = 0x20,
 364                 .dmars = 4,
 365                 .dmars_bit = 0,
 366         }, {
 367                 .offset = 0x30,
 368                 .dmars = 4,
 369                 .dmars_bit = 8,
 370         }, {
 371                 .offset = 0x50,
 372                 .dmars = 8,
 373                 .dmars_bit = 0,
 374         }, {
 375                 .offset = 0x60,
 376                 .dmars = 8,
 377                 .dmars_bit = 8,
 378         }
 379 };
 380
 381 static const unsigned int ts_shift[] = TS_SHIFT;
 382
 383 static struct sh_dmae_pdata dma0_platform_data = {
 384         .slave          = sh7757_dmae0_slaves,
 385         .slave_num      = ARRAY_SIZE(sh7757_dmae0_slaves),
 386         .channel        = sh7757_dmae_channels,
 387         .channel_num    = ARRAY_SIZE(sh7757_dmae_channels),
 388         .ts_low_shift   = CHCR_TS_LOW_SHIFT,
 389         .ts_low_mask    = CHCR_TS_LOW_MASK,
 390         .ts_high_shift  = CHCR_TS_HIGH_SHIFT,
 391         .ts_high_mask   = CHCR_TS_HIGH_MASK,
 392         .ts_shift       = ts_shift,
 393         .ts_shift_num   = ARRAY_SIZE(ts_shift),
 394         .dmaor_init     = DMAOR_INIT,
 395 };
 396
 397 static struct sh_dmae_pdata dma1_platform_data = {
 398         .slave          = sh7757_dmae1_slaves,
 399         .slave_num      = ARRAY_SIZE(sh7757_dmae1_slaves),
 400         .channel        = sh7757_dmae_channels,
 401         .channel_num    = ARRAY_SIZE(sh7757_dmae_channels),
 402         .ts_low_shift   = CHCR_TS_LOW_SHIFT,
 403         .ts_low_mask    = CHCR_TS_LOW_MASK,
 404         .ts_high_shift  = CHCR_TS_HIGH_SHIFT,
 405         .ts_high_mask   = CHCR_TS_HIGH_MASK,
 406         .ts_shift       = ts_shift,
 407         .ts_shift_num   = ARRAY_SIZE(ts_shift),
 408         .dmaor_init     = DMAOR_INIT,
 409 };
 410
 411 static struct sh_dmae_pdata dma2_platform_data = {
 412         .slave          = sh7757_dmae2_slaves,
 413         .slave_num      = ARRAY_SIZE(sh7757_dmae2_slaves),
 414         .channel        = sh7757_dmae_channels,
 415         .channel_num    = ARRAY_SIZE(sh7757_dmae_channels),
 416         .ts_low_shift   = CHCR_TS_LOW_SHIFT,
 417         .ts_low_mask    = CHCR_TS_LOW_MASK,
 418         .ts_high_shift  = CHCR_TS_HIGH_SHIFT,
 419         .ts_high_mask   = CHCR_TS_HIGH_MASK,
 420         .ts_shift       = ts_shift,
 421         .ts_shift_num   = ARRAY_SIZE(ts_shift),
 422         .dmaor_init     = DMAOR_INIT,
 423 };
 424
 425 static struct sh_dmae_pdata dma3_platform_data = {
 426         .slave          = sh7757_dmae3_slaves,
 427         .slave_num      = ARRAY_SIZE(sh7757_dmae3_slaves),
 428         .channel        = sh7757_dmae_channels,
 429         .channel_num    = ARRAY_SIZE(sh7757_dmae_channels),
 430         .ts_low_shift   = CHCR_TS_LOW_SHIFT,
 431         .ts_low_mask    = CHCR_TS_LOW_MASK,
 432         .ts_high_shift  = CHCR_TS_HIGH_SHIFT,
 433         .ts_high_mask   = CHCR_TS_HIGH_MASK,
 434         .ts_shift       = ts_shift,
 435         .ts_shift_num   = ARRAY_SIZE(ts_shift),
 436         .dmaor_init     = DMAOR_INIT,
 437 };
 438
 439 /* channel 0 to 5 */
 440 static struct resource sh7757_dmae0_resources[] = {
 441         [0] = {
 442                 /* Channel registers and DMAOR */
 443                 .start  = 0xff608020,
 444                 .end    = 0xff60808f,
 445                 .flags  = IORESOURCE_MEM,
 446         },
 447         [1] = {
 448                 /* DMARSx */
 449                 .start  = 0xff609000,
 450                 .end    = 0xff60900b,
 451                 .flags  = IORESOURCE_MEM,
 452         },
 453         {
 454                 .name   = "error_irq",
 455                 .start  = evt2irq(0x640),
 456                 .end    = evt2irq(0x640),
 457                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
 458         },
 459 };
 460
 461 /* channel 6 to 11 */
 462 static struct resource sh7757_dmae1_resources[] = {
 463         [0] = {
 464                 /* Channel registers and DMAOR */
 465                 .start  = 0xff618020,
 466                 .end    = 0xff61808f,
 467                 .flags  = IORESOURCE_MEM,
 468         },
 469         [1] = {
 470                 /* DMARSx */
 471                 .start  = 0xff619000,
 472                 .end    = 0xff61900b,
 473                 .flags  = IORESOURCE_MEM,
 474         },
 475         {
 476                 .name   = "error_irq",
 477                 .start  = evt2irq(0x640),
 478                 .end    = evt2irq(0x640),
 479                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
 480         },
 481         {
 482                 /* IRQ for channels 4 */
 483                 .start  = evt2irq(0x7c0),
 484                 .end    = evt2irq(0x7c0),
 485                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
 486         },
 487         {
 488                 /* IRQ for channels 5 */
 489                 .start  = evt2irq(0x7c0),
 490                 .end    = evt2irq(0x7c0),
 491                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
 492         },
 493         {
 494                 /* IRQ for channels 6 */
 495                 .start  = evt2irq(0xd00),
 496                 .end    = evt2irq(0xd00),
 497                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
 498         },
 499         {
 500                 /* IRQ for channels 7 */
 501                 .start  = evt2irq(0xd00),
 502                 .end    = evt2irq(0xd00),
 503                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
 504         },
 505         {
 506                 /* IRQ for channels 8 */
 507                 .start  = evt2irq(0xd00),
 508                 .end    = evt2irq(0xd00),
 509                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
 510         },
 511         {
 512                 /* IRQ for channels 9 */
 513                 .start  = evt2irq(0xd00),
 514                 .end    = evt2irq(0xd00),
 515                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
 516         },
 517         {
 518                 /* IRQ for channels 10 */
 519                 .start  = evt2irq(0xd00),
 520                 .end    = evt2irq(0xd00),
 521                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
 522         },
 523         {
 524                 /* IRQ for channels 11 */
 525                 .start  = evt2irq(0xd00),
 526                 .end    = evt2irq(0xd00),
 527                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
 528         },
 529 };
 530
 531 /* channel 12 to 17 */
 532 static struct resource sh7757_dmae2_resources[] = {
 533         [0] = {
 534                 /* Channel registers and DMAOR */
 535                 .start  = 0xff708020,
 536                 .end    = 0xff70808f,
 537                 .flags  = IORESOURCE_MEM,
 538         },
 539         [1] = {
 540                 /* DMARSx */
 541                 .start  = 0xff709000,
 542                 .end    = 0xff70900b,
 543                 .flags  = IORESOURCE_MEM,
 544         },
 545         {
 546                 .name   = "error_irq",
 547                 .start  = evt2irq(0x2a60),
 548                 .end    = evt2irq(0x2a60),
 549                 .flags  = IORESOURCE_IRQ,
 550         },
 551         {
 552                 /* IRQ for channels 12 to 16 */
 553                 .start  = evt2irq(0x2400),
 554                 .end    = evt2irq(0x2480),
 555                 .flags  = IORESOURCE_IRQ,
 556         },
 557         {
 558                 /* IRQ for channel 17 */
 559                 .start  = evt2irq(0x24e0),
 560                 .end    = evt2irq(0x24e0),
 561                 .flags  = IORESOURCE_IRQ,
 562         },
 563 };
 564
 565 /* channel 18 to 23 */
 566 static struct resource sh7757_dmae3_resources[] = {
 567         [0] = {
 568                 /* Channel registers and DMAOR */
 569                 .start  = 0xff718020,
 570                 .end    = 0xff71808f,
 571                 .flags  = IORESOURCE_MEM,
 572         },
 573         [1] = {
 574                 /* DMARSx */
 575                 .start  = 0xff719000,
 576                 .end    = 0xff71900b,
 577                 .flags  = IORESOURCE_MEM,
 578         },
 579         {
 580                 .name   = "error_irq",
 581                 .start  = evt2irq(0x2a80),
 582                 .end    = evt2irq(0x2a80),
 583                 .flags  = IORESOURCE_IRQ,
 584         },
 585         {
 586                 /* IRQ for channels 18 to 22 */
 587                 .start  = evt2irq(0x2500),
 588                 .end    = evt2irq(0x2580),
 589                 .flags  = IORESOURCE_IRQ,
 590         },
 591         {
 592                 /* IRQ for channel 23 */
 593                 .start  = evt2irq(0x2600),
 594                 .end    = evt2irq(0x2600),
 595                 .flags  = IORESOURCE_IRQ,
 596         },
 597 };
 598
 599 static struct platform_device dma0_device = {
 600         .name           = "sh-dma-engine",
 601         .id             = 0,
 602         .resource       = sh7757_dmae0_resources,
 603         .num_resources  = ARRAY_SIZE(sh7757_dmae0_resources),
 604         .dev            = {
 605                 .platform_data  = &dma0_platform_data,
 606         },
 607 };
 608
 609 static struct platform_device dma1_device = {
 610         .name           = "sh-dma-engine",
 611         .id             = 1,
 612         .resource       = sh7757_dmae1_resources,
 613         .num_resources  = ARRAY_SIZE(sh7757_dmae1_resources),
 614         .dev            = {
 615                 .platform_data  = &dma1_platform_data,
 616         },
 617 };
 618
 619 static struct platform_device dma2_device = {
 620         .name           = "sh-dma-engine",
 621         .id             = 2,
 622         .resource       = sh7757_dmae2_resources,
 623         .num_resources  = ARRAY_SIZE(sh7757_dmae2_resources),
 624         .dev            = {
 625                 .platform_data  = &dma2_platform_data,
 626         },
 627 };
 628
 629 static struct platform_device dma3_device = {
 630         .name           = "sh-dma-engine",
 631         .id             = 3,
 632         .resource       = sh7757_dmae3_resources,
 633         .num_resources  = ARRAY_SIZE(sh7757_dmae3_resources),
 634         .dev            = {
 635                 .platform_data  = &dma3_platform_data,
 636         },
 637 };
 638
 639 static struct platform_device spi0_device = {
 640         .name   = "sh_spi",
 641         .id     = 0,
 642         .dev    = {
 643                 .dma_mask               = NULL,
 644                 .coherent_dma_mask      = 0xffffffff,
 645         },
 646         .num_resources  = ARRAY_SIZE(spi0_resources),
 647         .resource       = spi0_resources,
 648 };
 649
 650 static struct resource spi1_resources[] = {
 651         {
 652                 .start  = 0xffd8ee70,
 653                 .end    = 0xffd8eeff,
 654                 .flags  = IORESOURCE_MEM | IORESOURCE_MEM_8BIT,
 655         },
 656         {
 657                 .start  = evt2irq(0x8c0),
 658                 .flags  = IORESOURCE_IRQ,
 659         },
 660 };
 661
 662 static struct platform_device spi1_device = {
 663         .name   = "sh_spi",
 664         .id     = 1,
 665         .num_resources  = ARRAY_SIZE(spi1_resources),
 666         .resource       = spi1_resources,
 667 };
 668
 669 static struct resource rspi_resources[] = {
 670         {
 671                 .start  = 0xfe480000,
 672                 .end    = 0xfe4800ff,
 673                 .flags  = IORESOURCE_MEM,
 674         },
 675         {
 676                 .start  = evt2irq(0x1d80),
 677                 .flags  = IORESOURCE_IRQ,
 678         },
 679 };
 680
 681 static struct platform_device rspi_device = {
 682         .name   = "rspi",
 683         .id     = 2,
 684         .num_resources  = ARRAY_SIZE(rspi_resources),
 685         .resource       = rspi_resources,
 686 };
 687
 688 static struct resource usb_ehci_resources[] = {
 689         [0] = {
 690                 .start  = 0xfe4f1000,
 691                 .end    = 0xfe4f10ff,
 692                 .flags  = IORESOURCE_MEM,
 693         },
 694         [1] = {
 695                 .start  = evt2irq(0x920),
 696                 .end    = evt2irq(0x920),
 697                 .flags  = IORESOURCE_IRQ,
 698         },
 699 };
 700
 701 static struct platform_device usb_ehci_device = {
 702         .name           = "sh_ehci",
 703         .id             = -1,
 704         .dev = {
 705                 .dma_mask = &usb_ehci_device.dev.coherent_dma_mask,
 706                 .coherent_dma_mask = DMA_BIT_MASK(32),
 707         },
 708         .num_resources  = ARRAY_SIZE(usb_ehci_resources),
 709         .resource       = usb_ehci_resources,
 710 };
 711
 712 static struct resource usb_ohci_resources[] = {
 713         [0] = {
 714                 .start  = 0xfe4f1800,
 715                 .end    = 0xfe4f18ff,
 716                 .flags  = IORESOURCE_MEM,
 717         },
 718         [1] = {
 719                 .start  = evt2irq(0x920),
 720                 .end    = evt2irq(0x920),
 721                 .flags  = IORESOURCE_IRQ,
 722         },
 723 };
 724
 725 static struct usb_ohci_pdata usb_ohci_pdata;
 726
 727 static struct platform_device usb_ohci_device = {
 728         .name           = "ohci-platform",
 729         .id             = -1,
 730         .dev = {
 731                 .dma_mask = &usb_ohci_device.dev.coherent_dma_mask,
 732                 .coherent_dma_mask = DMA_BIT_MASK(32),
 733                 .platform_data  = &usb_ohci_pdata,
 734         },
 735         .num_resources  = ARRAY_SIZE(usb_ohci_resources),
 736         .resource       = usb_ohci_resources,
 737 };
 738
 739 static struct platform_device *sh7757_devices[] __initdata = {
 740         &scif2_device,
 741         &scif3_device,
 742         &scif4_device,
 743         &tmu0_device,
 744         &dma0_device,
 745         &dma1_device,
 746         &dma2_device,
 747         &dma3_device,
 748         &spi0_device,
 749         &spi1_device,
 750         &rspi_device,
 751         &usb_ehci_device,
 752         &usb_ohci_device,
 753 };
 754
 755 static int __init sh7757_devices_setup(void)
 756 {
 757         return platform_add_devices(sh7757_devices,
 758                                     ARRAY_SIZE(sh7757_devices));
 759 }
 760 arch_initcall(sh7757_devices_setup);
 761
 762 static struct platform_device *sh7757_early_devices[] __initdata = {
 763         &scif2_device,
 764         &scif3_device,
 765         &scif4_device,
 766         &tmu0_device,
 767 };
 768
 769 void __init plat_early_device_setup(void)
 770 {
 771         sh_early_platform_add_devices(sh7757_early_devices,
 772                                    ARRAY_SIZE(sh7757_early_devices));
 773 }
 774
 775 enum {
 776         UNUSED = 0,
 777
 778         /* interrupt sources */
 779
 780         IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
 781         IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
 782         IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
 783         IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
 784
 785         IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
 786         IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
 787         IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
 788         IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
 789         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
 790
 791         SDHI, DVC,
 792         IRQ8, IRQ9, IRQ11, IRQ10, IRQ12, IRQ13, IRQ14, IRQ15,
 793         TMU0, TMU1, TMU2, TMU2_TICPI, TMU3, TMU4, TMU5,
 794         HUDI,
 795         ARC4,
 796         DMAC0_5, DMAC6_7, DMAC8_11,
 797         SCIF0, SCIF1, SCIF2, SCIF3, SCIF4,
 798         USB0, USB1,
 799         JMC,
 800         SPI0, SPI1,
 801         TMR01, TMR23, TMR45,
 802         FRT,
 803         LPC, LPC5, LPC6, LPC7, LPC8,
 804         PECI0, PECI1, PECI2, PECI3, PECI4, PECI5,
 805         ETHERC,
 806         ADC0, ADC1,
 807         SIM,
 808         IIC0_0, IIC0_1, IIC0_2, IIC0_3,
 809         IIC1_0, IIC1_1, IIC1_2, IIC1_3,
 810         IIC2_0, IIC2_1, IIC2_2, IIC2_3,
 811         IIC3_0, IIC3_1, IIC3_2, IIC3_3,
 812         IIC4_0, IIC4_1, IIC4_2, IIC4_3,
 813         IIC5_0, IIC5_1, IIC5_2, IIC5_3,
 814         IIC6_0, IIC6_1, IIC6_2, IIC6_3,
 815         IIC7_0, IIC7_1, IIC7_2, IIC7_3,
 816         IIC8_0, IIC8_1, IIC8_2, IIC8_3,
 817         IIC9_0, IIC9_1, IIC9_2, IIC9_3,
 818         ONFICTL,
 819         MMC1, MMC2,
 820         ECCU,
 821         PCIC,
 822         G200,
 823         RSPI,
 824         SGPIO,
 825         DMINT12, DMINT13, DMINT14, DMINT15, DMINT16, DMINT17, DMINT18, DMINT19,
 826         DMINT20, DMINT21, DMINT22, DMINT23,
 827         DDRECC,
 828         TSIP,
 829         PCIE_BRIDGE,
 830         WDT0B, WDT1B, WDT2B, WDT3B, WDT4B, WDT5B, WDT6B, WDT7B, WDT8B,
 831         GETHER0, GETHER1, GETHER2,
 832         PBIA, PBIB, PBIC,
 833         DMAE2, DMAE3,
 834         SERMUX2, SERMUX3,
 835
 836         /* interrupt groups */
 837
 838         TMU012, TMU345,
 839 };
 840
 841 static struct intc_vect vectors[] __initdata = {
 842         INTC_VECT(SDHI, 0x480), INTC_VECT(SDHI, 0x04a0),
 843         INTC_VECT(SDHI, 0x4c0),
 844         INTC_VECT(DVC, 0x4e0),
 845         INTC_VECT(IRQ8, 0x500), INTC_VECT(IRQ9, 0x520),
 846         INTC_VECT(IRQ10, 0x540),
 847         INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
 848         INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
 849         INTC_VECT(HUDI, 0x600),
 850         INTC_VECT(ARC4, 0x620),
 851         INTC_VECT(DMAC0_5, 0x640), INTC_VECT(DMAC0_5, 0x660),
 852         INTC_VECT(DMAC0_5, 0x680), INTC_VECT(DMAC0_5, 0x6a0),
 853         INTC_VECT(DMAC0_5, 0x6c0),
 854         INTC_VECT(IRQ11, 0x6e0),
 855         INTC_VECT(SCIF2, 0x700), INTC_VECT(SCIF2, 0x720),
 856         INTC_VECT(SCIF2, 0x740), INTC_VECT(SCIF2, 0x760),
 857         INTC_VECT(DMAC0_5, 0x780), INTC_VECT(DMAC0_5, 0x7a0),
 858         INTC_VECT(DMAC6_7, 0x7c0), INTC_VECT(DMAC6_7, 0x7e0),
 859         INTC_VECT(USB0, 0x840),
 860         INTC_VECT(IRQ12, 0x880),
 861         INTC_VECT(JMC, 0x8a0),
 862         INTC_VECT(SPI1, 0x8c0),
 863         INTC_VECT(IRQ13, 0x8e0), INTC_VECT(IRQ14, 0x900),
 864         INTC_VECT(USB1, 0x920),
 865         INTC_VECT(TMR01, 0xa00), INTC_VECT(TMR23, 0xa20),
 866         INTC_VECT(TMR45, 0xa40),
 867         INTC_VECT(FRT, 0xa80),
 868         INTC_VECT(LPC, 0xaa0), INTC_VECT(LPC, 0xac0),
 869         INTC_VECT(LPC, 0xae0), INTC_VECT(LPC, 0xb00),
 870         INTC_VECT(LPC, 0xb20),
 871         INTC_VECT(SCIF0, 0xb40), INTC_VECT(SCIF1, 0xb60),
 872         INTC_VECT(SCIF3, 0xb80), INTC_VECT(SCIF3, 0xba0),
 873         INTC_VECT(SCIF3, 0xbc0), INTC_VECT(SCIF3, 0xbe0),
 874         INTC_VECT(PECI0, 0xc00), INTC_VECT(PECI1, 0xc20),
 875         INTC_VECT(PECI2, 0xc40),
 876         INTC_VECT(IRQ15, 0xc60),
 877         INTC_VECT(ETHERC, 0xc80), INTC_VECT(ETHERC, 0xca0),
 878         INTC_VECT(SPI0, 0xcc0),
 879         INTC_VECT(ADC1, 0xce0),
 880         INTC_VECT(DMAC8_11, 0xd00), INTC_VECT(DMAC8_11, 0xd20),
 881         INTC_VECT(DMAC8_11, 0xd40), INTC_VECT(DMAC8_11, 0xd60),
 882         INTC_VECT(SIM, 0xd80), INTC_VECT(SIM, 0xda0),
 883         INTC_VECT(SIM, 0xdc0), INTC_VECT(SIM, 0xde0),
 884         INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
 885         INTC_VECT(TMU5, 0xe40),
 886         INTC_VECT(ADC0, 0xe60),
 887         INTC_VECT(SCIF4, 0xf00), INTC_VECT(SCIF4, 0xf20),
 888         INTC_VECT(SCIF4, 0xf40), INTC_VECT(SCIF4, 0xf60),
 889         INTC_VECT(IIC0_0, 0x1400), INTC_VECT(IIC0_1, 0x1420),
 890         INTC_VECT(IIC0_2, 0x1440), INTC_VECT(IIC0_3, 0x1460),
 891         INTC_VECT(IIC1_0, 0x1480), INTC_VECT(IIC1_1, 0x14e0),
 892         INTC_VECT(IIC1_2, 0x1500), INTC_VECT(IIC1_3, 0x1520),
 893         INTC_VECT(IIC2_0, 0x1540), INTC_VECT(IIC2_1, 0x1560),
 894         INTC_VECT(IIC2_2, 0x1580), INTC_VECT(IIC2_3, 0x1600),
 895         INTC_VECT(IIC3_0, 0x1620), INTC_VECT(IIC3_1, 0x1640),
 896         INTC_VECT(IIC3_2, 0x16e0), INTC_VECT(IIC3_3, 0x1700),
 897         INTC_VECT(IIC4_0, 0x17c0), INTC_VECT(IIC4_1, 0x1800),
 898         INTC_VECT(IIC4_2, 0x1820), INTC_VECT(IIC4_3, 0x1840),
 899         INTC_VECT(IIC5_0, 0x1860), INTC_VECT(IIC5_1, 0x1880),
 900         INTC_VECT(IIC5_2, 0x18a0), INTC_VECT(IIC5_3, 0x18c0),
 901         INTC_VECT(IIC6_0, 0x18e0), INTC_VECT(IIC6_1, 0x1900),
 902         INTC_VECT(IIC6_2, 0x1920),
 903         INTC_VECT(ONFICTL, 0x1960),
 904         INTC_VECT(IIC6_3, 0x1980),
 905         INTC_VECT(IIC7_0, 0x19a0), INTC_VECT(IIC7_1, 0x1a00),
 906         INTC_VECT(IIC7_2, 0x1a20), INTC_VECT(IIC7_3, 0x1a40),
 907         INTC_VECT(IIC8_0, 0x1a60), INTC_VECT(IIC8_1, 0x1a80),
 908         INTC_VECT(IIC8_2, 0x1aa0), INTC_VECT(IIC8_3, 0x1b40),
 909         INTC_VECT(IIC9_0, 0x1b60), INTC_VECT(IIC9_1, 0x1b80),
 910         INTC_VECT(IIC9_2, 0x1c00), INTC_VECT(IIC9_3, 0x1c20),
 911         INTC_VECT(MMC1, 0x1c60), INTC_VECT(MMC2, 0x1c80),
 912         INTC_VECT(ECCU, 0x1cc0),
 913         INTC_VECT(PCIC, 0x1ce0),
 914         INTC_VECT(G200, 0x1d00),
 915         INTC_VECT(RSPI, 0x1d80), INTC_VECT(RSPI, 0x1da0),
 916         INTC_VECT(RSPI, 0x1dc0), INTC_VECT(RSPI, 0x1de0),
 917         INTC_VECT(PECI3, 0x1ec0), INTC_VECT(PECI4, 0x1ee0),
 918         INTC_VECT(PECI5, 0x1f00),
 919         INTC_VECT(SGPIO, 0x1f80), INTC_VECT(SGPIO, 0x1fa0),
 920         INTC_VECT(SGPIO, 0x1fc0),
 921         INTC_VECT(DMINT12, 0x2400), INTC_VECT(DMINT13, 0x2420),
 922         INTC_VECT(DMINT14, 0x2440), INTC_VECT(DMINT15, 0x2460),
 923         INTC_VECT(DMINT16, 0x2480), INTC_VECT(DMINT17, 0x24e0),
 924         INTC_VECT(DMINT18, 0x2500), INTC_VECT(DMINT19, 0x2520),
 925         INTC_VECT(DMINT20, 0x2540), INTC_VECT(DMINT21, 0x2560),
 926         INTC_VECT(DMINT22, 0x2580), INTC_VECT(DMINT23, 0x2600),
 927         INTC_VECT(DDRECC, 0x2620),
 928         INTC_VECT(TSIP, 0x2640),
 929         INTC_VECT(PCIE_BRIDGE, 0x27c0),
 930         INTC_VECT(WDT0B, 0x2800), INTC_VECT(WDT1B, 0x2820),
 931         INTC_VECT(WDT2B, 0x2840), INTC_VECT(WDT3B, 0x2860),
 932         INTC_VECT(WDT4B, 0x2880), INTC_VECT(WDT5B, 0x28a0),
 933         INTC_VECT(WDT6B, 0x28c0), INTC_VECT(WDT7B, 0x28e0),
 934         INTC_VECT(WDT8B, 0x2900),
 935         INTC_VECT(GETHER0, 0x2960), INTC_VECT(GETHER1, 0x2980),
 936         INTC_VECT(GETHER2, 0x29a0),
 937         INTC_VECT(PBIA, 0x2a00), INTC_VECT(PBIB, 0x2a20),
 938         INTC_VECT(PBIC, 0x2a40),
 939         INTC_VECT(DMAE2, 0x2a60), INTC_VECT(DMAE3, 0x2a80),
 940         INTC_VECT(SERMUX2, 0x2aa0), INTC_VECT(SERMUX3, 0x2b40),
 941         INTC_VECT(LPC5, 0x2b60), INTC_VECT(LPC6, 0x2b80),
 942         INTC_VECT(LPC7, 0x2c00), INTC_VECT(LPC8, 0x2c20),
 943 };
 944
 945 static struct intc_group groups[] __initdata = {
 946         INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
 947         INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
 948 };
 949
 950 static struct intc_mask_reg mask_registers[] __initdata = {
 951         { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
 952           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 953
 954         { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
 955           { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
 956             IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
 957             IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
 958             IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
 959             IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
 960             IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
 961             IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
 962             IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
 963
 964         { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
 965           { 0, 0, 0, 0, 0, 0, 0, 0,
 966             0, DMAC8_11, 0, PECI0, LPC, FRT, 0, TMR45,
 967             TMR23, TMR01, 0, 0, 0, 0, 0, DMAC0_5,
 968             HUDI, 0, 0, SCIF3, SCIF2, SDHI, TMU345, TMU012
 969              } },
 970
 971         { 0xffd400d0, 0xffd400d4, 32, /* INT2MSKR1 / INT2MSKCR1 */
 972           { IRQ15, IRQ14, IRQ13, IRQ12, IRQ11, IRQ10, SCIF4, ETHERC,
 973             IRQ9, IRQ8, SCIF1, SCIF0, USB0, 0, 0, USB1,
 974             ADC1, 0, DMAC6_7, ADC0, SPI0, SIM, PECI2, PECI1,
 975             ARC4, 0, SPI1, JMC, 0, 0, 0, DVC
 976              } },
 977
 978         { 0xffd10038, 0xffd1003c, 32, /* INT2MSKR2 / INT2MSKCR2 */
 979           { IIC4_1, IIC4_2, IIC5_0, ONFICTL, 0, 0, SGPIO, 0,
 980             0, G200, 0, IIC9_2, IIC8_2, IIC8_1, IIC8_0, IIC7_3,
 981             IIC7_2, IIC7_1, IIC6_3, IIC0_0, IIC0_1, IIC0_2, IIC0_3, IIC3_1,
 982             IIC2_3, 0, IIC2_1, IIC9_1, IIC3_3, IIC1_0, 0, IIC2_2
 983              } },
 984
 985         { 0xffd100d0, 0xffd100d4, 32, /* INT2MSKR3 / INT2MSKCR3 */
 986           { MMC1, IIC6_1, IIC6_0, IIC5_1, IIC3_2, IIC2_0, PECI5, MMC2,
 987             IIC1_3, IIC1_2, IIC9_0, IIC8_3, IIC4_3, IIC7_0, 0, IIC6_2,
 988             PCIC, 0, IIC4_0, 0, ECCU, RSPI, 0, IIC9_3,
 989             IIC3_0, 0, IIC5_3, IIC5_2, 0, 0, 0, IIC1_1
 990              } },
 991
 992         { 0xffd20038, 0xffd2003c, 32, /* INT2MSKR4 / INT2MSKCR4 */
 993           { WDT0B, WDT1B, WDT3B, GETHER0, 0, 0, 0, 0,
 994             0, 0, 0, LPC7, SERMUX2, DMAE3, DMAE2, PBIC,
 995             PBIB, PBIA, GETHER1, DMINT12, DMINT13, DMINT14, DMINT15, TSIP,
 996             DMINT23, 0, DMINT21, LPC6, 0, DMINT16, 0, DMINT22
 997              } },
 998
 999         { 0xffd200d0, 0xffd200d4, 32, /* INT2MSKR5 / INT2MSKCR5 */
1000           { 0, WDT8B, WDT7B, WDT4B, 0, DMINT20, 0, 0,
1001             DMINT19, DMINT18, LPC5, SERMUX3, WDT2B, GETHER2, 0, 0,
1002             0, 0, PCIE_BRIDGE, 0, 0, 0, 0, LPC8,
1003             DDRECC, 0, WDT6B, WDT5B, 0, 0, 0, DMINT17
1004              } },
1005 };
1006
1007 #define INTPRI          0xffd00010
1008 #define INT2PRI0        0xffd40000
1009 #define INT2PRI1        0xffd40004
1010 #define INT2PRI2        0xffd40008
1011 #define INT2PRI3        0xffd4000c
1012 #define INT2PRI4        0xffd40010
1013 #define INT2PRI5        0xffd40014
1014 #define INT2PRI6        0xffd40018
1015 #define INT2PRI7        0xffd4001c
1016 #define INT2PRI8        0xffd400a0
1017 #define INT2PRI9        0xffd400a4
1018 #define INT2PRI10       0xffd400a8
1019 #define INT2PRI11       0xffd400ac
1020 #define INT2PRI12       0xffd400b0
1021 #define INT2PRI13       0xffd400b4
1022 #define INT2PRI14       0xffd400b8
1023 #define INT2PRI15       0xffd400bc
1024 #define INT2PRI16       0xffd10000
1025 #define INT2PRI17       0xffd10004
1026 #define INT2PRI18       0xffd10008
1027 #define INT2PRI19       0xffd1000c
1028 #define INT2PRI20       0xffd10010
1029 #define INT2PRI21       0xffd10014
1030 #define INT2PRI22       0xffd10018
1031 #define INT2PRI23       0xffd1001c
1032 #define INT2PRI24       0xffd100a0
1033 #define INT2PRI25       0xffd100a4
1034 #define INT2PRI26       0xffd100a8
1035 #define INT2PRI27       0xffd100ac
1036 #define INT2PRI28       0xffd100b0
1037 #define INT2PRI29       0xffd100b4
1038 #define INT2PRI30       0xffd100b8
1039 #define INT2PRI31       0xffd100bc
1040 #define INT2PRI32       0xffd20000
1041 #define INT2PRI33       0xffd20004
1042 #define INT2PRI34       0xffd20008
1043 #define INT2PRI35       0xffd2000c
1044 #define INT2PRI36       0xffd20010
1045 #define INT2PRI37       0xffd20014
1046 #define INT2PRI38       0xffd20018
1047 #define INT2PRI39       0xffd2001c
1048 #define INT2PRI40       0xffd200a0
1049 #define INT2PRI41       0xffd200a4
1050 #define INT2PRI42       0xffd200a8
1051 #define INT2PRI43       0xffd200ac
1052 #define INT2PRI44       0xffd200b0
1053 #define INT2PRI45       0xffd200b4
1054 #define INT2PRI46       0xffd200b8
1055 #define INT2PRI47       0xffd200bc
1056
1057 static struct intc_prio_reg prio_registers[] __initdata = {
1058         { INTPRI, 0, 32, 4, { IRQ0, IRQ1, IRQ2, IRQ3,
1059                               IRQ4, IRQ5, IRQ6, IRQ7 } },
1060
1061         { INT2PRI0, 0, 32, 8, { TMU0, TMU1, TMU2, TMU2_TICPI } },
1062         { INT2PRI1, 0, 32, 8, { TMU3, TMU4, TMU5, SDHI } },
1063         { INT2PRI2, 0, 32, 8, { SCIF2, SCIF3, 0, IRQ8 } },
1064         { INT2PRI3, 0, 32, 8, { HUDI, DMAC0_5, ADC0, IRQ9 } },
1065         { INT2PRI4, 0, 32, 8, { IRQ10, 0, TMR01, TMR23 } },
1066         { INT2PRI5, 0, 32, 8, { TMR45, 0, FRT, LPC } },
1067         { INT2PRI6, 0, 32, 8, { PECI0, ETHERC, DMAC8_11, 0 } },
1068         { INT2PRI7, 0, 32, 8, { SCIF4, 0, IRQ11, IRQ12 } },
1069         { INT2PRI8, 0, 32, 8, { 0, 0, 0, DVC } },
1070         { INT2PRI9, 0, 32, 8, { ARC4, 0, SPI1, JMC } },
1071         { INT2PRI10, 0, 32, 8, { SPI0, SIM, PECI2, PECI1 } },
1072         { INT2PRI11, 0, 32, 8, { ADC1, IRQ13, DMAC6_7, IRQ14 } },
1073         { INT2PRI12, 0, 32, 8, { USB0, 0, IRQ15, USB1 } },
1074         { INT2PRI13, 0, 32, 8, { 0, 0, SCIF1, SCIF0 } },
1075
1076         { INT2PRI16, 0, 32, 8, { IIC2_2, 0, 0, 0 } },
1077         { INT2PRI17, 0, 32, 8, { 0, 0, 0, IIC1_0 } },
1078         { INT2PRI18, 0, 32, 8, { IIC3_3, IIC9_1, IIC2_1, IIC1_2 } },
1079         { INT2PRI19, 0, 32, 8, { IIC2_3, IIC3_1, 0, IIC1_3 } },
1080         { INT2PRI20, 0, 32, 8, { IIC2_0, IIC6_3, IIC7_1, IIC7_2 } },
1081         { INT2PRI21, 0, 32, 8, { IIC7_3, IIC8_0, IIC8_1, IIC8_2 } },
1082         { INT2PRI22, 0, 32, 8, { IIC9_2, MMC2, G200, 0 } },
1083         { INT2PRI23, 0, 32, 8, { PECI5, SGPIO, IIC3_2, IIC5_1 } },
1084         { INT2PRI24, 0, 32, 8, { PECI4, PECI3, 0, IIC1_1 } },
1085         { INT2PRI25, 0, 32, 8, { IIC3_0, 0, IIC5_3, IIC5_2 } },
1086         { INT2PRI26, 0, 32, 8, { ECCU, RSPI, 0, IIC9_3 } },
1087         { INT2PRI27, 0, 32, 8, { PCIC, IIC6_0, IIC4_0, IIC6_1 } },
1088         { INT2PRI28, 0, 32, 8, { IIC4_3, IIC7_0, MMC1, IIC6_2 } },
1089         { INT2PRI29, 0, 32, 8, { 0, 0, IIC9_0, IIC8_3 } },
1090         { INT2PRI30, 0, 32, 8, { IIC4_1, IIC4_2, IIC5_0, ONFICTL } },
1091         { INT2PRI31, 0, 32, 8, { IIC0_0, IIC0_1, IIC0_2, IIC0_3 } },
1092         { INT2PRI32, 0, 32, 8, { DMINT22, 0, 0, 0 } },
1093         { INT2PRI33, 0, 32, 8, { 0, 0, 0, DMINT16 } },
1094         { INT2PRI34, 0, 32, 8, { 0, LPC6, DMINT21, DMINT18 } },
1095         { INT2PRI35, 0, 32, 8, { DMINT23, TSIP, 0, DMINT19 } },
1096         { INT2PRI36, 0, 32, 8, { DMINT20, GETHER1, PBIA, PBIB } },
1097         { INT2PRI37, 0, 32, 8, { PBIC, DMAE2, DMAE3, SERMUX2 } },
1098         { INT2PRI38, 0, 32, 8, { LPC7, 0, 0, 0 } },
1099         { INT2PRI39, 0, 32, 8, { 0, 0, 0, WDT4B } },
1100         { INT2PRI40, 0, 32, 8, { 0, 0, 0, DMINT17 } },
1101         { INT2PRI41, 0, 32, 8, { DDRECC, 0, WDT6B, WDT5B } },
1102         { INT2PRI42, 0, 32, 8, { 0, 0, 0, LPC8 } },
1103         { INT2PRI43, 0, 32, 8, { 0, WDT7B, PCIE_BRIDGE, WDT8B } },
1104         { INT2PRI44, 0, 32, 8, { WDT2B, GETHER2, 0, 0 } },
1105         { INT2PRI45, 0, 32, 8, { 0, 0, LPC5, SERMUX3 } },
1106         { INT2PRI46, 0, 32, 8, { WDT0B, WDT1B, WDT3B, GETHER0 } },
1107         { INT2PRI47, 0, 32, 8, { DMINT12, DMINT13, DMINT14, DMINT15 } },
1108 };
1109
1110 static struct intc_sense_reg sense_registers_irq8to15[] __initdata = {
1111         { 0xffd100f8, 32, 2, /* ICR2 */   { IRQ15, IRQ14, IRQ13, IRQ12,
1112                                             IRQ11, IRQ10, IRQ9, IRQ8 } },
1113 };
1114
1115 static DECLARE_INTC_DESC(intc_desc, "sh7757", vectors, groups,
1116                          mask_registers, prio_registers,
1117                          sense_registers_irq8to15);
1118
1119 /* Support for external interrupt pins in IRQ mode */
1120 static struct intc_vect vectors_irq0123[] __initdata = {
1121         INTC_VECT(IRQ0, 0x200), INTC_VECT(IRQ1, 0x240),
1122         INTC_VECT(IRQ2, 0x280), INTC_VECT(IRQ3, 0x2c0),
1123 };
1124
1125 static struct intc_vect vectors_irq4567[] __initdata = {
1126         INTC_VECT(IRQ4, 0x300), INTC_VECT(IRQ5, 0x340),
1127         INTC_VECT(IRQ6, 0x380), INTC_VECT(IRQ7, 0x3c0),
1128 };
1129
1130 static struct intc_sense_reg sense_registers[] __initdata = {
1131         { 0xffd0001c, 32, 2, /* ICR1 */   { IRQ0, IRQ1, IRQ2, IRQ3,
1132                                             IRQ4, IRQ5, IRQ6, IRQ7 } },
1133 };
1134
1135 static struct intc_mask_reg ack_registers[] __initdata = {
1136         { 0xffd00024, 0, 32, /* INTREQ */
1137           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
1138 };
1139
1140 static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7757-irq0123",
1141                              vectors_irq0123, NULL, mask_registers,
1142                              prio_registers, sense_registers, ack_registers);
1143
1144 static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7757-irq4567",
1145                              vectors_irq4567, NULL, mask_registers,
1146                              prio_registers, sense_registers, ack_registers);
1147
1148 /* External interrupt pins in IRL mode */
1149 static struct intc_vect vectors_irl0123[] __initdata = {
1150         INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
1151         INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
1152         INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
1153         INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
1154         INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
1155         INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
1156         INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
1157         INTC_VECT(IRL0_HHHL, 0x3c0),
1158 };
1159
1160 static struct intc_vect vectors_irl4567[] __initdata = {
1161         INTC_VECT(IRL4_LLLL, 0x200), INTC_VECT(IRL4_LLLH, 0x220),
1162         INTC_VECT(IRL4_LLHL, 0x240), INTC_VECT(IRL4_LLHH, 0x260),
1163         INTC_VECT(IRL4_LHLL, 0x280), INTC_VECT(IRL4_LHLH, 0x2a0),
1164         INTC_VECT(IRL4_LHHL, 0x2c0), INTC_VECT(IRL4_LHHH, 0x2e0),
1165         INTC_VECT(IRL4_HLLL, 0x300), INTC_VECT(IRL4_HLLH, 0x320),
1166         INTC_VECT(IRL4_HLHL, 0x340), INTC_VECT(IRL4_HLHH, 0x360),
1167         INTC_VECT(IRL4_HHLL, 0x380), INTC_VECT(IRL4_HHLH, 0x3a0),
1168         INTC_VECT(IRL4_HHHL, 0x3c0),
1169 };
1170
1171 static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7757-irl0123", vectors_irl0123,
1172                          NULL, mask_registers, NULL, NULL);
1173
1174 static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7757-irl4567", vectors_irl4567,
1175                          NULL, mask_registers, NULL, NULL);
1176
1177 #define INTC_ICR0       0xffd00000
1178 #define INTC_INTMSK0    0xffd00044
1179 #define INTC_INTMSK1    0xffd00048
1180 #define INTC_INTMSK2    0xffd40080
1181 #define INTC_INTMSKCLR1 0xffd00068
1182 #define INTC_INTMSKCLR2 0xffd40084
1183
1184 void __init plat_irq_setup(void)
1185 {
1186         /* disable IRQ3-0 + IRQ7-4 */
1187         __raw_writel(0xff000000, INTC_INTMSK0);
1188
1189         /* disable IRL3-0 + IRL7-4 */
1190         __raw_writel(0xc0000000, INTC_INTMSK1);
1191         __raw_writel(0xfffefffe, INTC_INTMSK2);
1192
1193         /* select IRL mode for IRL3-0 + IRL7-4 */
1194         __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
1195
1196         /* disable holding function, ie enable "SH-4 Mode" */
1197         __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
1198
1199         register_intc_controller(&intc_desc);
1200 }
1201
1202 void __init plat_irq_setup_pins(int mode)
1203 {
1204         switch (mode) {
1205         case IRQ_MODE_IRQ7654:
1206                 /* select IRQ mode for IRL7-4 */
1207                 __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0);
1208                 register_intc_controller(&intc_desc_irq4567);
1209                 break;
1210         case IRQ_MODE_IRQ3210:
1211                 /* select IRQ mode for IRL3-0 */
1212                 __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
1213                 register_intc_controller(&intc_desc_irq0123);
1214                 break;
1215         case IRQ_MODE_IRL7654:
1216                 /* enable IRL7-4 but don't provide any masking */
1217                 __raw_writel(0x40000000, INTC_INTMSKCLR1);
1218                 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
1219                 break;
1220         case IRQ_MODE_IRL3210:
1221                 /* enable IRL0-3 but don't provide any masking */
1222                 __raw_writel(0x80000000, INTC_INTMSKCLR1);
1223                 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
1224                 break;
1225         case IRQ_MODE_IRL7654_MASK:
1226                 /* enable IRL7-4 and mask using cpu intc controller */
1227                 __raw_writel(0x40000000, INTC_INTMSKCLR1);
1228                 register_intc_controller(&intc_desc_irl4567);
1229                 break;
1230         case IRQ_MODE_IRL3210_MASK:
1231                 /* enable IRL0-3 and mask using cpu intc controller */
1232                 __raw_writel(0x80000000, INTC_INTMSKCLR1);
1233                 register_intc_controller(&intc_desc_irl0123);
1234                 break;
1235         default:
1236                 BUG();
1237         }
1238 }
1239
1240 void __init plat_mem_setup(void)
1241 {
1242 }