arch/sh/kernel/cpu/sh4a/clock-sh7786.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * arch/sh/kernel/cpu/sh4a/clock-sh7786.c
   4  *
   5  * SH7786 support for the clock framework
   6  *
   7  *  Copyright (C) 2010  Paul Mundt
   8  */
   9 #include <linux/init.h>
  10 #include <linux/kernel.h>
  11 #include <linux/clk.h>
  12 #include <linux/io.h>
  13 #include <linux/clkdev.h>
  14 #include <asm/clock.h>
  15 #include <asm/freq.h>
  16
  17 /*
  18  * Default rate for the root input clock, reset this with clk_set_rate()
  19  * from the platform code.
  20  */
  21 static struct clk extal_clk = {
  22         .rate           = 33333333,
  23 };
  24
  25 static unsigned long pll_recalc(struct clk *clk)
  26 {
  27         int multiplier;
  28
  29         /*
  30          * Clock modes 0, 1, and 2 use an x64 multiplier against PLL1,
  31          * while modes 3, 4, and 5 use an x32.
  32          */
  33         multiplier = (sh_mv.mv_mode_pins() & 0xf) < 3 ? 64 : 32;
  34
  35         return clk->parent->rate * multiplier;
  36 }
  37
  38 static struct sh_clk_ops pll_clk_ops = {
  39         .recalc         = pll_recalc,
  40 };
  41
  42 static struct clk pll_clk = {
  43         .ops            = &pll_clk_ops,
  44         .parent         = &extal_clk,
  45         .flags          = CLK_ENABLE_ON_INIT,
  46 };
  47
  48 static struct clk *clks[] = {
  49         &extal_clk,
  50         &pll_clk,
  51 };
  52
  53 static unsigned int div2[] = { 1, 2, 4, 6, 8, 12, 16, 18,
  54                                24, 32, 36, 48 };
  55
  56 static struct clk_div_mult_table div4_div_mult_table = {
  57         .divisors = div2,
  58         .nr_divisors = ARRAY_SIZE(div2),
  59 };
  60
  61 static struct clk_div4_table div4_table = {
  62         .div_mult_table = &div4_div_mult_table,
  63 };
  64
  65 enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_DU, DIV4_P, DIV4_NR };
  66
  67 #define DIV4(_bit, _mask, _flags) \
  68   SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags)
  69
  70 struct clk div4_clks[DIV4_NR] = {
  71         [DIV4_P] = DIV4(0, 0x0b40, 0),
  72         [DIV4_DU] = DIV4(4, 0x0010, 0),
  73         [DIV4_DDR] = DIV4(12, 0x0002, CLK_ENABLE_ON_INIT),
  74         [DIV4_B] = DIV4(16, 0x0360, CLK_ENABLE_ON_INIT),
  75         [DIV4_SH] = DIV4(20, 0x0002, CLK_ENABLE_ON_INIT),
  76         [DIV4_I] = DIV4(28, 0x0006, CLK_ENABLE_ON_INIT),
  77 };
  78
  79 #define MSTPCR0         0xffc40030
  80 #define MSTPCR1         0xffc40034
  81
  82 enum { MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024,
  83        MSTP023, MSTP022, MSTP021, MSTP020, MSTP017, MSTP016,
  84        MSTP015, MSTP014, MSTP011, MSTP010, MSTP009, MSTP008,
  85        MSTP005, MSTP004, MSTP002,
  86        MSTP112, MSTP110, MSTP109, MSTP108,
  87        MSTP105, MSTP104, MSTP103, MSTP102,
  88        MSTP_NR };
  89
  90 static struct clk mstp_clks[MSTP_NR] = {
  91         /* MSTPCR0 */
  92         [MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0),
  93         [MSTP028] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 28, 0),
  94         [MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0),
  95         [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0),
  96         [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0),
  97         [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0),
  98         [MSTP023] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 23, 0),
  99         [MSTP022] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 22, 0),
 100         [MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
 101         [MSTP020] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 20, 0),
 102         [MSTP017] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 17, 0),
 103         [MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0),
 104         [MSTP015] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
 105         [MSTP014] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 14, 0),
 106         [MSTP011] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 11, 0),
 107         [MSTP010] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
 108         [MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
 109         [MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
 110         [MSTP005] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 5, 0),
 111         [MSTP004] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 4, 0),
 112         [MSTP002] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 2, 0),
 113
 114         /* MSTPCR1 */
 115         [MSTP112] = SH_CLK_MSTP32(NULL, MSTPCR1, 12, 0),
 116         [MSTP110] = SH_CLK_MSTP32(NULL, MSTPCR1, 10, 0),
 117         [MSTP109] = SH_CLK_MSTP32(NULL, MSTPCR1, 9, 0),
 118         [MSTP108] = SH_CLK_MSTP32(NULL, MSTPCR1, 8, 0),
 119         [MSTP105] = SH_CLK_MSTP32(NULL, MSTPCR1, 5, 0),
 120         [MSTP104] = SH_CLK_MSTP32(NULL, MSTPCR1, 4, 0),
 121         [MSTP103] = SH_CLK_MSTP32(NULL, MSTPCR1, 3, 0),
 122         [MSTP102] = SH_CLK_MSTP32(NULL, MSTPCR1, 2, 0),
 123 };
 124
 125 static struct clk_lookup lookups[] = {
 126         /* main clocks */
 127         CLKDEV_CON_ID("extal", &extal_clk),
 128         CLKDEV_CON_ID("pll_clk", &pll_clk),
 129
 130         /* DIV4 clocks */
 131         CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
 132         CLKDEV_CON_ID("du_clk", &div4_clks[DIV4_DU]),
 133         CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_DDR]),
 134         CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
 135         CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
 136         CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
 137
 138         /* MSTP32 clocks */
 139         CLKDEV_ICK_ID("fck", "sh-sci.5", &mstp_clks[MSTP029]),
 140         CLKDEV_ICK_ID("fck", "sh-sci.4", &mstp_clks[MSTP028]),
 141         CLKDEV_ICK_ID("fck", "sh-sci.3", &mstp_clks[MSTP027]),
 142         CLKDEV_ICK_ID("fck", "sh-sci.2", &mstp_clks[MSTP026]),
 143         CLKDEV_ICK_ID("fck", "sh-sci.1", &mstp_clks[MSTP025]),
 144         CLKDEV_ICK_ID("fck", "sh-sci.0", &mstp_clks[MSTP024]),
 145
 146         CLKDEV_CON_ID("ssi3_fck", &mstp_clks[MSTP023]),
 147         CLKDEV_CON_ID("ssi2_fck", &mstp_clks[MSTP022]),
 148         CLKDEV_CON_ID("ssi1_fck", &mstp_clks[MSTP021]),
 149         CLKDEV_CON_ID("ssi0_fck", &mstp_clks[MSTP020]),
 150         CLKDEV_CON_ID("hac1_fck", &mstp_clks[MSTP017]),
 151         CLKDEV_CON_ID("hac0_fck", &mstp_clks[MSTP016]),
 152         CLKDEV_CON_ID("i2c1_fck", &mstp_clks[MSTP015]),
 153         CLKDEV_CON_ID("i2c0_fck", &mstp_clks[MSTP014]),
 154
 155         CLKDEV_ICK_ID("fck", "sh-tmu.0", &mstp_clks[MSTP008]),
 156         CLKDEV_ICK_ID("fck", "sh-tmu.1", &mstp_clks[MSTP009]),
 157         CLKDEV_ICK_ID("fck", "sh-tmu.2", &mstp_clks[MSTP010]),
 158         CLKDEV_ICK_ID("fck", "sh-tmu.3", &mstp_clks[MSTP011]),
 159
 160         CLKDEV_CON_ID("sdif1_fck", &mstp_clks[MSTP005]),
 161         CLKDEV_CON_ID("sdif0_fck", &mstp_clks[MSTP004]),
 162         CLKDEV_CON_ID("hspi_fck", &mstp_clks[MSTP002]),
 163         CLKDEV_CON_ID("usb_fck", &mstp_clks[MSTP112]),
 164         CLKDEV_CON_ID("pcie2_fck", &mstp_clks[MSTP110]),
 165         CLKDEV_CON_ID("pcie1_fck", &mstp_clks[MSTP109]),
 166         CLKDEV_CON_ID("pcie0_fck", &mstp_clks[MSTP108]),
 167         CLKDEV_CON_ID("dmac_11_6_fck", &mstp_clks[MSTP105]),
 168         CLKDEV_CON_ID("dmac_5_0_fck", &mstp_clks[MSTP104]),
 169         CLKDEV_CON_ID("du_fck", &mstp_clks[MSTP103]),
 170         CLKDEV_CON_ID("ether_fck", &mstp_clks[MSTP102]),
 171 };
 172
 173 int __init arch_clk_init(void)
 174 {
 175         int i, ret = 0;
 176
 177         for (i = 0; i < ARRAY_SIZE(clks); i++)
 178                 ret |= clk_register(clks[i]);
 179
 180         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 181
 182         if (!ret)
 183                 ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks),
 184                                            &div4_table);
 185         if (!ret)
 186                 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
 187
 188         return ret;
 189 }