arch/sh/kernel/cpu/sh2a/clock-sh7203.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * arch/sh/kernel/cpu/sh2a/clock-sh7203.c
   4  *
   5  * SH7203 support for the clock framework
   6  *
   7  *  Copyright (C) 2007 Kieran Bingham (MPC-Data Ltd)
   8  *
   9  * Based on clock-sh7263.c
  10  *  Copyright (C) 2006  Yoshinori Sato
  11  *
  12  * Based on clock-sh4.c
  13  *  Copyright (C) 2005  Paul Mundt
  14  */
  15 #include <linux/init.h>
  16 #include <linux/kernel.h>
  17 #include <asm/clock.h>
  18 #include <asm/freq.h>
  19 #include <asm/io.h>
  20
  21 static const int pll1rate[]={8,12,16,0};
  22 static const int pfc_divisors[]={1,2,3,4,6,8,12};
  23 #define ifc_divisors pfc_divisors
  24
  25 static unsigned int pll2_mult;
  26
  27 static void master_clk_init(struct clk *clk)
  28 {
  29         clk->rate *= pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0003] * pll2_mult;
  30 }
  31
  32 static struct sh_clk_ops sh7203_master_clk_ops = {
  33         .init           = master_clk_init,
  34 };
  35
  36 static unsigned long module_clk_recalc(struct clk *clk)
  37 {
  38         int idx = (__raw_readw(FREQCR) & 0x0007);
  39         return clk->parent->rate / pfc_divisors[idx];
  40 }
  41
  42 static struct sh_clk_ops sh7203_module_clk_ops = {
  43         .recalc         = module_clk_recalc,
  44 };
  45
  46 static unsigned long bus_clk_recalc(struct clk *clk)
  47 {
  48         int idx = (__raw_readw(FREQCR) & 0x0007);
  49         return clk->parent->rate / pfc_divisors[idx-2];
  50 }
  51
  52 static struct sh_clk_ops sh7203_bus_clk_ops = {
  53         .recalc         = bus_clk_recalc,
  54 };
  55
  56 static struct sh_clk_ops sh7203_cpu_clk_ops = {
  57         .recalc         = followparent_recalc,
  58 };
  59
  60 static struct sh_clk_ops *sh7203_clk_ops[] = {
  61         &sh7203_master_clk_ops,
  62         &sh7203_module_clk_ops,
  63         &sh7203_bus_clk_ops,
  64         &sh7203_cpu_clk_ops,
  65 };
  66
  67 void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx)
  68 {
  69         if (test_mode_pin(MODE_PIN1))
  70                 pll2_mult = 4;
  71         else if (test_mode_pin(MODE_PIN0))
  72                 pll2_mult = 2;
  73         else
  74                 pll2_mult = 1;
  75
  76         if (idx < ARRAY_SIZE(sh7203_clk_ops))
  77                 *ops = sh7203_clk_ops[idx];
  78 }