2 * include/asm-sh/spinlock-llsc.h
4 * Copyright (C) 2002, 2003 Paul Mundt
5 * Copyright (C) 2006, 2007 Akio Idehara
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
11 #ifndef __ASM_SH_SPINLOCK_LLSC_H
12 #define __ASM_SH_SPINLOCK_LLSC_H
14 #include <asm/barrier.h>
15 #include <asm/processor.h>
18 * Your basic SMP spinlocks, allowing only a single CPU anywhere
21 #define arch_spin_is_locked(x) ((x)->lock <= 0)
22 #define arch_spin_lock_flags(lock, flags) arch_spin_lock(lock)
24 static inline void arch_spin_unlock_wait(arch_spinlock_t *lock)
26 smp_cond_load_acquire(&lock->lock, VAL > 0);
30 * Simple spin lock operations. There are two variants, one clears IRQ's
31 * on the local processor, one does not.
33 * We make no fairness assumptions. They have a cost.
35 static inline void arch_spin_lock(arch_spinlock_t *lock)
40 __asm__ __volatile__ (
42 "movli.l @%2, %0 ! arch_spin_lock \n\t"
45 "movco.l %0, @%2 \n\t"
49 : "=&z" (tmp), "=&r" (oldval)
55 static inline void arch_spin_unlock(arch_spinlock_t *lock)
59 __asm__ __volatile__ (
60 "mov #1, %0 ! arch_spin_unlock \n\t"
68 static inline int arch_spin_trylock(arch_spinlock_t *lock)
70 unsigned long tmp, oldval;
72 __asm__ __volatile__ (
74 "movli.l @%2, %0 ! arch_spin_trylock \n\t"
77 "movco.l %0, @%2 \n\t"
80 : "=&z" (tmp), "=&r" (oldval)
89 * Read-write spinlocks, allowing multiple readers but only one writer.
91 * NOTE! it is quite common to have readers in interrupts but no interrupt
92 * writers. For those circumstances we can "mix" irq-safe locks - any writer
93 * needs to get a irq-safe write-lock, but readers can get non-irqsafe
98 * read_can_lock - would read_trylock() succeed?
99 * @lock: the rwlock in question.
101 #define arch_read_can_lock(x) ((x)->lock > 0)
104 * write_can_lock - would write_trylock() succeed?
105 * @lock: the rwlock in question.
107 #define arch_write_can_lock(x) ((x)->lock == RW_LOCK_BIAS)
109 static inline void arch_read_lock(arch_rwlock_t *rw)
113 __asm__ __volatile__ (
115 "movli.l @%1, %0 ! arch_read_lock \n\t"
119 "movco.l %0, @%1 \n\t"
127 static inline void arch_read_unlock(arch_rwlock_t *rw)
131 __asm__ __volatile__ (
133 "movli.l @%1, %0 ! arch_read_unlock \n\t"
135 "movco.l %0, @%1 \n\t"
143 static inline void arch_write_lock(arch_rwlock_t *rw)
147 __asm__ __volatile__ (
149 "movli.l @%1, %0 ! arch_write_lock \n\t"
153 "movco.l %0, @%1 \n\t"
156 : "r" (&rw->lock), "r" (RW_LOCK_BIAS)
161 static inline void arch_write_unlock(arch_rwlock_t *rw)
163 __asm__ __volatile__ (
164 "mov.l %1, @%0 ! arch_write_unlock \n\t"
166 : "r" (&rw->lock), "r" (RW_LOCK_BIAS)
171 static inline int arch_read_trylock(arch_rwlock_t *rw)
173 unsigned long tmp, oldval;
175 __asm__ __volatile__ (
177 "movli.l @%2, %0 ! arch_read_trylock \n\t"
182 "movco.l %0, @%2 \n\t"
186 : "=&z" (tmp), "=&r" (oldval)
194 static inline int arch_write_trylock(arch_rwlock_t *rw)
196 unsigned long tmp, oldval;
198 __asm__ __volatile__ (
200 "movli.l @%2, %0 ! arch_write_trylock \n\t"
206 "movco.l %0, @%2 \n\t"
209 : "=&z" (tmp), "=&r" (oldval)
210 : "r" (&rw->lock), "r" (RW_LOCK_BIAS)
214 return (oldval > (RW_LOCK_BIAS - 1));
217 #define arch_read_lock_flags(lock, flags) arch_read_lock(lock)
218 #define arch_write_lock_flags(lock, flags) arch_write_lock(lock)
220 #define arch_spin_relax(lock) cpu_relax()
221 #define arch_read_relax(lock) cpu_relax()
222 #define arch_write_relax(lock) cpu_relax()
224 #endif /* __ASM_SH_SPINLOCK_LLSC_H */