1 /* SPDX-License-Identifier: GPL-2.0
3 * include/asm-sh/spinlock-cas.h
5 * Copyright (C) 2015 SEI
7 #ifndef __ASM_SH_SPINLOCK_CAS_H
8 #define __ASM_SH_SPINLOCK_CAS_H
10 #include <asm/barrier.h>
11 #include <asm/processor.h>
13 static inline unsigned __sl_cas(volatile unsigned *p, unsigned old, unsigned new)
15 __asm__ __volatile__("cas.l %1,%0,@r0"
23 * Your basic SMP spinlocks, allowing only a single CPU anywhere
26 #define arch_spin_is_locked(x) ((x)->lock <= 0)
28 static inline void arch_spin_lock(arch_spinlock_t *lock)
30 while (!__sl_cas(&lock->lock, 1, 0));
33 static inline void arch_spin_unlock(arch_spinlock_t *lock)
35 __sl_cas(&lock->lock, 0, 1);
38 static inline int arch_spin_trylock(arch_spinlock_t *lock)
40 return __sl_cas(&lock->lock, 1, 0);
44 * Read-write spinlocks, allowing multiple readers but only one writer.
46 * NOTE! it is quite common to have readers in interrupts but no interrupt
47 * writers. For those circumstances we can "mix" irq-safe locks - any writer
48 * needs to get a irq-safe write-lock, but readers can get non-irqsafe
52 static inline void arch_read_lock(arch_rwlock_t *rw)
56 while (!old || __sl_cas(&rw->lock, old, old-1) != old);
59 static inline void arch_read_unlock(arch_rwlock_t *rw)
63 while (__sl_cas(&rw->lock, old, old+1) != old);
66 static inline void arch_write_lock(arch_rwlock_t *rw)
68 while (__sl_cas(&rw->lock, RW_LOCK_BIAS, 0) != RW_LOCK_BIAS);
71 static inline void arch_write_unlock(arch_rwlock_t *rw)
73 __sl_cas(&rw->lock, 0, RW_LOCK_BIAS);
76 static inline int arch_read_trylock(arch_rwlock_t *rw)
80 while (old && __sl_cas(&rw->lock, old, old-1) != old);
84 static inline int arch_write_trylock(arch_rwlock_t *rw)
86 return __sl_cas(&rw->lock, RW_LOCK_BIAS, 0) == RW_LOCK_BIAS;
89 #endif /* __ASM_SH_SPINLOCK_CAS_H */