1 // SPDX-License-Identifier: GPL-2.0
3 * Generic SH-4 / SH-4A PCIC operations (SH7751, SH7780).
5 * Copyright (C) 2002 - 2009 Paul Mundt
9 #include <linux/spinlock.h>
10 #include <asm/addrspace.h>
14 * Direct access to PCI hardware...
16 #define CONFIG_CMD(bus, devfn, where) \
17 (0x80000000 | (bus->number << 16) | (devfn << 8) | (where & ~3))
20 * Functions for accessing PCI configuration space with type 1 accesses
22 static int sh4_pci_read(struct pci_bus *bus, unsigned int devfn,
23 int where, int size, u32 *val)
25 struct pci_channel *chan = bus->sysdata;
30 * PCIPDR may only be accessed as 32 bit words,
31 * so we must do byte alignment by hand
33 raw_spin_lock_irqsave(&pci_config_lock, flags);
34 pci_write_reg(chan, CONFIG_CMD(bus, devfn, where), SH4_PCIPAR);
35 data = pci_read_reg(chan, SH4_PCIPDR);
36 raw_spin_unlock_irqrestore(&pci_config_lock, flags);
40 *val = (data >> ((where & 3) << 3)) & 0xff;
43 *val = (data >> ((where & 2) << 3)) & 0xffff;
49 return PCIBIOS_FUNC_NOT_SUPPORTED;
52 return PCIBIOS_SUCCESSFUL;
56 * Since SH4 only does 32bit access we'll have to do a read,
57 * mask,write operation.
58 * We'll allow an odd byte offset, though it should be illegal.
60 static int sh4_pci_write(struct pci_bus *bus, unsigned int devfn,
61 int where, int size, u32 val)
63 struct pci_channel *chan = bus->sysdata;
68 raw_spin_lock_irqsave(&pci_config_lock, flags);
69 pci_write_reg(chan, CONFIG_CMD(bus, devfn, where), SH4_PCIPAR);
70 data = pci_read_reg(chan, SH4_PCIPDR);
71 raw_spin_unlock_irqrestore(&pci_config_lock, flags);
75 shift = (where & 3) << 3;
76 data &= ~(0xff << shift);
77 data |= ((val & 0xff) << shift);
80 shift = (where & 2) << 3;
81 data &= ~(0xffff << shift);
82 data |= ((val & 0xffff) << shift);
88 return PCIBIOS_FUNC_NOT_SUPPORTED;
91 pci_write_reg(chan, data, SH4_PCIPDR);
93 return PCIBIOS_SUCCESSFUL;
96 struct pci_ops sh4_pci_ops = {
98 .write = sh4_pci_write,
101 int __attribute__((weak)) pci_fixup_pcic(struct pci_channel *chan)