arch/sh/boot/dts/j2_mimas_v2.dts

   1 /dts-v1/;
   2
   3 / {
   4         compatible = "jcore,j2-soc";
   5         model = "J2 FPGA SoC on Mimas v2 board";
   6
   7         #address-cells = <1>;
   8         #size-cells = <1>;
   9
  10         interrupt-parent = <&aic>;
  11
  12         cpus {
  13                 #address-cells = <1>;
  14                 #size-cells = <0>;
  15
  16                 cpu@0 {
  17                         device_type = "cpu";
  18                         compatible = "jcore,j2";
  19                         reg = <0>;
  20                         clock-frequency = <50000000>;
  21                         d-cache-size = <8192>;
  22                         i-cache-size = <8192>;
  23                         d-cache-block-size = <16>;
  24                         i-cache-block-size = <16>;
  25                 };
  26         };
  27
  28         memory@10000000 {
  29                 device_type = "memory";
  30                 reg = <0x10000000 0x4000000>;
  31         };
  32
  33         aliases {
  34                 serial0 = &uart0;
  35                 spi0 = &spi0;
  36         };
  37
  38         chosen {
  39                 stdout-path = "serial0";
  40         };
  41
  42         soc@abcd0000 {
  43                 compatible = "simple-bus";
  44                 ranges = <0 0xabcd0000 0x100000>;
  45
  46                 #address-cells = <1>;
  47                 #size-cells = <1>;
  48
  49                 aic: interrupt-controller@200 {
  50                         compatible = "jcore,aic1";
  51                         reg = <0x200 0x10>;
  52                         interrupt-controller;
  53                         #interrupt-cells = <1>;
  54                 };
  55
  56                 cache-controller@c0 {
  57                         compatible = "jcore,cache";
  58                         reg = <0xc0 4>;
  59                 };
  60
  61                 timer@200 {
  62                         compatible = "jcore,pit";
  63                         reg = <0x200 0x30>;
  64                         interrupts = <0x48>;
  65                 };
  66
  67                 spi0: spi@40 {
  68                         compatible = "jcore,spi2";
  69
  70                         #address-cells = <1>;
  71                         #size-cells = <0>;
  72
  73                         spi-max-frequency = <25000000>;
  74
  75                         reg = <0x40 0x8>;
  76
  77                         sdcard@0 {
  78                                 compatible = "mmc-spi-slot";
  79                                 reg = <0>;
  80                                 spi-max-frequency = <25000000>;
  81                                 voltage-ranges = <3200 3400>;
  82                                 mode = <0>;
  83                         };
  84                 };
  85
  86                 uart0: serial@100 {
  87                         clock-frequency = <125000000>;
  88                         compatible = "xlnx,xps-uartlite-1.00.a";
  89                         current-speed = <19200>;
  90                         device_type = "serial";
  91                         interrupts = <0x12>;
  92                         port-number = <0>;
  93                         reg = <0x100 0x10>;
  94                 };
  95         };
  96 };