4 compatible = "jcore,j2-soc";
5 model = "J2 FPGA SoC on Mimas v2 board";
10 interrupt-parent = <&aic>;
18 compatible = "jcore,j2";
20 clock-frequency = <50000000>;
21 d-cache-size = <8192>;
22 i-cache-size = <8192>;
23 d-cache-block-size = <16>;
24 i-cache-block-size = <16>;
29 device_type = "memory";
30 reg = <0x10000000 0x4000000>;
39 stdout-path = "serial0";
43 compatible = "simple-bus";
44 ranges = <0 0xabcd0000 0x100000>;
49 aic: interrupt-controller@200 {
50 compatible = "jcore,aic1";
53 #interrupt-cells = <1>;
57 compatible = "jcore,cache";
62 compatible = "jcore,pit";
68 compatible = "jcore,spi2";
73 spi-max-frequency = <25000000>;
78 compatible = "mmc-spi-slot";
80 spi-max-frequency = <25000000>;
81 voltage-ranges = <3200 3400>;
87 clock-frequency = <125000000>;
88 compatible = "xlnx,xps-uartlite-1.00.a";
89 current-speed = <19200>;
90 device_type = "serial";