arch/sh/boards/mach-microdev/fdc37c93xapm.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Setup for the SMSC FDC37C93xAPM
   4  *
   5  * Copyright (C) 2003 Sean McGoogan (Sean.McGoogan@superh.com)
   6  * Copyright (C) 2003, 2004 SuperH, Inc.
   7  * Copyright (C) 2004, 2005 Paul Mundt
   8  *
   9  * SuperH SH4-202 MicroDev board support.
  10  */
  11 #include <linux/init.h>
  12 #include <linux/ioport.h>
  13 #include <linux/io.h>
  14 #include <linux/err.h>
  15 #include <mach/microdev.h>
  16
  17 #define SMSC_CONFIG_PORT_ADDR    (0x3F0)
  18 #define SMSC_INDEX_PORT_ADDR     SMSC_CONFIG_PORT_ADDR
  19 #define SMSC_DATA_PORT_ADDR      (SMSC_INDEX_PORT_ADDR + 1)
  20
  21 #define SMSC_ENTER_CONFIG_KEY    0x55
  22 #define SMSC_EXIT_CONFIG_KEY     0xaa
  23
  24 #define SMCS_LOGICAL_DEV_INDEX   0x07   /* Logical Device Number */
  25 #define SMSC_DEVICE_ID_INDEX     0x20   /* Device ID */
  26 #define SMSC_DEVICE_REV_INDEX    0x21   /* Device Revision */
  27 #define SMSC_ACTIVATE_INDEX      0x30   /* Activate */
  28 #define SMSC_PRIMARY_BASE_INDEX  0x60   /* Primary Base Address */
  29 #define SMSC_SECONDARY_BASE_INDEX 0x62  /* Secondary Base Address */
  30 #define SMSC_PRIMARY_INT_INDEX   0x70   /* Primary Interrupt Select */
  31 #define SMSC_SECONDARY_INT_INDEX 0x72   /* Secondary Interrupt Select */
  32 #define SMSC_HDCS0_INDEX         0xf0   /* HDCS0 Address Decoder */
  33 #define SMSC_HDCS1_INDEX         0xf1   /* HDCS1 Address Decoder */
  34
  35 #define SMSC_IDE1_DEVICE        1       /* IDE #1 logical device */
  36 #define SMSC_IDE2_DEVICE        2       /* IDE #2 logical device */
  37 #define SMSC_PARALLEL_DEVICE    3       /* Parallel Port logical device */
  38 #define SMSC_SERIAL1_DEVICE     4       /* Serial #1 logical device */
  39 #define SMSC_SERIAL2_DEVICE     5       /* Serial #2 logical device */
  40 #define SMSC_KEYBOARD_DEVICE    7       /* Keyboard logical device */
  41 #define SMSC_CONFIG_REGISTERS   8       /* Configuration Registers (Aux I/O) */
  42
  43 #define SMSC_READ_INDEXED(index) ({ \
  44         outb((index), SMSC_INDEX_PORT_ADDR); \
  45         inb(SMSC_DATA_PORT_ADDR); })
  46 #define SMSC_WRITE_INDEXED(val, index) ({ \
  47         outb((index), SMSC_INDEX_PORT_ADDR); \
  48         outb((val),   SMSC_DATA_PORT_ADDR); })
  49
  50 #define IDE1_PRIMARY_BASE       0x01f0  /* Task File Registe base for IDE #1 */
  51 #define IDE1_SECONDARY_BASE     0x03f6  /* Miscellaneous AT registers for IDE #1 */
  52 #define IDE2_PRIMARY_BASE       0x0170  /* Task File Registe base for IDE #2 */
  53 #define IDE2_SECONDARY_BASE     0x0376  /* Miscellaneous AT registers for IDE #2 */
  54
  55 #define SERIAL1_PRIMARY_BASE    0x03f8
  56 #define SERIAL2_PRIMARY_BASE    0x02f8
  57
  58 #define MSB(x)          ( (x) >> 8 )
  59 #define LSB(x)          ( (x) & 0xff )
  60
  61         /* General-Purpose base address on CPU-board FPGA */
  62 #define MICRODEV_FPGA_GP_BASE           0xa6100000ul
  63
  64 static int __init smsc_superio_setup(void)
  65 {
  66
  67         unsigned char devid, devrev;
  68
  69                 /* Initially the chip is in run state */
  70                 /* Put it into configuration state */
  71         outb(SMSC_ENTER_CONFIG_KEY, SMSC_CONFIG_PORT_ADDR);
  72
  73                 /* Read device ID info */
  74         devid  = SMSC_READ_INDEXED(SMSC_DEVICE_ID_INDEX);
  75         devrev = SMSC_READ_INDEXED(SMSC_DEVICE_REV_INDEX);
  76
  77         if ((devid == 0x30) && (devrev == 0x01))
  78                 printk("SMSC FDC37C93xAPM SuperIO device detected\n");
  79         else
  80                 return -ENODEV;
  81
  82                 /* Select the keyboard device */
  83         SMSC_WRITE_INDEXED(SMSC_KEYBOARD_DEVICE, SMCS_LOGICAL_DEV_INDEX);
  84                 /* enable it */
  85         SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);
  86                 /* enable the interrupts */
  87         SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_KEYBOARD, SMSC_PRIMARY_INT_INDEX);
  88         SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_MOUSE, SMSC_SECONDARY_INT_INDEX);
  89
  90                 /* Select the Serial #1 device */
  91         SMSC_WRITE_INDEXED(SMSC_SERIAL1_DEVICE, SMCS_LOGICAL_DEV_INDEX);
  92                 /* enable it */
  93         SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);
  94                 /* program with port addresses */
  95         SMSC_WRITE_INDEXED(MSB(SERIAL1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0);
  96         SMSC_WRITE_INDEXED(LSB(SERIAL1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1);
  97         SMSC_WRITE_INDEXED(0x00, SMSC_HDCS0_INDEX);
  98                 /* enable the interrupts */
  99         SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_SERIAL1, SMSC_PRIMARY_INT_INDEX);
 100
 101                 /* Select the Serial #2 device */
 102         SMSC_WRITE_INDEXED(SMSC_SERIAL2_DEVICE, SMCS_LOGICAL_DEV_INDEX);
 103                 /* enable it */
 104         SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);
 105                 /* program with port addresses */
 106         SMSC_WRITE_INDEXED(MSB(SERIAL2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0);
 107         SMSC_WRITE_INDEXED(LSB(SERIAL2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1);
 108         SMSC_WRITE_INDEXED(0x00, SMSC_HDCS0_INDEX);
 109                 /* enable the interrupts */
 110         SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_SERIAL2, SMSC_PRIMARY_INT_INDEX);
 111
 112                 /* Select the IDE#1 device */
 113         SMSC_WRITE_INDEXED(SMSC_IDE1_DEVICE, SMCS_LOGICAL_DEV_INDEX);
 114                 /* enable it */
 115         SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);
 116                 /* program with port addresses */
 117         SMSC_WRITE_INDEXED(MSB(IDE1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0);
 118         SMSC_WRITE_INDEXED(LSB(IDE1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1);
 119         SMSC_WRITE_INDEXED(MSB(IDE1_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+0);
 120         SMSC_WRITE_INDEXED(LSB(IDE1_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+1);
 121         SMSC_WRITE_INDEXED(0x0c, SMSC_HDCS0_INDEX);
 122         SMSC_WRITE_INDEXED(0x00, SMSC_HDCS1_INDEX);
 123                 /* select the interrupt */
 124         SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_IDE1, SMSC_PRIMARY_INT_INDEX);
 125
 126                 /* Select the IDE#2 device */
 127         SMSC_WRITE_INDEXED(SMSC_IDE2_DEVICE, SMCS_LOGICAL_DEV_INDEX);
 128                 /* enable it */
 129         SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);
 130                 /* program with port addresses */
 131         SMSC_WRITE_INDEXED(MSB(IDE2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0);
 132         SMSC_WRITE_INDEXED(LSB(IDE2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1);
 133         SMSC_WRITE_INDEXED(MSB(IDE2_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+0);
 134         SMSC_WRITE_INDEXED(LSB(IDE2_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+1);
 135                 /* select the interrupt */
 136         SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_IDE2, SMSC_PRIMARY_INT_INDEX);
 137
 138                 /* Select the configuration registers */
 139         SMSC_WRITE_INDEXED(SMSC_CONFIG_REGISTERS, SMCS_LOGICAL_DEV_INDEX);
 140                 /* enable the appropriate GPIO pins for IDE functionality:
 141                  * bit[0]   In/Out              1==input;  0==output
 142                  * bit[1]   Polarity            1==invert; 0==no invert
 143                  * bit[2]   Int Enb #1          1==Enable Combined IRQ #1; 0==disable
 144                  * bit[3:4] Function Select     00==original; 01==Alternate Function #1
 145                  */
 146         SMSC_WRITE_INDEXED(0x00, 0xc2); /* GP42 = nIDE1_OE */
 147         SMSC_WRITE_INDEXED(0x01, 0xc5); /* GP45 = IDE1_IRQ */
 148         SMSC_WRITE_INDEXED(0x00, 0xc6); /* GP46 = nIOROP */
 149         SMSC_WRITE_INDEXED(0x00, 0xc7); /* GP47 = nIOWOP */
 150         SMSC_WRITE_INDEXED(0x08, 0xe8); /* GP20 = nIDE2_OE */
 151
 152                 /* Exit the configuration state */
 153         outb(SMSC_EXIT_CONFIG_KEY, SMSC_CONFIG_PORT_ADDR);
 154
 155         return 0;
 156 }
 157 device_initcall(smsc_superio_setup);