1 // SPDX-License-Identifier: GPL-2.0
3 * hp6x0 Power Management Routines
5 * Copyright (c) 2006 Andriy Skulysh <askulsyh@gmail.com>
7 #include <linux/init.h>
8 #include <linux/suspend.h>
9 #include <linux/errno.h>
10 #include <linux/time.h>
11 #include <linux/delay.h>
12 #include <linux/gfp.h>
14 #include <asm/hd64461.h>
15 #include <asm/bl_bit.h>
16 #include <mach/hp6xx.h>
19 #include <asm/watchdog.h>
21 #define INTR_OFFSET 0x600
23 #define STBCR 0xffffff82
24 #define STBCR2 0xffffff88
26 #define STBCR_STBY 0x80
27 #define STBCR_MSTP2 0x04
29 #define MCR 0xffffff68
30 #define RTCNT 0xffffff70
35 extern u8 wakeup_start;
38 static void pm_enter(void)
47 csr = sh_wdt_read_csr();
49 csr |= WTCSR_CKS_4096;
50 sh_wdt_write_csr(csr);
51 csr = sh_wdt_read_csr();
55 frqcr = __raw_readw(FRQCR);
56 frqcr &= ~(FRQCR_PLLEN | FRQCR_PSTBY);
57 __raw_writew(frqcr, FRQCR);
60 stbcr = __raw_readb(STBCR);
61 __raw_writeb(stbcr | STBCR_STBY | STBCR_MSTP2, STBCR);
63 /* set self-refresh */
64 mcr = __raw_readw(MCR);
65 __raw_writew(mcr & ~MCR_RFSH, MCR);
67 /* set interrupt handler */
68 asm volatile("stc vbr, %0" : "=r" (vbr_old));
69 vbr_new = get_zeroed_page(GFP_ATOMIC);
71 memcpy((void*)(vbr_new + INTR_OFFSET),
72 &wakeup_start, &wakeup_end - &wakeup_start);
73 asm volatile("ldc %0, vbr" : : "r" (vbr_new));
75 __raw_writew(0, RTCNT);
76 __raw_writew(mcr | MCR_RFSH | MCR_RMODE, MCR);
80 asm volatile("ldc %0, vbr" : : "r" (vbr_old));
85 frqcr = __raw_readw(FRQCR);
87 __raw_writew(frqcr, FRQCR);
90 __raw_writew(frqcr, FRQCR);
92 __raw_writeb(stbcr, STBCR);
97 static int hp6x0_pm_enter(suspend_state_t state)
100 #ifdef CONFIG_HD64461_ENABLER
105 #ifdef CONFIG_HD64461_ENABLER
106 outb(0, HD64461_PCC1CSCIER);
108 scr = inb(HD64461_PCC1SCR);
109 scr |= HD64461_PCCSCR_VCC1;
110 outb(scr, HD64461_PCC1SCR);
112 hd64461_stbcr = inw(HD64461_STBCR);
113 hd64461_stbcr |= HD64461_STBCR_SPC1ST;
114 outw(hd64461_stbcr, HD64461_STBCR);
117 __raw_writeb(0x1f, DACR);
119 stbcr = __raw_readb(STBCR);
120 __raw_writeb(0x01, STBCR);
122 stbcr2 = __raw_readb(STBCR2);
123 __raw_writeb(0x7f , STBCR2);
125 outw(0xf07f, HD64461_SCPUCR);
129 outw(0, HD64461_SCPUCR);
130 __raw_writeb(stbcr, STBCR);
131 __raw_writeb(stbcr2, STBCR2);
133 #ifdef CONFIG_HD64461_ENABLER
134 hd64461_stbcr = inw(HD64461_STBCR);
135 hd64461_stbcr &= ~HD64461_STBCR_SPC1ST;
136 outw(hd64461_stbcr, HD64461_STBCR);
138 outb(0x4c, HD64461_PCC1CSCIER);
139 outb(0x00, HD64461_PCC1CSCR);
145 static const struct platform_suspend_ops hp6x0_pm_ops = {
146 .enter = hp6x0_pm_enter,
147 .valid = suspend_valid_only_mem,
150 static int __init hp6x0_pm_init(void)
152 suspend_set_ops(&hp6x0_pm_ops);
156 late_initcall(hp6x0_pm_init);