arch/sh/boards/board-magicpanelr2.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * linux/arch/sh/boards/magicpanel/setup.c
   4  *
   5  *  Copyright (C) 2007  Markus Brunner, Mark Jonas
   6  *
   7  *  Magic Panel Release 2 board setup
   8  */
   9 #include <linux/init.h>
  10 #include <linux/irq.h>
  11 #include <linux/platform_device.h>
  12 #include <linux/delay.h>
  13 #include <linux/gpio.h>
  14 #include <linux/regulator/fixed.h>
  15 #include <linux/regulator/machine.h>
  16 #include <linux/smsc911x.h>
  17 #include <linux/mtd/mtd.h>
  18 #include <linux/mtd/partitions.h>
  19 #include <linux/mtd/physmap.h>
  20 #include <linux/mtd/map.h>
  21 #include <linux/sh_intc.h>
  22 #include <mach/magicpanelr2.h>
  23 #include <asm/heartbeat.h>
  24 #include <cpu/gpio.h>
  25 #include <cpu/sh7720.h>
  26
  27 /* Dummy supplies, where voltage doesn't matter */
  28 static struct regulator_consumer_supply dummy_supplies[] = {
  29         REGULATOR_SUPPLY("vddvario", "smsc911x"),
  30         REGULATOR_SUPPLY("vdd33a", "smsc911x"),
  31 };
  32
  33 #define LAN9115_READY   (__raw_readl(0xA8000084UL) & 0x00000001UL)
  34
  35 /* Wait until reset finished. Timeout is 100ms. */
  36 static int __init ethernet_reset_finished(void)
  37 {
  38         int i;
  39
  40         if (LAN9115_READY)
  41                 return 1;
  42
  43         for (i = 0; i < 10; ++i) {
  44                 mdelay(10);
  45                 if (LAN9115_READY)
  46                         return 1;
  47         }
  48
  49         return 0;
  50 }
  51
  52 static void __init reset_ethernet(void)
  53 {
  54         /* PMDR: LAN_RESET=on */
  55         CLRBITS_OUTB(0x10, PORT_PMDR);
  56
  57         udelay(200);
  58
  59         /* PMDR: LAN_RESET=off */
  60         SETBITS_OUTB(0x10, PORT_PMDR);
  61 }
  62
  63 static void __init setup_chip_select(void)
  64 {
  65         /* CS2: LAN (0x08000000 - 0x0bffffff) */
  66         /* no idle cycles, normal space, 8 bit data bus */
  67         __raw_writel(0x36db0400, CS2BCR);
  68         /* (SW:1.5 WR:3 HW:1.5), ext. wait */
  69         __raw_writel(0x000003c0, CS2WCR);
  70
  71         /* CS4: CAN1 (0xb0000000 - 0xb3ffffff) */
  72         /* no idle cycles, normal space, 8 bit data bus */
  73         __raw_writel(0x00000200, CS4BCR);
  74         /* (SW:1.5 WR:3 HW:1.5), ext. wait */
  75         __raw_writel(0x00100981, CS4WCR);
  76
  77         /* CS5a: CAN2 (0xb4000000 - 0xb5ffffff) */
  78         /* no idle cycles, normal space, 8 bit data bus */
  79         __raw_writel(0x00000200, CS5ABCR);
  80         /* (SW:1.5 WR:3 HW:1.5), ext. wait */
  81         __raw_writel(0x00100981, CS5AWCR);
  82
  83         /* CS5b: CAN3 (0xb6000000 - 0xb7ffffff) */
  84         /* no idle cycles, normal space, 8 bit data bus */
  85         __raw_writel(0x00000200, CS5BBCR);
  86         /* (SW:1.5 WR:3 HW:1.5), ext. wait */
  87         __raw_writel(0x00100981, CS5BWCR);
  88
  89         /* CS6a: Rotary (0xb8000000 - 0xb9ffffff) */
  90         /* no idle cycles, normal space, 8 bit data bus */
  91         __raw_writel(0x00000200, CS6ABCR);
  92         /* (SW:1.5 WR:3 HW:1.5), no ext. wait */
  93         __raw_writel(0x001009C1, CS6AWCR);
  94 }
  95
  96 static void __init setup_port_multiplexing(void)
  97 {
  98         /* A7 GPO(LED8);     A6 GPO(LED7);     A5 GPO(LED6);      A4 GPO(LED5);
  99          * A3 GPO(LED4);     A2 GPO(LED3);     A1 GPO(LED2);      A0 GPO(LED1);
 100          */
 101         __raw_writew(0x5555, PORT_PACR);        /* 01 01 01 01 01 01 01 01 */
 102
 103         /* B7 GPO(RST4);   B6 GPO(RST3);  B5 GPO(RST2);    B4 GPO(RST1);
 104          * B3 GPO(PB3);    B2 GPO(PB2);   B1 GPO(PB1);     B0 GPO(PB0);
 105          */
 106         __raw_writew(0x5555, PORT_PBCR);        /* 01 01 01 01 01 01 01 01 */
 107
 108         /* C7 GPO(PC7);   C6 GPO(PC6);    C5 GPO(PC5);     C4 GPO(PC4);
 109          * C3 LCD_DATA3;  C2 LCD_DATA2;   C1 LCD_DATA1;    C0 LCD_DATA0;
 110          */
 111         __raw_writew(0x5500, PORT_PCCR);        /* 01 01 01 01 00 00 00 00 */
 112
 113         /* D7 GPO(PD7); D6 GPO(PD6);    D5 GPO(PD5);       D4 GPO(PD4);
 114          * D3 GPO(PD3); D2 GPO(PD2);    D1 GPO(PD1);       D0 GPO(PD0);
 115          */
 116         __raw_writew(0x5555, PORT_PDCR);        /* 01 01 01 01 01 01 01 01 */
 117
 118         /* E7 (x);        E6 GPI(nu);    E5 GPI(nu);      E4 LCD_M_DISP;
 119          * E3 LCD_CL1;    E2 LCD_CL2;    E1 LCD_DON;      E0 LCD_FLM;
 120          */
 121         __raw_writew(0x3C00, PORT_PECR);        /* 00 11 11 00 00 00 00 00 */
 122
 123         /* F7 (x);           F6 DA1(VLCD);     F5 DA0(nc);        F4 AN3;
 124          * F3 AN2(MID_AD);   F2 AN1(EARTH_AD); F1 AN0(TEMP);      F0 GPI+(nc);
 125          */
 126         __raw_writew(0x0002, PORT_PFCR);        /* 00 00 00 00 00 00 00 10 */
 127
 128         /* G7 (x);        G6 IRQ5(TOUCH_BUSY); G5 IRQ4(TOUCH_IRQ); G4 GPI(KEY2);
 129          * G3 GPI(KEY1);  G2 GPO(LED11);        G1 GPO(LED10);     G0 GPO(LED9);
 130          */
 131         __raw_writew(0x03D5, PORT_PGCR);        /* 00 00 00 11 11 01 01 01 */
 132
 133         /* H7 (x);            H6 /RAS(BRAS);      H5 /CAS(BCAS); H4 CKE(BCKE);
 134          * H3 GPO(EARTH_OFF); H2 GPO(EARTH_TEST); H1 USB2_PWR;   H0 USB1_PWR;
 135          */
 136         __raw_writew(0x0050, PORT_PHCR);        /* 00 00 00 00 01 01 00 00 */
 137
 138         /* J7 (x);        J6 AUDCK;        J5 ASEBRKAK;     J4 AUDATA3;
 139          * J3 AUDATA2;    J2 AUDATA1;      J1 AUDATA0;      J0 AUDSYNC;
 140          */
 141         __raw_writew(0x0000, PORT_PJCR);        /* 00 00 00 00 00 00 00 00 */
 142
 143         /* K7 (x);          K6 (x);          K5 (x);       K4 (x);
 144          * K3 PINT7(/PWR2); K2 PINT6(/PWR1); K1 PINT5(nu); K0 PINT4(FLASH_READY)
 145          */
 146         __raw_writew(0x00FF, PORT_PKCR);        /* 00 00 00 00 11 11 11 11 */
 147
 148         /* L7 TRST;        L6 TMS;           L5 TDO;              L4 TDI;
 149          * L3 TCK;         L2 (x);           L1 (x);              L0 (x);
 150          */
 151         __raw_writew(0x0000, PORT_PLCR);        /* 00 00 00 00 00 00 00 00 */
 152
 153         /* M7 GPO(CURRENT_SINK);    M6 GPO(PWR_SWITCH);     M5 GPO(LAN_SPEED);
 154          * M4 GPO(LAN_RESET);       M3 GPO(BUZZER);         M2 GPO(LCD_BL);
 155          * M1 CS5B(CAN3_CS);        M0 GPI+(nc);
 156          */
 157         __raw_writew(0x5552, PORT_PMCR);           /* 01 01 01 01 01 01 00 10 */
 158
 159         /* CURRENT_SINK=off,    PWR_SWITCH=off, LAN_SPEED=100MBit,
 160          * LAN_RESET=off,       BUZZER=off,     LCD_BL=off
 161          */
 162 #if CONFIG_SH_MAGIC_PANEL_R2_VERSION == 2
 163         __raw_writeb(0x30, PORT_PMDR);
 164 #elif CONFIG_SH_MAGIC_PANEL_R2_VERSION == 3
 165         __raw_writeb(0xF0, PORT_PMDR);
 166 #else
 167 #error Unknown revision of PLATFORM_MP_R2
 168 #endif
 169
 170         /* P7 (x);             P6 (x);            P5 (x);
 171          * P4 GPO(nu);         P3 IRQ3(LAN_IRQ);  P2 IRQ2(CAN3_IRQ);
 172          * P1 IRQ1(CAN2_IRQ);  P0 IRQ0(CAN1_IRQ)
 173          */
 174         __raw_writew(0x0100, PORT_PPCR);        /* 00 00 00 01 00 00 00 00 */
 175         __raw_writeb(0x10, PORT_PPDR);
 176
 177         /* R7 A25;           R6 A24;         R5 A23;              R4 A22;
 178          * R3 A21;           R2 A20;         R1 A19;              R0 A0;
 179          */
 180         gpio_request(GPIO_FN_A25, NULL);
 181         gpio_request(GPIO_FN_A24, NULL);
 182         gpio_request(GPIO_FN_A23, NULL);
 183         gpio_request(GPIO_FN_A22, NULL);
 184         gpio_request(GPIO_FN_A21, NULL);
 185         gpio_request(GPIO_FN_A20, NULL);
 186         gpio_request(GPIO_FN_A19, NULL);
 187         gpio_request(GPIO_FN_A0, NULL);
 188
 189         /* S7 (x);              S6 (x);        S5 (x);       S4 GPO(EEPROM_CS2);
 190          * S3 GPO(EEPROM_CS1);  S2 SIOF0_TXD;  S1 SIOF0_RXD; S0 SIOF0_SCK;
 191          */
 192         __raw_writew(0x0140, PORT_PSCR);        /* 00 00 00 01 01 00 00 00 */
 193
 194         /* T7 (x);         T6 (x);        T5 (x);         T4 COM1_CTS;
 195          * T3 COM1_RTS;    T2 COM1_TXD;   T1 COM1_RXD;    T0 GPO(WDOG)
 196          */
 197         __raw_writew(0x0001, PORT_PTCR);        /* 00 00 00 00 00 00 00 01 */
 198
 199         /* U7 (x);           U6 (x);       U5 (x);        U4 GPI+(/AC_FAULT);
 200          * U3 GPO(TOUCH_CS); U2 TOUCH_TXD; U1 TOUCH_RXD;  U0 TOUCH_SCK;
 201          */
 202         __raw_writew(0x0240, PORT_PUCR);        /* 00 00 00 10 01 00 00 00 */
 203
 204         /* V7 (x);        V6 (x);       V5 (x);           V4 GPO(MID2);
 205          * V3 GPO(MID1);  V2 CARD_TxD;  V1 CARD_RxD;      V0 GPI+(/BAT_FAULT);
 206          */
 207         __raw_writew(0x0142, PORT_PVCR);        /* 00 00 00 01 01 00 00 10 */
 208 }
 209
 210 static void __init mpr2_setup(char **cmdline_p)
 211 {
 212         /* set Pin Select Register A:
 213          * /PCC_CD1, /PCC_CD2,  PCC_BVD1, PCC_BVD2,
 214          * /IOIS16,  IRQ4,      IRQ5,     USB1d_SUSPEND
 215          */
 216         __raw_writew(0xAABC, PORT_PSELA);
 217         /* set Pin Select Register B:
 218          * /SCIF0_RTS, /SCIF0_CTS, LCD_VCPWC,
 219          * LCD_VEPWC,  IIC_SDA,    IIC_SCL, Reserved
 220          */
 221         __raw_writew(0x3C00, PORT_PSELB);
 222         /* set Pin Select Register C:
 223          * SIOF1_SCK, SIOF1_RxD, SCIF1_RxD, SCIF1_TxD, Reserved
 224          */
 225         __raw_writew(0x0000, PORT_PSELC);
 226         /* set Pin Select Register D: Reserved, SIOF1_TxD, Reserved, SIOF1_MCLK,
 227          * Reserved, SIOF1_SYNC, Reserved, SCIF1_SCK, Reserved
 228          */
 229         __raw_writew(0x0000, PORT_PSELD);
 230         /* set USB TxRx Control: Reserved, DRV, Reserved, USB_TRANS, USB_SEL */
 231         __raw_writew(0x0101, PORT_UTRCTL);
 232         /* set USB Clock Control: USSCS, USSTB, Reserved (HighByte always A5) */
 233         __raw_writew(0xA5C0, PORT_UCLKCR_W);
 234
 235         setup_chip_select();
 236
 237         setup_port_multiplexing();
 238
 239         reset_ethernet();
 240
 241         printk(KERN_INFO "Magic Panel Release 2 A.%i\n",
 242                                 CONFIG_SH_MAGIC_PANEL_R2_VERSION);
 243
 244         if (ethernet_reset_finished() == 0)
 245                 printk(KERN_WARNING "Ethernet not ready\n");
 246 }
 247
 248 static struct resource smsc911x_resources[] = {
 249         [0] = {
 250                 .start          = 0xa8000000,
 251                 .end            = 0xabffffff,
 252                 .flags          = IORESOURCE_MEM,
 253         },
 254         [1] = {
 255                 .start          = evt2irq(0x660),
 256                 .end            = evt2irq(0x660),
 257                 .flags          = IORESOURCE_IRQ,
 258         },
 259 };
 260
 261 static struct smsc911x_platform_config smsc911x_config = {
 262         .phy_interface  = PHY_INTERFACE_MODE_MII,
 263         .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
 264         .irq_type       = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
 265         .flags          = SMSC911X_USE_32BIT,
 266 };
 267
 268 static struct platform_device smsc911x_device = {
 269         .name           = "smsc911x",
 270         .id             = -1,
 271         .num_resources  = ARRAY_SIZE(smsc911x_resources),
 272         .resource       = smsc911x_resources,
 273         .dev = {
 274                 .platform_data = &smsc911x_config,
 275         },
 276 };
 277
 278 static struct resource heartbeat_resources[] = {
 279         [0] = {
 280                 .start  = PA_LED,
 281                 .end    = PA_LED,
 282                 .flags  = IORESOURCE_MEM,
 283         },
 284 };
 285
 286 static struct heartbeat_data heartbeat_data = {
 287         .flags          = HEARTBEAT_INVERTED,
 288 };
 289
 290 static struct platform_device heartbeat_device = {
 291         .name           = "heartbeat",
 292         .id             = -1,
 293         .dev    = {
 294                 .platform_data  = &heartbeat_data,
 295         },
 296         .num_resources  = ARRAY_SIZE(heartbeat_resources),
 297         .resource       = heartbeat_resources,
 298 };
 299
 300 static struct mtd_partition mpr2_partitions[] = {
 301         /* Reserved for bootloader, read-only */
 302         {
 303                 .name = "Bootloader",
 304                 .offset = 0x00000000UL,
 305                 .size = MPR2_MTD_BOOTLOADER_SIZE,
 306                 .mask_flags = MTD_WRITEABLE,
 307         },
 308         /* Reserved for kernel image */
 309         {
 310                 .name = "Kernel",
 311                 .offset = MTDPART_OFS_NXTBLK,
 312                 .size = MPR2_MTD_KERNEL_SIZE,
 313         },
 314         /* Rest is used for Flash FS */
 315         {
 316                 .name = "Flash_FS",
 317                 .offset = MTDPART_OFS_NXTBLK,
 318                 .size = MTDPART_SIZ_FULL,
 319         }
 320 };
 321
 322 static struct physmap_flash_data flash_data = {
 323         .parts          = mpr2_partitions,
 324         .nr_parts       = ARRAY_SIZE(mpr2_partitions),
 325         .width          = 2,
 326 };
 327
 328 static struct resource flash_resource = {
 329         .start          = 0x00000000,
 330         .end            = 0x2000000UL,
 331         .flags          = IORESOURCE_MEM,
 332 };
 333
 334 static struct platform_device flash_device = {
 335         .name           = "physmap-flash",
 336         .id             = -1,
 337         .resource       = &flash_resource,
 338         .num_resources  = 1,
 339         .dev            = {
 340                 .platform_data = &flash_data,
 341         },
 342 };
 343
 344 /*
 345  * Add all resources to the platform_device
 346  */
 347
 348 static struct platform_device *mpr2_devices[] __initdata = {
 349         &heartbeat_device,
 350         &smsc911x_device,
 351         &flash_device,
 352 };
 353
 354
 355 static int __init mpr2_devices_setup(void)
 356 {
 357         regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
 358
 359         return platform_add_devices(mpr2_devices, ARRAY_SIZE(mpr2_devices));
 360 }
 361 device_initcall(mpr2_devices_setup);
 362
 363 /*
 364  * Initialize IRQ setting
 365  */
 366 static void __init init_mpr2_IRQ(void)
 367 {
 368         plat_irq_setup_pins(IRQ_MODE_IRQ); /* install handlers for IRQ0-5 */
 369
 370         irq_set_irq_type(evt2irq(0x600), IRQ_TYPE_LEVEL_LOW);    /* IRQ0 CAN1 */
 371         irq_set_irq_type(evt2irq(0x620), IRQ_TYPE_LEVEL_LOW);    /* IRQ1 CAN2 */
 372         irq_set_irq_type(evt2irq(0x640), IRQ_TYPE_LEVEL_LOW);    /* IRQ2 CAN3 */
 373         irq_set_irq_type(evt2irq(0x660), IRQ_TYPE_LEVEL_LOW);    /* IRQ3 SMSC9115 */
 374         irq_set_irq_type(evt2irq(0x680), IRQ_TYPE_EDGE_RISING);  /* IRQ4 touchscreen */
 375         irq_set_irq_type(evt2irq(0x6a0), IRQ_TYPE_EDGE_FALLING); /* IRQ5 touchscreen */
 376
 377         intc_set_priority(evt2irq(0x600), 13);          /* IRQ0 CAN1 */
 378         intc_set_priority(evt2irq(0x620), 13);          /* IRQ0 CAN2 */
 379         intc_set_priority(evt2irq(0x640), 13);          /* IRQ0 CAN3 */
 380         intc_set_priority(evt2irq(0x660), 6);           /* IRQ3 SMSC9115 */
 381 }
 382
 383 /*
 384  * The Machine Vector
 385  */
 386
 387 static struct sh_machine_vector mv_mpr2 __initmv = {
 388         .mv_name                = "mpr2",
 389         .mv_setup               = mpr2_setup,
 390         .mv_init_irq            = init_mpr2_IRQ,
 391 };