2 * s390 specific pci instructions
4 * Copyright IBM Corp. 2013
7 #include <linux/export.h>
8 #include <linux/errno.h>
9 #include <linux/delay.h>
10 #include <asm/facility.h>
11 #include <asm/pci_insn.h>
12 #include <asm/pci_debug.h>
13 #include <asm/processor.h>
15 #define ZPCI_INSN_BUSY_DELAY 1 /* 1 microsecond */
17 static inline void zpci_err_insn(u8 cc, u8 status, u64 req, u64 offset)
24 } __packed data = {req, offset, cc, status};
26 zpci_err_hex(&data, sizeof(data));
29 /* Modify PCI Function Controls */
30 static inline u8 __mpcifc(u64 req, struct zpci_fib *fib, u8 *status)
35 " .insn rxy,0xe300000000d0,%[req],%[fib]\n"
38 : [cc] "=d" (cc), [req] "+d" (req), [fib] "+Q" (*fib)
40 *status = req >> 24 & 0xff;
44 int zpci_mod_fc(u64 req, struct zpci_fib *fib)
49 cc = __mpcifc(req, fib, &status);
51 msleep(ZPCI_INSN_BUSY_DELAY);
55 zpci_err_insn(cc, status, req, 0);
57 return (cc) ? -EIO : 0;
60 /* Refresh PCI Translations */
61 static inline u8 __rpcit(u64 fn, u64 addr, u64 range, u8 *status)
63 register u64 __addr asm("2") = addr;
64 register u64 __range asm("3") = range;
68 " .insn rre,0xb9d30000,%[fn],%[addr]\n"
71 : [cc] "=d" (cc), [fn] "+d" (fn)
72 : [addr] "d" (__addr), "d" (__range)
74 *status = fn >> 24 & 0xff;
78 int zpci_refresh_trans(u64 fn, u64 addr, u64 range)
83 cc = __rpcit(fn, addr, range, &status);
85 udelay(ZPCI_INSN_BUSY_DELAY);
89 zpci_err_insn(cc, status, addr, range);
91 return (cc) ? -EIO : 0;
94 /* Set Interruption Controls */
95 int zpci_set_irq_ctrl(u16 ctl, char *unused, u8 isc)
97 if (!test_facility(72))
100 " .insn rsy,0xeb00000000d1,%[ctl],%[isc],%[u]\n"
101 : : [ctl] "d" (ctl), [isc] "d" (isc << 27), [u] "Q" (*unused));
106 static inline int __pcilg(u64 *data, u64 req, u64 offset, u8 *status)
108 register u64 __req asm("2") = req;
109 register u64 __offset asm("3") = offset;
114 " .insn rre,0xb9d20000,%[data],%[req]\n"
119 : [cc] "+d" (cc), [data] "=d" (__data), [req] "+d" (__req)
122 *status = __req >> 24 & 0xff;
129 int zpci_load(u64 *data, u64 req, u64 offset)
135 cc = __pcilg(data, req, offset, &status);
137 udelay(ZPCI_INSN_BUSY_DELAY);
141 zpci_err_insn(cc, status, req, offset);
143 return (cc > 0) ? -EIO : cc;
145 EXPORT_SYMBOL_GPL(zpci_load);
148 static inline int __pcistg(u64 data, u64 req, u64 offset, u8 *status)
150 register u64 __req asm("2") = req;
151 register u64 __offset asm("3") = offset;
155 " .insn rre,0xb9d00000,%[data],%[req]\n"
160 : [cc] "+d" (cc), [req] "+d" (__req)
161 : "d" (__offset), [data] "d" (data)
163 *status = __req >> 24 & 0xff;
167 int zpci_store(u64 data, u64 req, u64 offset)
173 cc = __pcistg(data, req, offset, &status);
175 udelay(ZPCI_INSN_BUSY_DELAY);
179 zpci_err_insn(cc, status, req, offset);
181 return (cc > 0) ? -EIO : cc;
183 EXPORT_SYMBOL_GPL(zpci_store);
185 /* PCI Store Block */
186 static inline int __pcistb(const u64 *data, u64 req, u64 offset, u8 *status)
191 " .insn rsy,0xeb00000000d0,%[req],%[offset],%[data]\n"
196 : [cc] "+d" (cc), [req] "+d" (req)
197 : [offset] "d" (offset), [data] "Q" (*data)
199 *status = req >> 24 & 0xff;
203 int zpci_store_block(const u64 *data, u64 req, u64 offset)
209 cc = __pcistb(data, req, offset, &status);
211 udelay(ZPCI_INSN_BUSY_DELAY);
215 zpci_err_insn(cc, status, req, offset);
217 return (cc > 0) ? -EIO : cc;
219 EXPORT_SYMBOL_GPL(zpci_store_block);