1 // SPDX-License-Identifier: GPL-2.0
3 * s390 specific pci instructions
5 * Copyright IBM Corp. 2013
8 #include <linux/export.h>
9 #include <linux/errno.h>
10 #include <linux/delay.h>
11 #include <linux/jump_label.h>
12 #include <asm/asm-extable.h>
13 #include <asm/facility.h>
14 #include <asm/pci_insn.h>
15 #include <asm/pci_debug.h>
16 #include <asm/pci_io.h>
17 #include <asm/processor.h>
19 #define ZPCI_INSN_BUSY_DELAY 1 /* 1 microsecond */
21 struct zpci_err_insn_data {
37 static inline void zpci_err_insn_req(int lvl, u8 insn, u8 cc, u8 status,
40 struct zpci_err_insn_data data = {
41 .insn = insn, .cc = cc, .status = status,
42 .req = req, .offset = offset};
44 zpci_err_hex_level(lvl, &data, sizeof(data));
47 static inline void zpci_err_insn_addr(int lvl, u8 insn, u8 cc, u8 status,
50 struct zpci_err_insn_data data = {
51 .insn = insn, .cc = cc, .status = status,
52 .addr = addr, .len = len};
54 zpci_err_hex_level(lvl, &data, sizeof(data));
57 /* Modify PCI Function Controls */
58 static inline u8 __mpcifc(u64 req, struct zpci_fib *fib, u8 *status)
63 " .insn rxy,0xe300000000d0,%[req],%[fib]\n"
66 : [cc] "=d" (cc), [req] "+d" (req), [fib] "+Q" (*fib)
68 *status = req >> 24 & 0xff;
72 u8 zpci_mod_fc(u64 req, struct zpci_fib *fib, u8 *status)
78 cc = __mpcifc(req, fib, status);
80 msleep(ZPCI_INSN_BUSY_DELAY);
82 zpci_err_insn_req(1, 'M', cc, *status, req, 0);
89 zpci_err_insn_req(0, 'M', cc, *status, req, 0);
91 zpci_err_insn_req(1, 'M', cc, *status, req, 0);
96 /* Refresh PCI Translations */
97 static inline u8 __rpcit(u64 fn, u64 addr, u64 range, u8 *status)
99 union register_pair addr_range = {.even = addr, .odd = range};
103 " .insn rre,0xb9d30000,%[fn],%[addr_range]\n"
106 : [cc] "=d" (cc), [fn] "+d" (fn)
107 : [addr_range] "d" (addr_range.pair)
109 *status = fn >> 24 & 0xff;
113 int zpci_refresh_trans(u64 fn, u64 addr, u64 range)
115 bool retried = false;
119 cc = __rpcit(fn, addr, range, &status);
121 udelay(ZPCI_INSN_BUSY_DELAY);
123 zpci_err_insn_addr(1, 'R', cc, status, addr, range);
130 zpci_err_insn_addr(0, 'R', cc, status, addr, range);
132 zpci_err_insn_addr(1, 'R', cc, status, addr, range);
134 if (cc == 1 && (status == 4 || status == 16))
137 return (cc) ? -EIO : 0;
140 /* Set Interruption Controls */
141 int __zpci_set_irq_ctrl(u16 ctl, u8 isc, union zpci_sic_iib *iib)
143 if (!test_facility(72))
147 ".insn rsy,0xeb00000000d1,%[ctl],%[isc],%[iib]\n"
148 : : [ctl] "d" (ctl), [isc] "d" (isc << 27), [iib] "Q" (*iib));
154 static inline int ____pcilg(u64 *data, u64 req, u64 offset, u8 *status)
156 union register_pair req_off = {.even = req, .odd = offset};
161 " .insn rre,0xb9d20000,%[data],%[req_off]\n"
166 : [cc] "+d" (cc), [data] "=d" (__data),
167 [req_off] "+&d" (req_off.pair) :: "cc");
168 *status = req_off.even >> 24 & 0xff;
173 static inline int __pcilg(u64 *data, u64 req, u64 offset, u8 *status)
178 cc = ____pcilg(&__data, req, offset, status);
185 int __zpci_load(u64 *data, u64 req, u64 offset)
187 bool retried = false;
192 cc = __pcilg(data, req, offset, &status);
194 udelay(ZPCI_INSN_BUSY_DELAY);
196 zpci_err_insn_req(1, 'l', cc, status, req, offset);
203 zpci_err_insn_req(0, 'l', cc, status, req, offset);
205 zpci_err_insn_req(1, 'l', cc, status, req, offset);
207 return (cc > 0) ? -EIO : cc;
209 EXPORT_SYMBOL_GPL(__zpci_load);
211 static inline int zpci_load_fh(u64 *data, const volatile void __iomem *addr,
214 struct zpci_iomap_entry *entry = &zpci_iomap_start[ZPCI_IDX(addr)];
215 u64 req = ZPCI_CREATE_REQ(READ_ONCE(entry->fh), entry->bar, len);
217 return __zpci_load(data, req, ZPCI_OFFSET(addr));
220 static inline int __pcilg_mio(u64 *data, u64 ioaddr, u64 len, u8 *status)
222 union register_pair ioaddr_len = {.even = ioaddr, .odd = len};
227 " .insn rre,0xb9d60000,%[data],%[ioaddr_len]\n"
232 : [cc] "+d" (cc), [data] "=d" (__data),
233 [ioaddr_len] "+&d" (ioaddr_len.pair) :: "cc");
234 *status = ioaddr_len.odd >> 24 & 0xff;
239 int zpci_load(u64 *data, const volatile void __iomem *addr, unsigned long len)
244 if (!static_branch_unlikely(&have_mio))
245 return zpci_load_fh(data, addr, len);
247 cc = __pcilg_mio(data, (__force u64) addr, len, &status);
249 zpci_err_insn_addr(0, 'L', cc, status, (__force u64) addr, len);
251 return (cc > 0) ? -EIO : cc;
253 EXPORT_SYMBOL_GPL(zpci_load);
256 static inline int __pcistg(u64 data, u64 req, u64 offset, u8 *status)
258 union register_pair req_off = {.even = req, .odd = offset};
262 " .insn rre,0xb9d00000,%[data],%[req_off]\n"
267 : [cc] "+d" (cc), [req_off] "+&d" (req_off.pair)
270 *status = req_off.even >> 24 & 0xff;
274 int __zpci_store(u64 data, u64 req, u64 offset)
276 bool retried = false;
281 cc = __pcistg(data, req, offset, &status);
283 udelay(ZPCI_INSN_BUSY_DELAY);
285 zpci_err_insn_req(1, 's', cc, status, req, offset);
292 zpci_err_insn_req(0, 's', cc, status, req, offset);
294 zpci_err_insn_req(1, 's', cc, status, req, offset);
296 return (cc > 0) ? -EIO : cc;
298 EXPORT_SYMBOL_GPL(__zpci_store);
300 static inline int zpci_store_fh(const volatile void __iomem *addr, u64 data,
303 struct zpci_iomap_entry *entry = &zpci_iomap_start[ZPCI_IDX(addr)];
304 u64 req = ZPCI_CREATE_REQ(READ_ONCE(entry->fh), entry->bar, len);
306 return __zpci_store(data, req, ZPCI_OFFSET(addr));
309 static inline int __pcistg_mio(u64 data, u64 ioaddr, u64 len, u8 *status)
311 union register_pair ioaddr_len = {.even = ioaddr, .odd = len};
315 " .insn rre,0xb9d40000,%[data],%[ioaddr_len]\n"
320 : [cc] "+d" (cc), [ioaddr_len] "+&d" (ioaddr_len.pair)
323 *status = ioaddr_len.odd >> 24 & 0xff;
327 int zpci_store(const volatile void __iomem *addr, u64 data, unsigned long len)
332 if (!static_branch_unlikely(&have_mio))
333 return zpci_store_fh(addr, data, len);
335 cc = __pcistg_mio(data, (__force u64) addr, len, &status);
337 zpci_err_insn_addr(0, 'S', cc, status, (__force u64) addr, len);
339 return (cc > 0) ? -EIO : cc;
341 EXPORT_SYMBOL_GPL(zpci_store);
343 /* PCI Store Block */
344 static inline int __pcistb(const u64 *data, u64 req, u64 offset, u8 *status)
349 " .insn rsy,0xeb00000000d0,%[req],%[offset],%[data]\n"
354 : [cc] "+d" (cc), [req] "+d" (req)
355 : [offset] "d" (offset), [data] "Q" (*data)
357 *status = req >> 24 & 0xff;
361 int __zpci_store_block(const u64 *data, u64 req, u64 offset)
363 bool retried = false;
368 cc = __pcistb(data, req, offset, &status);
370 udelay(ZPCI_INSN_BUSY_DELAY);
372 zpci_err_insn_req(0, 'b', cc, status, req, offset);
379 zpci_err_insn_req(0, 'b', cc, status, req, offset);
381 zpci_err_insn_req(1, 'b', cc, status, req, offset);
383 return (cc > 0) ? -EIO : cc;
385 EXPORT_SYMBOL_GPL(__zpci_store_block);
387 static inline int zpci_write_block_fh(volatile void __iomem *dst,
388 const void *src, unsigned long len)
390 struct zpci_iomap_entry *entry = &zpci_iomap_start[ZPCI_IDX(dst)];
391 u64 req = ZPCI_CREATE_REQ(entry->fh, entry->bar, len);
392 u64 offset = ZPCI_OFFSET(dst);
394 return __zpci_store_block(src, req, offset);
397 static inline int __pcistb_mio(const u64 *data, u64 ioaddr, u64 len, u8 *status)
402 " .insn rsy,0xeb00000000d4,%[len],%[ioaddr],%[data]\n"
407 : [cc] "+d" (cc), [len] "+d" (len)
408 : [ioaddr] "d" (ioaddr), [data] "Q" (*data)
410 *status = len >> 24 & 0xff;
414 int zpci_write_block(volatile void __iomem *dst,
415 const void *src, unsigned long len)
420 if (!static_branch_unlikely(&have_mio))
421 return zpci_write_block_fh(dst, src, len);
423 cc = __pcistb_mio(src, (__force u64) dst, len, &status);
425 zpci_err_insn_addr(0, 'B', cc, status, (__force u64) dst, len);
427 return (cc > 0) ? -EIO : cc;
429 EXPORT_SYMBOL_GPL(zpci_write_block);
431 static inline void __pciwb_mio(void)
433 asm volatile (".insn rre,0xb9d50000,0,0\n");
436 void zpci_barrier(void)
438 if (static_branch_likely(&have_mio))
441 EXPORT_SYMBOL_GPL(zpci_barrier);