1 // SPDX-License-Identifier: GPL-2.0
3 * BPF Jit compiler for s390.
5 * Minimum build requirements:
7 * - HAVE_MARCH_Z196_FEATURES: laal, laalg
8 * - HAVE_MARCH_Z10_FEATURES: msfi, cgrj, clgrj
9 * - HAVE_MARCH_Z9_109_FEATURES: alfi, llilf, clfi, oilf, nilf
13 * Copyright IBM Corp. 2012,2015
15 * Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>
16 * Michael Holzheu <holzheu@linux.vnet.ibm.com>
19 #define KMSG_COMPONENT "bpf_jit"
20 #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
22 #include <linux/netdevice.h>
23 #include <linux/filter.h>
24 #include <linux/init.h>
25 #include <linux/bpf.h>
26 #include <asm/cacheflush.h>
28 #include <asm/facility.h>
29 #include <asm/nospec-branch.h>
30 #include <asm/set_memory.h>
34 u32 seen; /* Flags to remember seen eBPF instructions */
35 u32 seen_reg[16]; /* Array to remember which registers are used */
36 u32 *addrs; /* Array with relative instruction addresses */
37 u8 *prg_buf; /* Start of program */
38 int size; /* Size of program and literal pool */
39 int size_prg; /* Size of program */
40 int prg; /* Current position in program */
41 int lit_start; /* Start of literal pool */
42 int lit; /* Current position in literal pool */
43 int base_ip; /* Base address for literal pool */
44 int ret0_ip; /* Address of return 0 */
45 int exit_ip; /* Address of exit */
46 int r1_thunk_ip; /* Address of expoline thunk for 'br %r1' */
47 int r14_thunk_ip; /* Address of expoline thunk for 'br %r14' */
48 int tail_call_start; /* Tail call start offset */
49 int labels[1]; /* Labels for local jumps */
52 #define BPF_SIZE_MAX 0xffff /* Max size for program (16 bit branches) */
54 #define SEEN_SKB 1 /* skb access */
55 #define SEEN_MEM 2 /* use mem[] for temporary storage */
56 #define SEEN_RET0 4 /* ret0_ip points to a valid return 0 */
57 #define SEEN_LITERAL 8 /* code uses literals */
58 #define SEEN_FUNC 16 /* calls C functions */
59 #define SEEN_TAIL_CALL 32 /* code uses tail calls */
60 #define SEEN_REG_AX 64 /* code uses constant blinding */
61 #define SEEN_STACK (SEEN_FUNC | SEEN_MEM | SEEN_SKB)
66 #define REG_W0 (MAX_BPF_JIT_REG + 0) /* Work register 1 (even) */
67 #define REG_W1 (MAX_BPF_JIT_REG + 1) /* Work register 2 (odd) */
68 #define REG_SKB_DATA (MAX_BPF_JIT_REG + 2) /* SKB data register */
69 #define REG_L (MAX_BPF_JIT_REG + 3) /* Literal pool register */
70 #define REG_15 (MAX_BPF_JIT_REG + 4) /* Register 15 */
71 #define REG_0 REG_W0 /* Register 0 */
72 #define REG_1 REG_W1 /* Register 1 */
73 #define REG_2 BPF_REG_1 /* Register 2 */
74 #define REG_14 BPF_REG_0 /* Register 14 */
77 * Mapping of BPF registers to s390 registers
79 static const int reg2hex[] = {
82 /* Function parameters */
88 /* Call saved registers */
93 /* BPF stack pointer */
95 /* Register for blinding (shared with REG_SKB_DATA) */
97 /* SKB data pointer */
99 /* Work registers for s390x backend */
106 static inline u32 reg(u32 dst_reg, u32 src_reg)
108 return reg2hex[dst_reg] << 4 | reg2hex[src_reg];
111 static inline u32 reg_high(u32 reg)
113 return reg2hex[reg] << 4;
116 static inline void reg_set_seen(struct bpf_jit *jit, u32 b1)
118 u32 r1 = reg2hex[b1];
120 if (r1 >= 6 && r1 <= 15 && !jit->seen_reg[r1])
121 jit->seen_reg[r1] = 1;
124 #define REG_SET_SEEN(b1) \
126 reg_set_seen(jit, b1); \
129 #define REG_SEEN(b1) jit->seen_reg[reg2hex[(b1)]]
132 * EMIT macros for code generation
138 *(u16 *) (jit->prg_buf + jit->prg) = op; \
142 #define EMIT2(op, b1, b2) \
144 _EMIT2(op | reg(b1, b2)); \
152 *(u32 *) (jit->prg_buf + jit->prg) = op; \
156 #define EMIT4(op, b1, b2) \
158 _EMIT4(op | reg(b1, b2)); \
163 #define EMIT4_RRF(op, b1, b2, b3) \
165 _EMIT4(op | reg_high(b3) << 8 | reg(b1, b2)); \
171 #define _EMIT4_DISP(op, disp) \
173 unsigned int __disp = (disp) & 0xfff; \
174 _EMIT4(op | __disp); \
177 #define EMIT4_DISP(op, b1, b2, disp) \
179 _EMIT4_DISP(op | reg_high(b1) << 16 | \
180 reg_high(b2) << 8, disp); \
185 #define EMIT4_IMM(op, b1, imm) \
187 unsigned int __imm = (imm) & 0xffff; \
188 _EMIT4(op | reg_high(b1) << 16 | __imm); \
192 #define EMIT4_PCREL(op, pcrel) \
194 long __pcrel = ((pcrel) >> 1) & 0xffff; \
195 _EMIT4(op | __pcrel); \
198 #define _EMIT6(op1, op2) \
200 if (jit->prg_buf) { \
201 *(u32 *) (jit->prg_buf + jit->prg) = op1; \
202 *(u16 *) (jit->prg_buf + jit->prg + 4) = op2; \
207 #define _EMIT6_DISP(op1, op2, disp) \
209 unsigned int __disp = (disp) & 0xfff; \
210 _EMIT6(op1 | __disp, op2); \
213 #define _EMIT6_DISP_LH(op1, op2, disp) \
215 u32 _disp = (u32) disp; \
216 unsigned int __disp_h = _disp & 0xff000; \
217 unsigned int __disp_l = _disp & 0x00fff; \
218 _EMIT6(op1 | __disp_l, op2 | __disp_h >> 4); \
221 #define EMIT6_DISP_LH(op1, op2, b1, b2, b3, disp) \
223 _EMIT6_DISP_LH(op1 | reg(b1, b2) << 16 | \
224 reg_high(b3) << 8, op2, disp); \
230 #define EMIT6_PCREL_LABEL(op1, op2, b1, b2, label, mask) \
232 int rel = (jit->labels[label] - jit->prg) >> 1; \
233 _EMIT6(op1 | reg(b1, b2) << 16 | (rel & 0xffff), \
239 #define EMIT6_PCREL_IMM_LABEL(op1, op2, b1, imm, label, mask) \
241 int rel = (jit->labels[label] - jit->prg) >> 1; \
242 _EMIT6(op1 | (reg_high(b1) | mask) << 16 | \
243 (rel & 0xffff), op2 | (imm & 0xff) << 8); \
245 BUILD_BUG_ON(((unsigned long) imm) > 0xff); \
248 #define EMIT6_PCREL(op1, op2, b1, b2, i, off, mask) \
250 /* Branch instruction needs 6 bytes */ \
251 int rel = (addrs[i + off + 1] - (addrs[i + 1] - 6)) / 2;\
252 _EMIT6(op1 | reg(b1, b2) << 16 | (rel & 0xffff), op2 | mask); \
257 #define EMIT6_PCREL_RILB(op, b, target) \
259 int rel = (target - jit->prg) / 2; \
260 _EMIT6(op | reg_high(b) << 16 | rel >> 16, rel & 0xffff); \
264 #define EMIT6_PCREL_RIL(op, target) \
266 int rel = (target - jit->prg) / 2; \
267 _EMIT6(op | rel >> 16, rel & 0xffff); \
270 #define _EMIT6_IMM(op, imm) \
272 unsigned int __imm = (imm); \
273 _EMIT6(op | (__imm >> 16), __imm & 0xffff); \
276 #define EMIT6_IMM(op, b1, imm) \
278 _EMIT6_IMM(op | reg_high(b1) << 16, imm); \
282 #define EMIT_CONST_U32(val) \
285 ret = jit->lit - jit->base_ip; \
286 jit->seen |= SEEN_LITERAL; \
288 *(u32 *) (jit->prg_buf + jit->lit) = (u32) val; \
293 #define EMIT_CONST_U64(val) \
296 ret = jit->lit - jit->base_ip; \
297 jit->seen |= SEEN_LITERAL; \
299 *(u64 *) (jit->prg_buf + jit->lit) = (u64) val; \
304 #define EMIT_ZERO(b1) \
306 /* llgfr %dst,%dst (zero extend to 64 bit) */ \
307 EMIT4(0xb9160000, b1, b1); \
312 * Fill whole space with illegal instructions
314 static void jit_fill_hole(void *area, unsigned int size)
316 memset(area, 0, size);
320 * Save registers from "rs" (register start) to "re" (register end) on stack
322 static void save_regs(struct bpf_jit *jit, u32 rs, u32 re)
324 u32 off = STK_OFF_R6 + (rs - 6) * 8;
327 /* stg %rs,off(%r15) */
328 _EMIT6(0xe300f000 | rs << 20 | off, 0x0024);
330 /* stmg %rs,%re,off(%r15) */
331 _EMIT6_DISP(0xeb00f000 | rs << 20 | re << 16, 0x0024, off);
335 * Restore registers from "rs" (register start) to "re" (register end) on stack
337 static void restore_regs(struct bpf_jit *jit, u32 rs, u32 re)
339 u32 off = STK_OFF_R6 + (rs - 6) * 8;
341 if (jit->seen & SEEN_STACK)
345 /* lg %rs,off(%r15) */
346 _EMIT6(0xe300f000 | rs << 20 | off, 0x0004);
348 /* lmg %rs,%re,off(%r15) */
349 _EMIT6_DISP(0xeb00f000 | rs << 20 | re << 16, 0x0004, off);
353 * Return first seen register (from start)
355 static int get_start(struct bpf_jit *jit, int start)
359 for (i = start; i <= 15; i++) {
360 if (jit->seen_reg[i])
367 * Return last seen register (from start) (gap >= 2)
369 static int get_end(struct bpf_jit *jit, int start)
373 for (i = start; i < 15; i++) {
374 if (!jit->seen_reg[i] && !jit->seen_reg[i + 1])
377 return jit->seen_reg[15] ? 15 : 14;
381 #define REGS_RESTORE 0
383 * Save and restore clobbered registers (6-15) on stack.
384 * We save/restore registers in chunks with gap >= 2 registers.
386 static void save_restore_regs(struct bpf_jit *jit, int op)
392 rs = get_start(jit, re);
395 re = get_end(jit, rs + 1);
397 save_regs(jit, rs, re);
399 restore_regs(jit, rs, re);
405 * For SKB access %b1 contains the SKB pointer. For "bpf_jit.S"
406 * we store the SKB header length on the stack and the SKB data
407 * pointer in REG_SKB_DATA if BPF_REG_AX is not used.
409 static void emit_load_skb_data_hlen(struct bpf_jit *jit)
411 /* Header length: llgf %w1,<len>(%b1) */
412 EMIT6_DISP_LH(0xe3000000, 0x0016, REG_W1, REG_0, BPF_REG_1,
413 offsetof(struct sk_buff, len));
414 /* s %w1,<data_len>(%b1) */
415 EMIT4_DISP(0x5b000000, REG_W1, BPF_REG_1,
416 offsetof(struct sk_buff, data_len));
417 /* stg %w1,ST_OFF_HLEN(%r0,%r15) */
418 EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W1, REG_0, REG_15, STK_OFF_HLEN);
419 if (!(jit->seen & SEEN_REG_AX))
420 /* lg %skb_data,data_off(%b1) */
421 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_SKB_DATA, REG_0,
422 BPF_REG_1, offsetof(struct sk_buff, data));
426 * Emit function prologue
428 * Save registers and create stack frame if necessary.
429 * See stack frame layout desription in "bpf_jit.h"!
431 static void bpf_jit_prologue(struct bpf_jit *jit)
433 if (jit->seen & SEEN_TAIL_CALL) {
434 /* xc STK_OFF_TCCNT(4,%r15),STK_OFF_TCCNT(%r15) */
435 _EMIT6(0xd703f000 | STK_OFF_TCCNT, 0xf000 | STK_OFF_TCCNT);
437 /* j tail_call_start: NOP if no tail calls are used */
438 EMIT4_PCREL(0xa7f40000, 6);
441 /* Tail calls have to skip above initialization */
442 jit->tail_call_start = jit->prg;
444 save_restore_regs(jit, REGS_SAVE);
445 /* Setup literal pool */
446 if (jit->seen & SEEN_LITERAL) {
448 EMIT2(0x0d00, REG_L, REG_0);
449 jit->base_ip = jit->prg;
451 /* Setup stack and backchain */
452 if (jit->seen & SEEN_STACK) {
453 if (jit->seen & SEEN_FUNC)
454 /* lgr %w1,%r15 (backchain) */
455 EMIT4(0xb9040000, REG_W1, REG_15);
456 /* la %bfp,STK_160_UNUSED(%r15) (BPF frame pointer) */
457 EMIT4_DISP(0x41000000, BPF_REG_FP, REG_15, STK_160_UNUSED);
458 /* aghi %r15,-STK_OFF */
459 EMIT4_IMM(0xa70b0000, REG_15, -STK_OFF);
460 if (jit->seen & SEEN_FUNC)
461 /* stg %w1,152(%r15) (backchain) */
462 EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W1, REG_0,
465 if (jit->seen & SEEN_SKB) {
466 emit_load_skb_data_hlen(jit);
467 /* stg %b1,ST_OFF_SKBP(%r0,%r15) */
468 EMIT6_DISP_LH(0xe3000000, 0x0024, BPF_REG_1, REG_0, REG_15,
476 static void bpf_jit_epilogue(struct bpf_jit *jit)
479 if (jit->seen & SEEN_RET0) {
480 jit->ret0_ip = jit->prg;
482 EMIT4_IMM(0xa7090000, BPF_REG_0, 0);
484 jit->exit_ip = jit->prg;
485 /* Load exit code: lgr %r2,%b0 */
486 EMIT4(0xb9040000, REG_2, BPF_REG_0);
487 /* Restore registers */
488 save_restore_regs(jit, REGS_RESTORE);
489 if (IS_ENABLED(CC_USING_EXPOLINE) && !nospec_disable) {
490 jit->r14_thunk_ip = jit->prg;
491 /* Generate __s390_indirect_jump_r14 thunk */
492 if (test_facility(35)) {
494 EMIT6_PCREL_RIL(0xc6000000, jit->prg + 10);
497 EMIT6_PCREL_RILB(0xc0000000, REG_1, jit->prg + 14);
499 EMIT4_DISP(0x44000000, REG_0, REG_1, 0);
502 EMIT4_PCREL(0xa7f40000, 0);
507 if (IS_ENABLED(CC_USING_EXPOLINE) && !nospec_disable &&
508 (jit->seen & SEEN_FUNC)) {
509 jit->r1_thunk_ip = jit->prg;
510 /* Generate __s390_indirect_jump_r1 thunk */
511 if (test_facility(35)) {
513 EMIT6_PCREL_RIL(0xc6000000, jit->prg + 10);
515 EMIT4_PCREL(0xa7f40000, 0);
519 /* ex 0,S390_lowcore.br_r1_tampoline */
520 EMIT4_DISP(0x44000000, REG_0, REG_0,
521 offsetof(struct lowcore, br_r1_trampoline));
523 EMIT4_PCREL(0xa7f40000, 0);
529 * Compile one eBPF instruction into s390x code
531 * NOTE: Use noinline because for gcov (-fprofile-arcs) gcc allocates a lot of
532 * stack space for the large switch statement.
534 static noinline int bpf_jit_insn(struct bpf_jit *jit, struct bpf_prog *fp, int i)
536 struct bpf_insn *insn = &fp->insnsi[i];
537 int jmp_off, last, insn_count = 1;
538 unsigned int func_addr, mask;
539 u32 dst_reg = insn->dst_reg;
540 u32 src_reg = insn->src_reg;
541 u32 *addrs = jit->addrs;
545 if (dst_reg == BPF_REG_AX || src_reg == BPF_REG_AX)
546 jit->seen |= SEEN_REG_AX;
547 switch (insn->code) {
551 case BPF_ALU | BPF_MOV | BPF_X: /* dst = (u32) src */
552 /* llgfr %dst,%src */
553 EMIT4(0xb9160000, dst_reg, src_reg);
555 case BPF_ALU64 | BPF_MOV | BPF_X: /* dst = src */
557 EMIT4(0xb9040000, dst_reg, src_reg);
559 case BPF_ALU | BPF_MOV | BPF_K: /* dst = (u32) imm */
561 EMIT6_IMM(0xc00f0000, dst_reg, imm);
563 case BPF_ALU64 | BPF_MOV | BPF_K: /* dst = imm */
565 EMIT6_IMM(0xc0010000, dst_reg, imm);
570 case BPF_LD | BPF_IMM | BPF_DW: /* dst = (u64) imm */
572 /* 16 byte instruction that uses two 'struct bpf_insn' */
575 imm64 = (u64)(u32) insn[0].imm | ((u64)(u32) insn[1].imm) << 32;
576 /* lg %dst,<d(imm)>(%l) */
577 EMIT6_DISP_LH(0xe3000000, 0x0004, dst_reg, REG_0, REG_L,
578 EMIT_CONST_U64(imm64));
585 case BPF_ALU | BPF_ADD | BPF_X: /* dst = (u32) dst + (u32) src */
587 EMIT2(0x1a00, dst_reg, src_reg);
590 case BPF_ALU64 | BPF_ADD | BPF_X: /* dst = dst + src */
592 EMIT4(0xb9080000, dst_reg, src_reg);
594 case BPF_ALU | BPF_ADD | BPF_K: /* dst = (u32) dst + (u32) imm */
597 EMIT6_IMM(0xc20b0000, dst_reg, imm);
601 case BPF_ALU64 | BPF_ADD | BPF_K: /* dst = dst + imm */
605 EMIT6_IMM(0xc2080000, dst_reg, imm);
610 case BPF_ALU | BPF_SUB | BPF_X: /* dst = (u32) dst - (u32) src */
612 EMIT2(0x1b00, dst_reg, src_reg);
615 case BPF_ALU64 | BPF_SUB | BPF_X: /* dst = dst - src */
617 EMIT4(0xb9090000, dst_reg, src_reg);
619 case BPF_ALU | BPF_SUB | BPF_K: /* dst = (u32) dst - (u32) imm */
622 EMIT6_IMM(0xc20b0000, dst_reg, -imm);
626 case BPF_ALU64 | BPF_SUB | BPF_K: /* dst = dst - imm */
629 if (imm == -0x80000000) {
630 /* algfi %dst,0x80000000 */
631 EMIT6_IMM(0xc20a0000, dst_reg, 0x80000000);
634 EMIT6_IMM(0xc2080000, dst_reg, -imm);
640 case BPF_ALU | BPF_MUL | BPF_X: /* dst = (u32) dst * (u32) src */
642 EMIT4(0xb2520000, dst_reg, src_reg);
645 case BPF_ALU64 | BPF_MUL | BPF_X: /* dst = dst * src */
647 EMIT4(0xb90c0000, dst_reg, src_reg);
649 case BPF_ALU | BPF_MUL | BPF_K: /* dst = (u32) dst * (u32) imm */
652 EMIT6_IMM(0xc2010000, dst_reg, imm);
656 case BPF_ALU64 | BPF_MUL | BPF_K: /* dst = dst * imm */
660 EMIT6_IMM(0xc2000000, dst_reg, imm);
665 case BPF_ALU | BPF_DIV | BPF_X: /* dst = (u32) dst / (u32) src */
666 case BPF_ALU | BPF_MOD | BPF_X: /* dst = (u32) dst % (u32) src */
668 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
670 jit->seen |= SEEN_RET0;
671 /* ltr %src,%src (if src == 0 goto fail) */
672 EMIT2(0x1200, src_reg, src_reg);
674 EMIT4_PCREL(0xa7840000, jit->ret0_ip - jit->prg);
676 EMIT4_IMM(0xa7080000, REG_W0, 0);
678 EMIT2(0x1800, REG_W1, dst_reg);
680 EMIT4(0xb9970000, REG_W0, src_reg);
682 EMIT4(0xb9160000, dst_reg, rc_reg);
685 case BPF_ALU64 | BPF_DIV | BPF_X: /* dst = dst / src */
686 case BPF_ALU64 | BPF_MOD | BPF_X: /* dst = dst % src */
688 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
690 jit->seen |= SEEN_RET0;
691 /* ltgr %src,%src (if src == 0 goto fail) */
692 EMIT4(0xb9020000, src_reg, src_reg);
694 EMIT4_PCREL(0xa7840000, jit->ret0_ip - jit->prg);
696 EMIT4_IMM(0xa7090000, REG_W0, 0);
698 EMIT4(0xb9040000, REG_W1, dst_reg);
700 EMIT4(0xb9870000, REG_W0, src_reg);
702 EMIT4(0xb9040000, dst_reg, rc_reg);
705 case BPF_ALU | BPF_DIV | BPF_K: /* dst = (u32) dst / (u32) imm */
706 case BPF_ALU | BPF_MOD | BPF_K: /* dst = (u32) dst % (u32) imm */
708 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
711 if (BPF_OP(insn->code) == BPF_MOD)
713 EMIT4_IMM(0xa7090000, dst_reg, 0);
719 EMIT4_IMM(0xa7080000, REG_W0, 0);
721 EMIT2(0x1800, REG_W1, dst_reg);
722 /* dl %w0,<d(imm)>(%l) */
723 EMIT6_DISP_LH(0xe3000000, 0x0097, REG_W0, REG_0, REG_L,
724 EMIT_CONST_U32(imm));
726 EMIT4(0xb9160000, dst_reg, rc_reg);
729 case BPF_ALU64 | BPF_DIV | BPF_K: /* dst = dst / imm */
730 case BPF_ALU64 | BPF_MOD | BPF_K: /* dst = dst % imm */
732 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
735 if (BPF_OP(insn->code) == BPF_MOD)
737 EMIT4_IMM(0xa7090000, dst_reg, 0);
741 EMIT4_IMM(0xa7090000, REG_W0, 0);
743 EMIT4(0xb9040000, REG_W1, dst_reg);
744 /* dlg %w0,<d(imm)>(%l) */
745 EMIT6_DISP_LH(0xe3000000, 0x0087, REG_W0, REG_0, REG_L,
746 EMIT_CONST_U64(imm));
748 EMIT4(0xb9040000, dst_reg, rc_reg);
754 case BPF_ALU | BPF_AND | BPF_X: /* dst = (u32) dst & (u32) src */
756 EMIT2(0x1400, dst_reg, src_reg);
759 case BPF_ALU64 | BPF_AND | BPF_X: /* dst = dst & src */
761 EMIT4(0xb9800000, dst_reg, src_reg);
763 case BPF_ALU | BPF_AND | BPF_K: /* dst = (u32) dst & (u32) imm */
765 EMIT6_IMM(0xc00b0000, dst_reg, imm);
768 case BPF_ALU64 | BPF_AND | BPF_K: /* dst = dst & imm */
769 /* ng %dst,<d(imm)>(%l) */
770 EMIT6_DISP_LH(0xe3000000, 0x0080, dst_reg, REG_0, REG_L,
771 EMIT_CONST_U64(imm));
776 case BPF_ALU | BPF_OR | BPF_X: /* dst = (u32) dst | (u32) src */
778 EMIT2(0x1600, dst_reg, src_reg);
781 case BPF_ALU64 | BPF_OR | BPF_X: /* dst = dst | src */
783 EMIT4(0xb9810000, dst_reg, src_reg);
785 case BPF_ALU | BPF_OR | BPF_K: /* dst = (u32) dst | (u32) imm */
787 EMIT6_IMM(0xc00d0000, dst_reg, imm);
790 case BPF_ALU64 | BPF_OR | BPF_K: /* dst = dst | imm */
791 /* og %dst,<d(imm)>(%l) */
792 EMIT6_DISP_LH(0xe3000000, 0x0081, dst_reg, REG_0, REG_L,
793 EMIT_CONST_U64(imm));
798 case BPF_ALU | BPF_XOR | BPF_X: /* dst = (u32) dst ^ (u32) src */
800 EMIT2(0x1700, dst_reg, src_reg);
803 case BPF_ALU64 | BPF_XOR | BPF_X: /* dst = dst ^ src */
805 EMIT4(0xb9820000, dst_reg, src_reg);
807 case BPF_ALU | BPF_XOR | BPF_K: /* dst = (u32) dst ^ (u32) imm */
810 EMIT6_IMM(0xc0070000, dst_reg, imm);
814 case BPF_ALU64 | BPF_XOR | BPF_K: /* dst = dst ^ imm */
815 /* xg %dst,<d(imm)>(%l) */
816 EMIT6_DISP_LH(0xe3000000, 0x0082, dst_reg, REG_0, REG_L,
817 EMIT_CONST_U64(imm));
822 case BPF_ALU | BPF_LSH | BPF_X: /* dst = (u32) dst << (u32) src */
823 /* sll %dst,0(%src) */
824 EMIT4_DISP(0x89000000, dst_reg, src_reg, 0);
827 case BPF_ALU64 | BPF_LSH | BPF_X: /* dst = dst << src */
828 /* sllg %dst,%dst,0(%src) */
829 EMIT6_DISP_LH(0xeb000000, 0x000d, dst_reg, dst_reg, src_reg, 0);
831 case BPF_ALU | BPF_LSH | BPF_K: /* dst = (u32) dst << (u32) imm */
833 /* sll %dst,imm(%r0) */
834 EMIT4_DISP(0x89000000, dst_reg, REG_0, imm);
838 case BPF_ALU64 | BPF_LSH | BPF_K: /* dst = dst << imm */
841 /* sllg %dst,%dst,imm(%r0) */
842 EMIT6_DISP_LH(0xeb000000, 0x000d, dst_reg, dst_reg, REG_0, imm);
847 case BPF_ALU | BPF_RSH | BPF_X: /* dst = (u32) dst >> (u32) src */
848 /* srl %dst,0(%src) */
849 EMIT4_DISP(0x88000000, dst_reg, src_reg, 0);
852 case BPF_ALU64 | BPF_RSH | BPF_X: /* dst = dst >> src */
853 /* srlg %dst,%dst,0(%src) */
854 EMIT6_DISP_LH(0xeb000000, 0x000c, dst_reg, dst_reg, src_reg, 0);
856 case BPF_ALU | BPF_RSH | BPF_K: /* dst = (u32) dst >> (u32) imm */
858 /* srl %dst,imm(%r0) */
859 EMIT4_DISP(0x88000000, dst_reg, REG_0, imm);
863 case BPF_ALU64 | BPF_RSH | BPF_K: /* dst = dst >> imm */
866 /* srlg %dst,%dst,imm(%r0) */
867 EMIT6_DISP_LH(0xeb000000, 0x000c, dst_reg, dst_reg, REG_0, imm);
872 case BPF_ALU64 | BPF_ARSH | BPF_X: /* ((s64) dst) >>= src */
873 /* srag %dst,%dst,0(%src) */
874 EMIT6_DISP_LH(0xeb000000, 0x000a, dst_reg, dst_reg, src_reg, 0);
876 case BPF_ALU64 | BPF_ARSH | BPF_K: /* ((s64) dst) >>= imm */
879 /* srag %dst,%dst,imm(%r0) */
880 EMIT6_DISP_LH(0xeb000000, 0x000a, dst_reg, dst_reg, REG_0, imm);
885 case BPF_ALU | BPF_NEG: /* dst = (u32) -dst */
887 EMIT2(0x1300, dst_reg, dst_reg);
890 case BPF_ALU64 | BPF_NEG: /* dst = -dst */
892 EMIT4(0xb9030000, dst_reg, dst_reg);
897 case BPF_ALU | BPF_END | BPF_FROM_BE:
898 /* s390 is big endian, therefore only clear high order bytes */
900 case 16: /* dst = (u16) cpu_to_be16(dst) */
901 /* llghr %dst,%dst */
902 EMIT4(0xb9850000, dst_reg, dst_reg);
904 case 32: /* dst = (u32) cpu_to_be32(dst) */
905 /* llgfr %dst,%dst */
906 EMIT4(0xb9160000, dst_reg, dst_reg);
908 case 64: /* dst = (u64) cpu_to_be64(dst) */
912 case BPF_ALU | BPF_END | BPF_FROM_LE:
914 case 16: /* dst = (u16) cpu_to_le16(dst) */
916 EMIT4(0xb91f0000, dst_reg, dst_reg);
917 /* srl %dst,16(%r0) */
918 EMIT4_DISP(0x88000000, dst_reg, REG_0, 16);
919 /* llghr %dst,%dst */
920 EMIT4(0xb9850000, dst_reg, dst_reg);
922 case 32: /* dst = (u32) cpu_to_le32(dst) */
924 EMIT4(0xb91f0000, dst_reg, dst_reg);
925 /* llgfr %dst,%dst */
926 EMIT4(0xb9160000, dst_reg, dst_reg);
928 case 64: /* dst = (u64) cpu_to_le64(dst) */
929 /* lrvgr %dst,%dst */
930 EMIT4(0xb90f0000, dst_reg, dst_reg);
937 case BPF_STX | BPF_MEM | BPF_B: /* *(u8 *)(dst + off) = src_reg */
938 /* stcy %src,off(%dst) */
939 EMIT6_DISP_LH(0xe3000000, 0x0072, src_reg, dst_reg, REG_0, off);
940 jit->seen |= SEEN_MEM;
942 case BPF_STX | BPF_MEM | BPF_H: /* (u16 *)(dst + off) = src */
943 /* sthy %src,off(%dst) */
944 EMIT6_DISP_LH(0xe3000000, 0x0070, src_reg, dst_reg, REG_0, off);
945 jit->seen |= SEEN_MEM;
947 case BPF_STX | BPF_MEM | BPF_W: /* *(u32 *)(dst + off) = src */
948 /* sty %src,off(%dst) */
949 EMIT6_DISP_LH(0xe3000000, 0x0050, src_reg, dst_reg, REG_0, off);
950 jit->seen |= SEEN_MEM;
952 case BPF_STX | BPF_MEM | BPF_DW: /* (u64 *)(dst + off) = src */
953 /* stg %src,off(%dst) */
954 EMIT6_DISP_LH(0xe3000000, 0x0024, src_reg, dst_reg, REG_0, off);
955 jit->seen |= SEEN_MEM;
957 case BPF_ST | BPF_MEM | BPF_B: /* *(u8 *)(dst + off) = imm */
959 EMIT4_IMM(0xa7080000, REG_W0, (u8) imm);
960 /* stcy %w0,off(dst) */
961 EMIT6_DISP_LH(0xe3000000, 0x0072, REG_W0, dst_reg, REG_0, off);
962 jit->seen |= SEEN_MEM;
964 case BPF_ST | BPF_MEM | BPF_H: /* (u16 *)(dst + off) = imm */
966 EMIT4_IMM(0xa7080000, REG_W0, (u16) imm);
967 /* sthy %w0,off(dst) */
968 EMIT6_DISP_LH(0xe3000000, 0x0070, REG_W0, dst_reg, REG_0, off);
969 jit->seen |= SEEN_MEM;
971 case BPF_ST | BPF_MEM | BPF_W: /* *(u32 *)(dst + off) = imm */
973 EMIT6_IMM(0xc00f0000, REG_W0, (u32) imm);
974 /* sty %w0,off(%dst) */
975 EMIT6_DISP_LH(0xe3000000, 0x0050, REG_W0, dst_reg, REG_0, off);
976 jit->seen |= SEEN_MEM;
978 case BPF_ST | BPF_MEM | BPF_DW: /* *(u64 *)(dst + off) = imm */
980 EMIT6_IMM(0xc0010000, REG_W0, imm);
981 /* stg %w0,off(%dst) */
982 EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W0, dst_reg, REG_0, off);
983 jit->seen |= SEEN_MEM;
986 * BPF_STX XADD (atomic_add)
988 case BPF_STX | BPF_XADD | BPF_W: /* *(u32 *)(dst + off) += src */
989 /* laal %w0,%src,off(%dst) */
990 EMIT6_DISP_LH(0xeb000000, 0x00fa, REG_W0, src_reg,
992 jit->seen |= SEEN_MEM;
994 case BPF_STX | BPF_XADD | BPF_DW: /* *(u64 *)(dst + off) += src */
995 /* laalg %w0,%src,off(%dst) */
996 EMIT6_DISP_LH(0xeb000000, 0x00ea, REG_W0, src_reg,
998 jit->seen |= SEEN_MEM;
1003 case BPF_LDX | BPF_MEM | BPF_B: /* dst = *(u8 *)(ul) (src + off) */
1004 /* llgc %dst,0(off,%src) */
1005 EMIT6_DISP_LH(0xe3000000, 0x0090, dst_reg, src_reg, REG_0, off);
1006 jit->seen |= SEEN_MEM;
1008 case BPF_LDX | BPF_MEM | BPF_H: /* dst = *(u16 *)(ul) (src + off) */
1009 /* llgh %dst,0(off,%src) */
1010 EMIT6_DISP_LH(0xe3000000, 0x0091, dst_reg, src_reg, REG_0, off);
1011 jit->seen |= SEEN_MEM;
1013 case BPF_LDX | BPF_MEM | BPF_W: /* dst = *(u32 *)(ul) (src + off) */
1014 /* llgf %dst,off(%src) */
1015 jit->seen |= SEEN_MEM;
1016 EMIT6_DISP_LH(0xe3000000, 0x0016, dst_reg, src_reg, REG_0, off);
1018 case BPF_LDX | BPF_MEM | BPF_DW: /* dst = *(u64 *)(ul) (src + off) */
1019 /* lg %dst,0(off,%src) */
1020 jit->seen |= SEEN_MEM;
1021 EMIT6_DISP_LH(0xe3000000, 0x0004, dst_reg, src_reg, REG_0, off);
1026 case BPF_JMP | BPF_CALL:
1029 * b0 = (__bpf_call_base + imm)(b1, b2, b3, b4, b5)
1031 const u64 func = (u64)__bpf_call_base + imm;
1033 REG_SET_SEEN(BPF_REG_5);
1034 jit->seen |= SEEN_FUNC;
1035 /* lg %w1,<d(imm)>(%l) */
1036 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_W1, REG_0, REG_L,
1037 EMIT_CONST_U64(func));
1038 if (IS_ENABLED(CC_USING_EXPOLINE) && !nospec_disable) {
1039 /* brasl %r14,__s390_indirect_jump_r1 */
1040 EMIT6_PCREL_RILB(0xc0050000, REG_14, jit->r1_thunk_ip);
1043 EMIT2(0x0d00, REG_14, REG_W1);
1045 /* lgr %b0,%r2: load return value into %b0 */
1046 EMIT4(0xb9040000, BPF_REG_0, REG_2);
1047 if ((jit->seen & SEEN_SKB) &&
1048 bpf_helper_changes_pkt_data((void *)func)) {
1049 /* lg %b1,ST_OFF_SKBP(%r15) */
1050 EMIT6_DISP_LH(0xe3000000, 0x0004, BPF_REG_1, REG_0,
1051 REG_15, STK_OFF_SKBP);
1052 emit_load_skb_data_hlen(jit);
1056 case BPF_JMP | BPF_TAIL_CALL:
1059 * B1: pointer to ctx
1060 * B2: pointer to bpf_array
1061 * B3: index in bpf_array
1063 jit->seen |= SEEN_TAIL_CALL;
1066 * if (index >= array->map.max_entries)
1070 /* llgf %w1,map.max_entries(%b2) */
1071 EMIT6_DISP_LH(0xe3000000, 0x0016, REG_W1, REG_0, BPF_REG_2,
1072 offsetof(struct bpf_array, map.max_entries));
1073 /* clrj %b3,%w1,0xa,label0: if (u32)%b3 >= (u32)%w1 goto out */
1074 EMIT6_PCREL_LABEL(0xec000000, 0x0077, BPF_REG_3,
1078 * if (tail_call_cnt++ > MAX_TAIL_CALL_CNT)
1082 if (jit->seen & SEEN_STACK)
1083 off = STK_OFF_TCCNT + STK_OFF;
1085 off = STK_OFF_TCCNT;
1087 EMIT4_IMM(0xa7080000, REG_W0, 1);
1088 /* laal %w1,%w0,off(%r15) */
1089 EMIT6_DISP_LH(0xeb000000, 0x00fa, REG_W1, REG_W0, REG_15, off);
1090 /* clij %w1,MAX_TAIL_CALL_CNT,0x2,label0 */
1091 EMIT6_PCREL_IMM_LABEL(0xec000000, 0x007f, REG_W1,
1092 MAX_TAIL_CALL_CNT, 0, 0x2);
1095 * prog = array->ptrs[index];
1100 /* llgfr %r1,%b3: %r1 = (u32) index */
1101 EMIT4(0xb9160000, REG_1, BPF_REG_3);
1102 /* sllg %r1,%r1,3: %r1 *= 8 */
1103 EMIT6_DISP_LH(0xeb000000, 0x000d, REG_1, REG_1, REG_0, 3);
1104 /* lg %r1,prog(%b2,%r1) */
1105 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_1, BPF_REG_2,
1106 REG_1, offsetof(struct bpf_array, ptrs));
1107 /* clgij %r1,0,0x8,label0 */
1108 EMIT6_PCREL_IMM_LABEL(0xec000000, 0x007d, REG_1, 0, 0, 0x8);
1111 * Restore registers before calling function
1113 save_restore_regs(jit, REGS_RESTORE);
1116 * goto *(prog->bpf_func + tail_call_start);
1119 /* lg %r1,bpf_func(%r1) */
1120 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_1, REG_1, REG_0,
1121 offsetof(struct bpf_prog, bpf_func));
1122 /* bc 0xf,tail_call_start(%r1) */
1123 _EMIT4(0x47f01000 + jit->tail_call_start);
1125 jit->labels[0] = jit->prg;
1127 case BPF_JMP | BPF_EXIT: /* return b0 */
1128 last = (i == fp->len - 1) ? 1 : 0;
1129 if (last && !(jit->seen & SEEN_RET0))
1132 EMIT4_PCREL(0xa7f40000, jit->exit_ip - jit->prg);
1135 * Branch relative (number of skipped instructions) to offset on
1138 * Condition code to mask mapping:
1140 * CC | Description | Mask
1141 * ------------------------------
1142 * 0 | Operands equal | 8
1143 * 1 | First operand low | 4
1144 * 2 | First operand high | 2
1147 * For s390x relative branches: ip = ip + off_bytes
1148 * For BPF relative branches: insn = insn + off_insns + 1
1150 * For example for s390x with offset 0 we jump to the branch
1151 * instruction itself (loop) and for BPF with offset 0 we
1152 * branch to the instruction behind the branch.
1154 case BPF_JMP | BPF_JA: /* if (true) */
1155 mask = 0xf000; /* j */
1157 case BPF_JMP | BPF_JSGT | BPF_K: /* ((s64) dst > (s64) imm) */
1158 mask = 0x2000; /* jh */
1160 case BPF_JMP | BPF_JSLT | BPF_K: /* ((s64) dst < (s64) imm) */
1161 mask = 0x4000; /* jl */
1163 case BPF_JMP | BPF_JSGE | BPF_K: /* ((s64) dst >= (s64) imm) */
1164 mask = 0xa000; /* jhe */
1166 case BPF_JMP | BPF_JSLE | BPF_K: /* ((s64) dst <= (s64) imm) */
1167 mask = 0xc000; /* jle */
1169 case BPF_JMP | BPF_JGT | BPF_K: /* (dst_reg > imm) */
1170 mask = 0x2000; /* jh */
1172 case BPF_JMP | BPF_JLT | BPF_K: /* (dst_reg < imm) */
1173 mask = 0x4000; /* jl */
1175 case BPF_JMP | BPF_JGE | BPF_K: /* (dst_reg >= imm) */
1176 mask = 0xa000; /* jhe */
1178 case BPF_JMP | BPF_JLE | BPF_K: /* (dst_reg <= imm) */
1179 mask = 0xc000; /* jle */
1181 case BPF_JMP | BPF_JNE | BPF_K: /* (dst_reg != imm) */
1182 mask = 0x7000; /* jne */
1184 case BPF_JMP | BPF_JEQ | BPF_K: /* (dst_reg == imm) */
1185 mask = 0x8000; /* je */
1187 case BPF_JMP | BPF_JSET | BPF_K: /* (dst_reg & imm) */
1188 mask = 0x7000; /* jnz */
1189 /* lgfi %w1,imm (load sign extend imm) */
1190 EMIT6_IMM(0xc0010000, REG_W1, imm);
1192 EMIT4(0xb9800000, REG_W1, dst_reg);
1195 case BPF_JMP | BPF_JSGT | BPF_X: /* ((s64) dst > (s64) src) */
1196 mask = 0x2000; /* jh */
1198 case BPF_JMP | BPF_JSLT | BPF_X: /* ((s64) dst < (s64) src) */
1199 mask = 0x4000; /* jl */
1201 case BPF_JMP | BPF_JSGE | BPF_X: /* ((s64) dst >= (s64) src) */
1202 mask = 0xa000; /* jhe */
1204 case BPF_JMP | BPF_JSLE | BPF_X: /* ((s64) dst <= (s64) src) */
1205 mask = 0xc000; /* jle */
1207 case BPF_JMP | BPF_JGT | BPF_X: /* (dst > src) */
1208 mask = 0x2000; /* jh */
1210 case BPF_JMP | BPF_JLT | BPF_X: /* (dst < src) */
1211 mask = 0x4000; /* jl */
1213 case BPF_JMP | BPF_JGE | BPF_X: /* (dst >= src) */
1214 mask = 0xa000; /* jhe */
1216 case BPF_JMP | BPF_JLE | BPF_X: /* (dst <= src) */
1217 mask = 0xc000; /* jle */
1219 case BPF_JMP | BPF_JNE | BPF_X: /* (dst != src) */
1220 mask = 0x7000; /* jne */
1222 case BPF_JMP | BPF_JEQ | BPF_X: /* (dst == src) */
1223 mask = 0x8000; /* je */
1225 case BPF_JMP | BPF_JSET | BPF_X: /* (dst & src) */
1226 mask = 0x7000; /* jnz */
1227 /* ngrk %w1,%dst,%src */
1228 EMIT4_RRF(0xb9e40000, REG_W1, dst_reg, src_reg);
1231 /* lgfi %w1,imm (load sign extend imm) */
1232 EMIT6_IMM(0xc0010000, REG_W1, imm);
1233 /* cgrj %dst,%w1,mask,off */
1234 EMIT6_PCREL(0xec000000, 0x0064, dst_reg, REG_W1, i, off, mask);
1237 /* lgfi %w1,imm (load sign extend imm) */
1238 EMIT6_IMM(0xc0010000, REG_W1, imm);
1239 /* clgrj %dst,%w1,mask,off */
1240 EMIT6_PCREL(0xec000000, 0x0065, dst_reg, REG_W1, i, off, mask);
1243 /* cgrj %dst,%src,mask,off */
1244 EMIT6_PCREL(0xec000000, 0x0064, dst_reg, src_reg, i, off, mask);
1247 /* clgrj %dst,%src,mask,off */
1248 EMIT6_PCREL(0xec000000, 0x0065, dst_reg, src_reg, i, off, mask);
1251 /* brc mask,jmp_off (branch instruction needs 4 bytes) */
1252 jmp_off = addrs[i + off + 1] - (addrs[i + 1] - 4);
1253 EMIT4_PCREL(0xa7040000 | mask << 8, jmp_off);
1258 case BPF_LD | BPF_ABS | BPF_B: /* b0 = *(u8 *) (skb->data+imm) */
1259 case BPF_LD | BPF_IND | BPF_B: /* b0 = *(u8 *) (skb->data+imm+src) */
1260 if ((BPF_MODE(insn->code) == BPF_ABS) && (imm >= 0))
1261 func_addr = __pa(sk_load_byte_pos);
1263 func_addr = __pa(sk_load_byte);
1265 case BPF_LD | BPF_ABS | BPF_H: /* b0 = *(u16 *) (skb->data+imm) */
1266 case BPF_LD | BPF_IND | BPF_H: /* b0 = *(u16 *) (skb->data+imm+src) */
1267 if ((BPF_MODE(insn->code) == BPF_ABS) && (imm >= 0))
1268 func_addr = __pa(sk_load_half_pos);
1270 func_addr = __pa(sk_load_half);
1272 case BPF_LD | BPF_ABS | BPF_W: /* b0 = *(u32 *) (skb->data+imm) */
1273 case BPF_LD | BPF_IND | BPF_W: /* b0 = *(u32 *) (skb->data+imm+src) */
1274 if ((BPF_MODE(insn->code) == BPF_ABS) && (imm >= 0))
1275 func_addr = __pa(sk_load_word_pos);
1277 func_addr = __pa(sk_load_word);
1280 jit->seen |= SEEN_SKB | SEEN_RET0 | SEEN_FUNC;
1281 REG_SET_SEEN(REG_14); /* Return address of possible func call */
1285 * BPF_REG_6 (R7) : skb pointer
1286 * REG_SKB_DATA (R12): skb data pointer (if no BPF_REG_AX)
1289 * BPF_REG_2 (R3) : offset of byte(s) to fetch in skb
1290 * BPF_REG_5 (R6) : return address
1293 * BPF_REG_0 (R14): data read from skb
1295 * Scratch registers (BPF_REG_1-5)
1298 /* Call function: llilf %w1,func_addr */
1299 EMIT6_IMM(0xc00f0000, REG_W1, func_addr);
1301 /* Offset: lgfi %b2,imm */
1302 EMIT6_IMM(0xc0010000, BPF_REG_2, imm);
1303 if (BPF_MODE(insn->code) == BPF_IND)
1304 /* agfr %b2,%src (%src is s32 here) */
1305 EMIT4(0xb9180000, BPF_REG_2, src_reg);
1307 /* Reload REG_SKB_DATA if BPF_REG_AX is used */
1308 if (jit->seen & SEEN_REG_AX)
1309 /* lg %skb_data,data_off(%b6) */
1310 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_SKB_DATA, REG_0,
1311 BPF_REG_6, offsetof(struct sk_buff, data));
1312 /* basr %b5,%w1 (%b5 is call saved) */
1313 EMIT2(0x0d00, BPF_REG_5, REG_W1);
1316 * Note: For fast access we jump directly after the
1317 * jnz instruction from bpf_jit.S
1320 EMIT4_PCREL(0xa7740000, jit->ret0_ip - jit->prg);
1322 default: /* too complex, give up */
1323 pr_err("Unknown opcode %02x\n", insn->code);
1330 * Compile eBPF program into s390x code
1332 static int bpf_jit_prog(struct bpf_jit *jit, struct bpf_prog *fp)
1336 jit->lit = jit->lit_start;
1339 bpf_jit_prologue(jit);
1340 for (i = 0; i < fp->len; i += insn_count) {
1341 insn_count = bpf_jit_insn(jit, fp, i);
1344 /* Next instruction address */
1345 jit->addrs[i + insn_count] = jit->prg;
1347 bpf_jit_epilogue(jit);
1349 jit->lit_start = jit->prg;
1350 jit->size = jit->lit;
1351 jit->size_prg = jit->prg;
1356 * Compile eBPF program "fp"
1358 struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *fp)
1360 struct bpf_prog *tmp, *orig_fp = fp;
1361 struct bpf_binary_header *header;
1362 bool tmp_blinded = false;
1366 if (!bpf_jit_enable)
1369 tmp = bpf_jit_blind_constants(fp);
1371 * If blinding was requested and we failed during blinding,
1372 * we must fall back to the interpreter.
1381 memset(&jit, 0, sizeof(jit));
1382 jit.addrs = kcalloc(fp->len + 1, sizeof(*jit.addrs), GFP_KERNEL);
1383 if (jit.addrs == NULL) {
1388 * Three initial passes:
1389 * - 1/2: Determine clobbered registers
1390 * - 3: Calculate program size and addrs arrray
1392 for (pass = 1; pass <= 3; pass++) {
1393 if (bpf_jit_prog(&jit, fp)) {
1399 * Final pass: Allocate and generate program
1401 if (jit.size >= BPF_SIZE_MAX) {
1405 header = bpf_jit_binary_alloc(jit.size, &jit.prg_buf, 2, jit_fill_hole);
1410 if (bpf_jit_prog(&jit, fp)) {
1411 bpf_jit_binary_free(header);
1415 if (bpf_jit_enable > 1) {
1416 bpf_jit_dump(fp->len, jit.size, pass, jit.prg_buf);
1417 print_fn_code(jit.prg_buf, jit.size_prg);
1419 bpf_jit_binary_lock_ro(header);
1420 fp->bpf_func = (void *) jit.prg_buf;
1422 fp->jited_len = jit.size;
1427 bpf_jit_prog_release_other(fp, fp == orig_fp ?