2 * BPF Jit compiler for s390.
4 * Minimum build requirements:
6 * - HAVE_MARCH_Z196_FEATURES: laal, laalg
7 * - HAVE_MARCH_Z10_FEATURES: msfi, cgrj, clgrj
8 * - HAVE_MARCH_Z9_109_FEATURES: alfi, llilf, clfi, oilf, nilf
12 * Copyright IBM Corp. 2012,2015
14 * Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>
15 * Michael Holzheu <holzheu@linux.vnet.ibm.com>
18 #define KMSG_COMPONENT "bpf_jit"
19 #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
21 #include <linux/netdevice.h>
22 #include <linux/filter.h>
23 #include <linux/init.h>
24 #include <linux/bpf.h>
25 #include <asm/cacheflush.h>
27 #include <asm/facility.h>
28 #include <asm/nospec-branch.h>
31 int bpf_jit_enable __read_mostly;
34 u32 seen; /* Flags to remember seen eBPF instructions */
35 u32 seen_reg[16]; /* Array to remember which registers are used */
36 u32 *addrs; /* Array with relative instruction addresses */
37 u8 *prg_buf; /* Start of program */
38 int size; /* Size of program and literal pool */
39 int size_prg; /* Size of program */
40 int prg; /* Current position in program */
41 int lit_start; /* Start of literal pool */
42 int lit; /* Current position in literal pool */
43 int base_ip; /* Base address for literal pool */
44 int ret0_ip; /* Address of return 0 */
45 int exit_ip; /* Address of exit */
46 int r1_thunk_ip; /* Address of expoline thunk for 'br %r1' */
47 int r14_thunk_ip; /* Address of expoline thunk for 'br %r14' */
48 int tail_call_start; /* Tail call start offset */
49 int labels[1]; /* Labels for local jumps */
52 #define BPF_SIZE_MAX 0xffff /* Max size for program (16 bit branches) */
54 #define SEEN_SKB 1 /* skb access */
55 #define SEEN_MEM 2 /* use mem[] for temporary storage */
56 #define SEEN_RET0 4 /* ret0_ip points to a valid return 0 */
57 #define SEEN_LITERAL 8 /* code uses literals */
58 #define SEEN_FUNC 16 /* calls C functions */
59 #define SEEN_TAIL_CALL 32 /* code uses tail calls */
60 #define SEEN_SKB_CHANGE 64 /* code changes skb data */
61 #define SEEN_STACK (SEEN_FUNC | SEEN_MEM | SEEN_SKB)
66 #define REG_W0 (__MAX_BPF_REG+0) /* Work register 1 (even) */
67 #define REG_W1 (__MAX_BPF_REG+1) /* Work register 2 (odd) */
68 #define REG_SKB_DATA (__MAX_BPF_REG+2) /* SKB data register */
69 #define REG_L (__MAX_BPF_REG+3) /* Literal pool register */
70 #define REG_15 (__MAX_BPF_REG+4) /* Register 15 */
71 #define REG_0 REG_W0 /* Register 0 */
72 #define REG_1 REG_W1 /* Register 1 */
73 #define REG_2 BPF_REG_1 /* Register 2 */
74 #define REG_14 BPF_REG_0 /* Register 14 */
77 * Mapping of BPF registers to s390 registers
79 static const int reg2hex[] = {
82 /* Function parameters */
88 /* Call saved registers */
93 /* BPF stack pointer */
95 /* SKB data pointer */
97 /* Work registers for s390x backend */
104 static inline u32 reg(u32 dst_reg, u32 src_reg)
106 return reg2hex[dst_reg] << 4 | reg2hex[src_reg];
109 static inline u32 reg_high(u32 reg)
111 return reg2hex[reg] << 4;
114 static inline void reg_set_seen(struct bpf_jit *jit, u32 b1)
116 u32 r1 = reg2hex[b1];
118 if (r1 >= 6 && r1 <= 15 && !jit->seen_reg[r1])
119 jit->seen_reg[r1] = 1;
122 #define REG_SET_SEEN(b1) \
124 reg_set_seen(jit, b1); \
127 #define REG_SEEN(b1) jit->seen_reg[reg2hex[(b1)]]
130 * EMIT macros for code generation
136 *(u16 *) (jit->prg_buf + jit->prg) = op; \
140 #define EMIT2(op, b1, b2) \
142 _EMIT2(op | reg(b1, b2)); \
150 *(u32 *) (jit->prg_buf + jit->prg) = op; \
154 #define EMIT4(op, b1, b2) \
156 _EMIT4(op | reg(b1, b2)); \
161 #define EMIT4_RRF(op, b1, b2, b3) \
163 _EMIT4(op | reg_high(b3) << 8 | reg(b1, b2)); \
169 #define _EMIT4_DISP(op, disp) \
171 unsigned int __disp = (disp) & 0xfff; \
172 _EMIT4(op | __disp); \
175 #define EMIT4_DISP(op, b1, b2, disp) \
177 _EMIT4_DISP(op | reg_high(b1) << 16 | \
178 reg_high(b2) << 8, disp); \
183 #define EMIT4_IMM(op, b1, imm) \
185 unsigned int __imm = (imm) & 0xffff; \
186 _EMIT4(op | reg_high(b1) << 16 | __imm); \
190 #define EMIT4_PCREL(op, pcrel) \
192 long __pcrel = ((pcrel) >> 1) & 0xffff; \
193 _EMIT4(op | __pcrel); \
196 #define _EMIT6(op1, op2) \
198 if (jit->prg_buf) { \
199 *(u32 *) (jit->prg_buf + jit->prg) = op1; \
200 *(u16 *) (jit->prg_buf + jit->prg + 4) = op2; \
205 #define _EMIT6_DISP(op1, op2, disp) \
207 unsigned int __disp = (disp) & 0xfff; \
208 _EMIT6(op1 | __disp, op2); \
211 #define _EMIT6_DISP_LH(op1, op2, disp) \
213 u32 _disp = (u32) disp; \
214 unsigned int __disp_h = _disp & 0xff000; \
215 unsigned int __disp_l = _disp & 0x00fff; \
216 _EMIT6(op1 | __disp_l, op2 | __disp_h >> 4); \
219 #define EMIT6_DISP_LH(op1, op2, b1, b2, b3, disp) \
221 _EMIT6_DISP_LH(op1 | reg(b1, b2) << 16 | \
222 reg_high(b3) << 8, op2, disp); \
228 #define EMIT6_PCREL_LABEL(op1, op2, b1, b2, label, mask) \
230 int rel = (jit->labels[label] - jit->prg) >> 1; \
231 _EMIT6(op1 | reg(b1, b2) << 16 | (rel & 0xffff), \
237 #define EMIT6_PCREL_IMM_LABEL(op1, op2, b1, imm, label, mask) \
239 int rel = (jit->labels[label] - jit->prg) >> 1; \
240 _EMIT6(op1 | (reg_high(b1) | mask) << 16 | \
241 (rel & 0xffff), op2 | (imm & 0xff) << 8); \
243 BUILD_BUG_ON(((unsigned long) imm) > 0xff); \
246 #define EMIT6_PCREL(op1, op2, b1, b2, i, off, mask) \
248 /* Branch instruction needs 6 bytes */ \
249 int rel = (addrs[i + off + 1] - (addrs[i + 1] - 6)) / 2;\
250 _EMIT6(op1 | reg(b1, b2) << 16 | (rel & 0xffff), op2 | mask); \
255 #define EMIT6_PCREL_RILB(op, b, target) \
257 int rel = (target - jit->prg) / 2; \
258 _EMIT6(op | reg_high(b) << 16 | rel >> 16, rel & 0xffff); \
262 #define EMIT6_PCREL_RIL(op, target) \
264 int rel = (target - jit->prg) / 2; \
265 _EMIT6(op | rel >> 16, rel & 0xffff); \
268 #define _EMIT6_IMM(op, imm) \
270 unsigned int __imm = (imm); \
271 _EMIT6(op | (__imm >> 16), __imm & 0xffff); \
274 #define EMIT6_IMM(op, b1, imm) \
276 _EMIT6_IMM(op | reg_high(b1) << 16, imm); \
280 #define EMIT_CONST_U32(val) \
283 ret = jit->lit - jit->base_ip; \
284 jit->seen |= SEEN_LITERAL; \
286 *(u32 *) (jit->prg_buf + jit->lit) = (u32) val; \
291 #define EMIT_CONST_U64(val) \
294 ret = jit->lit - jit->base_ip; \
295 jit->seen |= SEEN_LITERAL; \
297 *(u64 *) (jit->prg_buf + jit->lit) = (u64) val; \
302 #define EMIT_ZERO(b1) \
304 /* llgfr %dst,%dst (zero extend to 64 bit) */ \
305 EMIT4(0xb9160000, b1, b1); \
310 * Fill whole space with illegal instructions
312 static void jit_fill_hole(void *area, unsigned int size)
314 memset(area, 0, size);
318 * Save registers from "rs" (register start) to "re" (register end) on stack
320 static void save_regs(struct bpf_jit *jit, u32 rs, u32 re)
322 u32 off = STK_OFF_R6 + (rs - 6) * 8;
325 /* stg %rs,off(%r15) */
326 _EMIT6(0xe300f000 | rs << 20 | off, 0x0024);
328 /* stmg %rs,%re,off(%r15) */
329 _EMIT6_DISP(0xeb00f000 | rs << 20 | re << 16, 0x0024, off);
333 * Restore registers from "rs" (register start) to "re" (register end) on stack
335 static void restore_regs(struct bpf_jit *jit, u32 rs, u32 re)
337 u32 off = STK_OFF_R6 + (rs - 6) * 8;
339 if (jit->seen & SEEN_STACK)
343 /* lg %rs,off(%r15) */
344 _EMIT6(0xe300f000 | rs << 20 | off, 0x0004);
346 /* lmg %rs,%re,off(%r15) */
347 _EMIT6_DISP(0xeb00f000 | rs << 20 | re << 16, 0x0004, off);
351 * Return first seen register (from start)
353 static int get_start(struct bpf_jit *jit, int start)
357 for (i = start; i <= 15; i++) {
358 if (jit->seen_reg[i])
365 * Return last seen register (from start) (gap >= 2)
367 static int get_end(struct bpf_jit *jit, int start)
371 for (i = start; i < 15; i++) {
372 if (!jit->seen_reg[i] && !jit->seen_reg[i + 1])
375 return jit->seen_reg[15] ? 15 : 14;
379 #define REGS_RESTORE 0
381 * Save and restore clobbered registers (6-15) on stack.
382 * We save/restore registers in chunks with gap >= 2 registers.
384 static void save_restore_regs(struct bpf_jit *jit, int op)
390 rs = get_start(jit, re);
393 re = get_end(jit, rs + 1);
395 save_regs(jit, rs, re);
397 restore_regs(jit, rs, re);
403 * For SKB access %b1 contains the SKB pointer. For "bpf_jit.S"
404 * we store the SKB header length on the stack and the SKB data
405 * pointer in REG_SKB_DATA.
407 static void emit_load_skb_data_hlen(struct bpf_jit *jit)
409 /* Header length: llgf %w1,<len>(%b1) */
410 EMIT6_DISP_LH(0xe3000000, 0x0016, REG_W1, REG_0, BPF_REG_1,
411 offsetof(struct sk_buff, len));
412 /* s %w1,<data_len>(%b1) */
413 EMIT4_DISP(0x5b000000, REG_W1, BPF_REG_1,
414 offsetof(struct sk_buff, data_len));
415 /* stg %w1,ST_OFF_HLEN(%r0,%r15) */
416 EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W1, REG_0, REG_15, STK_OFF_HLEN);
417 /* lg %skb_data,data_off(%b1) */
418 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_SKB_DATA, REG_0,
419 BPF_REG_1, offsetof(struct sk_buff, data));
423 * Emit function prologue
425 * Save registers and create stack frame if necessary.
426 * See stack frame layout desription in "bpf_jit.h"!
428 static void bpf_jit_prologue(struct bpf_jit *jit, bool is_classic)
430 if (jit->seen & SEEN_TAIL_CALL) {
431 /* xc STK_OFF_TCCNT(4,%r15),STK_OFF_TCCNT(%r15) */
432 _EMIT6(0xd703f000 | STK_OFF_TCCNT, 0xf000 | STK_OFF_TCCNT);
434 /* j tail_call_start: NOP if no tail calls are used */
435 EMIT4_PCREL(0xa7f40000, 6);
438 /* Tail calls have to skip above initialization */
439 jit->tail_call_start = jit->prg;
441 save_restore_regs(jit, REGS_SAVE);
442 /* Setup literal pool */
443 if (jit->seen & SEEN_LITERAL) {
445 EMIT2(0x0d00, REG_L, REG_0);
446 jit->base_ip = jit->prg;
448 /* Setup stack and backchain */
449 if (jit->seen & SEEN_STACK) {
450 if (jit->seen & SEEN_FUNC)
451 /* lgr %w1,%r15 (backchain) */
452 EMIT4(0xb9040000, REG_W1, REG_15);
453 /* la %bfp,STK_160_UNUSED(%r15) (BPF frame pointer) */
454 EMIT4_DISP(0x41000000, BPF_REG_FP, REG_15, STK_160_UNUSED);
455 /* aghi %r15,-STK_OFF */
456 EMIT4_IMM(0xa70b0000, REG_15, -STK_OFF);
457 if (jit->seen & SEEN_FUNC)
458 /* stg %w1,152(%r15) (backchain) */
459 EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W1, REG_0,
462 if (jit->seen & SEEN_SKB)
463 emit_load_skb_data_hlen(jit);
464 if (jit->seen & SEEN_SKB_CHANGE)
465 /* stg %b1,ST_OFF_SKBP(%r0,%r15) */
466 EMIT6_DISP_LH(0xe3000000, 0x0024, BPF_REG_1, REG_0, REG_15,
468 /* Clear A (%b0) and X (%b7) registers for converted BPF programs */
470 if (REG_SEEN(BPF_REG_A))
472 EMIT4_IMM(0xa7090000, BPF_REG_A, 0);
473 if (REG_SEEN(BPF_REG_X))
475 EMIT4_IMM(0xa7090000, BPF_REG_X, 0);
482 static void bpf_jit_epilogue(struct bpf_jit *jit)
485 if (jit->seen & SEEN_RET0) {
486 jit->ret0_ip = jit->prg;
488 EMIT4_IMM(0xa7090000, BPF_REG_0, 0);
490 jit->exit_ip = jit->prg;
491 /* Load exit code: lgr %r2,%b0 */
492 EMIT4(0xb9040000, REG_2, BPF_REG_0);
493 /* Restore registers */
494 save_restore_regs(jit, REGS_RESTORE);
495 if (IS_ENABLED(CC_USING_EXPOLINE) && !nospec_disable) {
496 jit->r14_thunk_ip = jit->prg;
497 /* Generate __s390_indirect_jump_r14 thunk */
498 if (test_facility(35)) {
500 EMIT6_PCREL_RIL(0xc6000000, jit->prg + 10);
503 EMIT6_PCREL_RILB(0xc0000000, REG_1, jit->prg + 14);
505 EMIT4_DISP(0x44000000, REG_0, REG_1, 0);
508 EMIT4_PCREL(0xa7f40000, 0);
513 if (IS_ENABLED(CC_USING_EXPOLINE) && !nospec_disable &&
514 (jit->seen & SEEN_FUNC)) {
515 jit->r1_thunk_ip = jit->prg;
516 /* Generate __s390_indirect_jump_r1 thunk */
517 if (test_facility(35)) {
519 EMIT6_PCREL_RIL(0xc6000000, jit->prg + 10);
521 EMIT4_PCREL(0xa7f40000, 0);
525 /* ex 0,S390_lowcore.br_r1_tampoline */
526 EMIT4_DISP(0x44000000, REG_0, REG_0,
527 offsetof(struct _lowcore, br_r1_trampoline));
529 EMIT4_PCREL(0xa7f40000, 0);
535 * Compile one eBPF instruction into s390x code
537 * NOTE: Use noinline because for gcov (-fprofile-arcs) gcc allocates a lot of
538 * stack space for the large switch statement.
540 static noinline int bpf_jit_insn(struct bpf_jit *jit, struct bpf_prog *fp, int i)
542 struct bpf_insn *insn = &fp->insnsi[i];
543 int jmp_off, last, insn_count = 1;
544 unsigned int func_addr, mask;
545 u32 dst_reg = insn->dst_reg;
546 u32 src_reg = insn->src_reg;
547 u32 *addrs = jit->addrs;
551 switch (insn->code) {
555 case BPF_ALU | BPF_MOV | BPF_X: /* dst = (u32) src */
556 /* llgfr %dst,%src */
557 EMIT4(0xb9160000, dst_reg, src_reg);
559 case BPF_ALU64 | BPF_MOV | BPF_X: /* dst = src */
561 EMIT4(0xb9040000, dst_reg, src_reg);
563 case BPF_ALU | BPF_MOV | BPF_K: /* dst = (u32) imm */
565 EMIT6_IMM(0xc00f0000, dst_reg, imm);
567 case BPF_ALU64 | BPF_MOV | BPF_K: /* dst = imm */
569 EMIT6_IMM(0xc0010000, dst_reg, imm);
574 case BPF_LD | BPF_IMM | BPF_DW: /* dst = (u64) imm */
576 /* 16 byte instruction that uses two 'struct bpf_insn' */
579 imm64 = (u64)(u32) insn[0].imm | ((u64)(u32) insn[1].imm) << 32;
580 /* lg %dst,<d(imm)>(%l) */
581 EMIT6_DISP_LH(0xe3000000, 0x0004, dst_reg, REG_0, REG_L,
582 EMIT_CONST_U64(imm64));
589 case BPF_ALU | BPF_ADD | BPF_X: /* dst = (u32) dst + (u32) src */
591 EMIT2(0x1a00, dst_reg, src_reg);
594 case BPF_ALU64 | BPF_ADD | BPF_X: /* dst = dst + src */
596 EMIT4(0xb9080000, dst_reg, src_reg);
598 case BPF_ALU | BPF_ADD | BPF_K: /* dst = (u32) dst + (u32) imm */
601 EMIT6_IMM(0xc20b0000, dst_reg, imm);
605 case BPF_ALU64 | BPF_ADD | BPF_K: /* dst = dst + imm */
609 EMIT6_IMM(0xc2080000, dst_reg, imm);
614 case BPF_ALU | BPF_SUB | BPF_X: /* dst = (u32) dst - (u32) src */
616 EMIT2(0x1b00, dst_reg, src_reg);
619 case BPF_ALU64 | BPF_SUB | BPF_X: /* dst = dst - src */
621 EMIT4(0xb9090000, dst_reg, src_reg);
623 case BPF_ALU | BPF_SUB | BPF_K: /* dst = (u32) dst - (u32) imm */
626 EMIT6_IMM(0xc20b0000, dst_reg, -imm);
630 case BPF_ALU64 | BPF_SUB | BPF_K: /* dst = dst - imm */
633 if (imm == -0x80000000) {
634 /* algfi %dst,0x80000000 */
635 EMIT6_IMM(0xc20a0000, dst_reg, 0x80000000);
638 EMIT6_IMM(0xc2080000, dst_reg, -imm);
644 case BPF_ALU | BPF_MUL | BPF_X: /* dst = (u32) dst * (u32) src */
646 EMIT4(0xb2520000, dst_reg, src_reg);
649 case BPF_ALU64 | BPF_MUL | BPF_X: /* dst = dst * src */
651 EMIT4(0xb90c0000, dst_reg, src_reg);
653 case BPF_ALU | BPF_MUL | BPF_K: /* dst = (u32) dst * (u32) imm */
656 EMIT6_IMM(0xc2010000, dst_reg, imm);
660 case BPF_ALU64 | BPF_MUL | BPF_K: /* dst = dst * imm */
664 EMIT6_IMM(0xc2000000, dst_reg, imm);
669 case BPF_ALU | BPF_DIV | BPF_X: /* dst = (u32) dst / (u32) src */
670 case BPF_ALU | BPF_MOD | BPF_X: /* dst = (u32) dst % (u32) src */
672 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
674 jit->seen |= SEEN_RET0;
675 /* ltr %src,%src (if src == 0 goto fail) */
676 EMIT2(0x1200, src_reg, src_reg);
678 EMIT4_PCREL(0xa7840000, jit->ret0_ip - jit->prg);
680 EMIT4_IMM(0xa7080000, REG_W0, 0);
682 EMIT2(0x1800, REG_W1, dst_reg);
684 EMIT4(0xb9970000, REG_W0, src_reg);
686 EMIT4(0xb9160000, dst_reg, rc_reg);
689 case BPF_ALU64 | BPF_DIV | BPF_X: /* dst = dst / src */
690 case BPF_ALU64 | BPF_MOD | BPF_X: /* dst = dst % src */
692 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
694 jit->seen |= SEEN_RET0;
695 /* ltgr %src,%src (if src == 0 goto fail) */
696 EMIT4(0xb9020000, src_reg, src_reg);
698 EMIT4_PCREL(0xa7840000, jit->ret0_ip - jit->prg);
700 EMIT4_IMM(0xa7090000, REG_W0, 0);
702 EMIT4(0xb9040000, REG_W1, dst_reg);
704 EMIT4(0xb9870000, REG_W0, src_reg);
706 EMIT4(0xb9040000, dst_reg, rc_reg);
709 case BPF_ALU | BPF_DIV | BPF_K: /* dst = (u32) dst / (u32) imm */
710 case BPF_ALU | BPF_MOD | BPF_K: /* dst = (u32) dst % (u32) imm */
712 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
715 if (BPF_OP(insn->code) == BPF_MOD)
717 EMIT4_IMM(0xa7090000, dst_reg, 0);
723 EMIT4_IMM(0xa7080000, REG_W0, 0);
725 EMIT2(0x1800, REG_W1, dst_reg);
726 /* dl %w0,<d(imm)>(%l) */
727 EMIT6_DISP_LH(0xe3000000, 0x0097, REG_W0, REG_0, REG_L,
728 EMIT_CONST_U32(imm));
730 EMIT4(0xb9160000, dst_reg, rc_reg);
733 case BPF_ALU64 | BPF_DIV | BPF_K: /* dst = dst / imm */
734 case BPF_ALU64 | BPF_MOD | BPF_K: /* dst = dst % imm */
736 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
739 if (BPF_OP(insn->code) == BPF_MOD)
741 EMIT4_IMM(0xa7090000, dst_reg, 0);
745 EMIT4_IMM(0xa7090000, REG_W0, 0);
747 EMIT4(0xb9040000, REG_W1, dst_reg);
748 /* dlg %w0,<d(imm)>(%l) */
749 EMIT6_DISP_LH(0xe3000000, 0x0087, REG_W0, REG_0, REG_L,
750 EMIT_CONST_U64(imm));
752 EMIT4(0xb9040000, dst_reg, rc_reg);
758 case BPF_ALU | BPF_AND | BPF_X: /* dst = (u32) dst & (u32) src */
760 EMIT2(0x1400, dst_reg, src_reg);
763 case BPF_ALU64 | BPF_AND | BPF_X: /* dst = dst & src */
765 EMIT4(0xb9800000, dst_reg, src_reg);
767 case BPF_ALU | BPF_AND | BPF_K: /* dst = (u32) dst & (u32) imm */
769 EMIT6_IMM(0xc00b0000, dst_reg, imm);
772 case BPF_ALU64 | BPF_AND | BPF_K: /* dst = dst & imm */
773 /* ng %dst,<d(imm)>(%l) */
774 EMIT6_DISP_LH(0xe3000000, 0x0080, dst_reg, REG_0, REG_L,
775 EMIT_CONST_U64(imm));
780 case BPF_ALU | BPF_OR | BPF_X: /* dst = (u32) dst | (u32) src */
782 EMIT2(0x1600, dst_reg, src_reg);
785 case BPF_ALU64 | BPF_OR | BPF_X: /* dst = dst | src */
787 EMIT4(0xb9810000, dst_reg, src_reg);
789 case BPF_ALU | BPF_OR | BPF_K: /* dst = (u32) dst | (u32) imm */
791 EMIT6_IMM(0xc00d0000, dst_reg, imm);
794 case BPF_ALU64 | BPF_OR | BPF_K: /* dst = dst | imm */
795 /* og %dst,<d(imm)>(%l) */
796 EMIT6_DISP_LH(0xe3000000, 0x0081, dst_reg, REG_0, REG_L,
797 EMIT_CONST_U64(imm));
802 case BPF_ALU | BPF_XOR | BPF_X: /* dst = (u32) dst ^ (u32) src */
804 EMIT2(0x1700, dst_reg, src_reg);
807 case BPF_ALU64 | BPF_XOR | BPF_X: /* dst = dst ^ src */
809 EMIT4(0xb9820000, dst_reg, src_reg);
811 case BPF_ALU | BPF_XOR | BPF_K: /* dst = (u32) dst ^ (u32) imm */
814 EMIT6_IMM(0xc0070000, dst_reg, imm);
818 case BPF_ALU64 | BPF_XOR | BPF_K: /* dst = dst ^ imm */
819 /* xg %dst,<d(imm)>(%l) */
820 EMIT6_DISP_LH(0xe3000000, 0x0082, dst_reg, REG_0, REG_L,
821 EMIT_CONST_U64(imm));
826 case BPF_ALU | BPF_LSH | BPF_X: /* dst = (u32) dst << (u32) src */
827 /* sll %dst,0(%src) */
828 EMIT4_DISP(0x89000000, dst_reg, src_reg, 0);
831 case BPF_ALU64 | BPF_LSH | BPF_X: /* dst = dst << src */
832 /* sllg %dst,%dst,0(%src) */
833 EMIT6_DISP_LH(0xeb000000, 0x000d, dst_reg, dst_reg, src_reg, 0);
835 case BPF_ALU | BPF_LSH | BPF_K: /* dst = (u32) dst << (u32) imm */
837 /* sll %dst,imm(%r0) */
838 EMIT4_DISP(0x89000000, dst_reg, REG_0, imm);
842 case BPF_ALU64 | BPF_LSH | BPF_K: /* dst = dst << imm */
845 /* sllg %dst,%dst,imm(%r0) */
846 EMIT6_DISP_LH(0xeb000000, 0x000d, dst_reg, dst_reg, REG_0, imm);
851 case BPF_ALU | BPF_RSH | BPF_X: /* dst = (u32) dst >> (u32) src */
852 /* srl %dst,0(%src) */
853 EMIT4_DISP(0x88000000, dst_reg, src_reg, 0);
856 case BPF_ALU64 | BPF_RSH | BPF_X: /* dst = dst >> src */
857 /* srlg %dst,%dst,0(%src) */
858 EMIT6_DISP_LH(0xeb000000, 0x000c, dst_reg, dst_reg, src_reg, 0);
860 case BPF_ALU | BPF_RSH | BPF_K: /* dst = (u32) dst >> (u32) imm */
862 /* srl %dst,imm(%r0) */
863 EMIT4_DISP(0x88000000, dst_reg, REG_0, imm);
867 case BPF_ALU64 | BPF_RSH | BPF_K: /* dst = dst >> imm */
870 /* srlg %dst,%dst,imm(%r0) */
871 EMIT6_DISP_LH(0xeb000000, 0x000c, dst_reg, dst_reg, REG_0, imm);
876 case BPF_ALU64 | BPF_ARSH | BPF_X: /* ((s64) dst) >>= src */
877 /* srag %dst,%dst,0(%src) */
878 EMIT6_DISP_LH(0xeb000000, 0x000a, dst_reg, dst_reg, src_reg, 0);
880 case BPF_ALU64 | BPF_ARSH | BPF_K: /* ((s64) dst) >>= imm */
883 /* srag %dst,%dst,imm(%r0) */
884 EMIT6_DISP_LH(0xeb000000, 0x000a, dst_reg, dst_reg, REG_0, imm);
889 case BPF_ALU | BPF_NEG: /* dst = (u32) -dst */
891 EMIT2(0x1300, dst_reg, dst_reg);
894 case BPF_ALU64 | BPF_NEG: /* dst = -dst */
896 EMIT4(0xb9030000, dst_reg, dst_reg);
901 case BPF_ALU | BPF_END | BPF_FROM_BE:
902 /* s390 is big endian, therefore only clear high order bytes */
904 case 16: /* dst = (u16) cpu_to_be16(dst) */
905 /* llghr %dst,%dst */
906 EMIT4(0xb9850000, dst_reg, dst_reg);
908 case 32: /* dst = (u32) cpu_to_be32(dst) */
909 /* llgfr %dst,%dst */
910 EMIT4(0xb9160000, dst_reg, dst_reg);
912 case 64: /* dst = (u64) cpu_to_be64(dst) */
916 case BPF_ALU | BPF_END | BPF_FROM_LE:
918 case 16: /* dst = (u16) cpu_to_le16(dst) */
920 EMIT4(0xb91f0000, dst_reg, dst_reg);
921 /* srl %dst,16(%r0) */
922 EMIT4_DISP(0x88000000, dst_reg, REG_0, 16);
923 /* llghr %dst,%dst */
924 EMIT4(0xb9850000, dst_reg, dst_reg);
926 case 32: /* dst = (u32) cpu_to_le32(dst) */
928 EMIT4(0xb91f0000, dst_reg, dst_reg);
929 /* llgfr %dst,%dst */
930 EMIT4(0xb9160000, dst_reg, dst_reg);
932 case 64: /* dst = (u64) cpu_to_le64(dst) */
933 /* lrvgr %dst,%dst */
934 EMIT4(0xb90f0000, dst_reg, dst_reg);
941 case BPF_STX | BPF_MEM | BPF_B: /* *(u8 *)(dst + off) = src_reg */
942 /* stcy %src,off(%dst) */
943 EMIT6_DISP_LH(0xe3000000, 0x0072, src_reg, dst_reg, REG_0, off);
944 jit->seen |= SEEN_MEM;
946 case BPF_STX | BPF_MEM | BPF_H: /* (u16 *)(dst + off) = src */
947 /* sthy %src,off(%dst) */
948 EMIT6_DISP_LH(0xe3000000, 0x0070, src_reg, dst_reg, REG_0, off);
949 jit->seen |= SEEN_MEM;
951 case BPF_STX | BPF_MEM | BPF_W: /* *(u32 *)(dst + off) = src */
952 /* sty %src,off(%dst) */
953 EMIT6_DISP_LH(0xe3000000, 0x0050, src_reg, dst_reg, REG_0, off);
954 jit->seen |= SEEN_MEM;
956 case BPF_STX | BPF_MEM | BPF_DW: /* (u64 *)(dst + off) = src */
957 /* stg %src,off(%dst) */
958 EMIT6_DISP_LH(0xe3000000, 0x0024, src_reg, dst_reg, REG_0, off);
959 jit->seen |= SEEN_MEM;
961 case BPF_ST | BPF_MEM | BPF_B: /* *(u8 *)(dst + off) = imm */
963 EMIT4_IMM(0xa7080000, REG_W0, (u8) imm);
964 /* stcy %w0,off(dst) */
965 EMIT6_DISP_LH(0xe3000000, 0x0072, REG_W0, dst_reg, REG_0, off);
966 jit->seen |= SEEN_MEM;
968 case BPF_ST | BPF_MEM | BPF_H: /* (u16 *)(dst + off) = imm */
970 EMIT4_IMM(0xa7080000, REG_W0, (u16) imm);
971 /* sthy %w0,off(dst) */
972 EMIT6_DISP_LH(0xe3000000, 0x0070, REG_W0, dst_reg, REG_0, off);
973 jit->seen |= SEEN_MEM;
975 case BPF_ST | BPF_MEM | BPF_W: /* *(u32 *)(dst + off) = imm */
977 EMIT6_IMM(0xc00f0000, REG_W0, (u32) imm);
978 /* sty %w0,off(%dst) */
979 EMIT6_DISP_LH(0xe3000000, 0x0050, REG_W0, dst_reg, REG_0, off);
980 jit->seen |= SEEN_MEM;
982 case BPF_ST | BPF_MEM | BPF_DW: /* *(u64 *)(dst + off) = imm */
984 EMIT6_IMM(0xc0010000, REG_W0, imm);
985 /* stg %w0,off(%dst) */
986 EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W0, dst_reg, REG_0, off);
987 jit->seen |= SEEN_MEM;
990 * BPF_STX XADD (atomic_add)
992 case BPF_STX | BPF_XADD | BPF_W: /* *(u32 *)(dst + off) += src */
993 /* laal %w0,%src,off(%dst) */
994 EMIT6_DISP_LH(0xeb000000, 0x00fa, REG_W0, src_reg,
996 jit->seen |= SEEN_MEM;
998 case BPF_STX | BPF_XADD | BPF_DW: /* *(u64 *)(dst + off) += src */
999 /* laalg %w0,%src,off(%dst) */
1000 EMIT6_DISP_LH(0xeb000000, 0x00ea, REG_W0, src_reg,
1002 jit->seen |= SEEN_MEM;
1007 case BPF_LDX | BPF_MEM | BPF_B: /* dst = *(u8 *)(ul) (src + off) */
1008 /* llgc %dst,0(off,%src) */
1009 EMIT6_DISP_LH(0xe3000000, 0x0090, dst_reg, src_reg, REG_0, off);
1010 jit->seen |= SEEN_MEM;
1012 case BPF_LDX | BPF_MEM | BPF_H: /* dst = *(u16 *)(ul) (src + off) */
1013 /* llgh %dst,0(off,%src) */
1014 EMIT6_DISP_LH(0xe3000000, 0x0091, dst_reg, src_reg, REG_0, off);
1015 jit->seen |= SEEN_MEM;
1017 case BPF_LDX | BPF_MEM | BPF_W: /* dst = *(u32 *)(ul) (src + off) */
1018 /* llgf %dst,off(%src) */
1019 jit->seen |= SEEN_MEM;
1020 EMIT6_DISP_LH(0xe3000000, 0x0016, dst_reg, src_reg, REG_0, off);
1022 case BPF_LDX | BPF_MEM | BPF_DW: /* dst = *(u64 *)(ul) (src + off) */
1023 /* lg %dst,0(off,%src) */
1024 jit->seen |= SEEN_MEM;
1025 EMIT6_DISP_LH(0xe3000000, 0x0004, dst_reg, src_reg, REG_0, off);
1030 case BPF_JMP | BPF_CALL:
1033 * b0 = (__bpf_call_base + imm)(b1, b2, b3, b4, b5)
1035 const u64 func = (u64)__bpf_call_base + imm;
1037 REG_SET_SEEN(BPF_REG_5);
1038 jit->seen |= SEEN_FUNC;
1039 /* lg %w1,<d(imm)>(%l) */
1040 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_W1, REG_0, REG_L,
1041 EMIT_CONST_U64(func));
1042 if (IS_ENABLED(CC_USING_EXPOLINE) && !nospec_disable) {
1043 /* brasl %r14,__s390_indirect_jump_r1 */
1044 EMIT6_PCREL_RILB(0xc0050000, REG_14, jit->r1_thunk_ip);
1047 EMIT2(0x0d00, REG_14, REG_W1);
1049 /* lgr %b0,%r2: load return value into %b0 */
1050 EMIT4(0xb9040000, BPF_REG_0, REG_2);
1051 if (bpf_helper_changes_skb_data((void *)func)) {
1052 jit->seen |= SEEN_SKB_CHANGE;
1053 /* lg %b1,ST_OFF_SKBP(%r15) */
1054 EMIT6_DISP_LH(0xe3000000, 0x0004, BPF_REG_1, REG_0,
1055 REG_15, STK_OFF_SKBP);
1056 emit_load_skb_data_hlen(jit);
1060 case BPF_JMP | BPF_CALL | BPF_X:
1063 * B1: pointer to ctx
1064 * B2: pointer to bpf_array
1065 * B3: index in bpf_array
1067 jit->seen |= SEEN_TAIL_CALL;
1070 * if (index >= array->map.max_entries)
1074 /* llgf %w1,map.max_entries(%b2) */
1075 EMIT6_DISP_LH(0xe3000000, 0x0016, REG_W1, REG_0, BPF_REG_2,
1076 offsetof(struct bpf_array, map.max_entries));
1077 /* clrj %b3,%w1,0xa,label0: if (u32)%b3 >= (u32)%w1 goto out */
1078 EMIT6_PCREL_LABEL(0xec000000, 0x0077, BPF_REG_3,
1082 * if (tail_call_cnt++ > MAX_TAIL_CALL_CNT)
1086 if (jit->seen & SEEN_STACK)
1087 off = STK_OFF_TCCNT + STK_OFF;
1089 off = STK_OFF_TCCNT;
1091 EMIT4_IMM(0xa7080000, REG_W0, 1);
1092 /* laal %w1,%w0,off(%r15) */
1093 EMIT6_DISP_LH(0xeb000000, 0x00fa, REG_W1, REG_W0, REG_15, off);
1094 /* clij %w1,MAX_TAIL_CALL_CNT,0x2,label0 */
1095 EMIT6_PCREL_IMM_LABEL(0xec000000, 0x007f, REG_W1,
1096 MAX_TAIL_CALL_CNT, 0, 0x2);
1099 * prog = array->ptrs[index];
1104 /* llgfr %r1,%b3: %r1 = (u32) index */
1105 EMIT4(0xb9160000, REG_1, BPF_REG_3);
1106 /* sllg %r1,%r1,3: %r1 *= 8 */
1107 EMIT6_DISP_LH(0xeb000000, 0x000d, REG_1, REG_1, REG_0, 3);
1108 /* lg %r1,prog(%b2,%r1) */
1109 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_1, BPF_REG_2,
1110 REG_1, offsetof(struct bpf_array, ptrs));
1111 /* clgij %r1,0,0x8,label0 */
1112 EMIT6_PCREL_IMM_LABEL(0xec000000, 0x007d, REG_1, 0, 0, 0x8);
1115 * Restore registers before calling function
1117 save_restore_regs(jit, REGS_RESTORE);
1120 * goto *(prog->bpf_func + tail_call_start);
1123 /* lg %r1,bpf_func(%r1) */
1124 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_1, REG_1, REG_0,
1125 offsetof(struct bpf_prog, bpf_func));
1126 /* bc 0xf,tail_call_start(%r1) */
1127 _EMIT4(0x47f01000 + jit->tail_call_start);
1129 jit->labels[0] = jit->prg;
1131 case BPF_JMP | BPF_EXIT: /* return b0 */
1132 last = (i == fp->len - 1) ? 1 : 0;
1133 if (last && !(jit->seen & SEEN_RET0))
1136 EMIT4_PCREL(0xa7f40000, jit->exit_ip - jit->prg);
1139 * Branch relative (number of skipped instructions) to offset on
1142 * Condition code to mask mapping:
1144 * CC | Description | Mask
1145 * ------------------------------
1146 * 0 | Operands equal | 8
1147 * 1 | First operand low | 4
1148 * 2 | First operand high | 2
1151 * For s390x relative branches: ip = ip + off_bytes
1152 * For BPF relative branches: insn = insn + off_insns + 1
1154 * For example for s390x with offset 0 we jump to the branch
1155 * instruction itself (loop) and for BPF with offset 0 we
1156 * branch to the instruction behind the branch.
1158 case BPF_JMP | BPF_JA: /* if (true) */
1159 mask = 0xf000; /* j */
1161 case BPF_JMP | BPF_JSGT | BPF_K: /* ((s64) dst > (s64) imm) */
1162 mask = 0x2000; /* jh */
1164 case BPF_JMP | BPF_JSGE | BPF_K: /* ((s64) dst >= (s64) imm) */
1165 mask = 0xa000; /* jhe */
1167 case BPF_JMP | BPF_JGT | BPF_K: /* (dst_reg > imm) */
1168 mask = 0x2000; /* jh */
1170 case BPF_JMP | BPF_JGE | BPF_K: /* (dst_reg >= imm) */
1171 mask = 0xa000; /* jhe */
1173 case BPF_JMP | BPF_JNE | BPF_K: /* (dst_reg != imm) */
1174 mask = 0x7000; /* jne */
1176 case BPF_JMP | BPF_JEQ | BPF_K: /* (dst_reg == imm) */
1177 mask = 0x8000; /* je */
1179 case BPF_JMP | BPF_JSET | BPF_K: /* (dst_reg & imm) */
1180 mask = 0x7000; /* jnz */
1181 /* lgfi %w1,imm (load sign extend imm) */
1182 EMIT6_IMM(0xc0010000, REG_W1, imm);
1184 EMIT4(0xb9800000, REG_W1, dst_reg);
1187 case BPF_JMP | BPF_JSGT | BPF_X: /* ((s64) dst > (s64) src) */
1188 mask = 0x2000; /* jh */
1190 case BPF_JMP | BPF_JSGE | BPF_X: /* ((s64) dst >= (s64) src) */
1191 mask = 0xa000; /* jhe */
1193 case BPF_JMP | BPF_JGT | BPF_X: /* (dst > src) */
1194 mask = 0x2000; /* jh */
1196 case BPF_JMP | BPF_JGE | BPF_X: /* (dst >= src) */
1197 mask = 0xa000; /* jhe */
1199 case BPF_JMP | BPF_JNE | BPF_X: /* (dst != src) */
1200 mask = 0x7000; /* jne */
1202 case BPF_JMP | BPF_JEQ | BPF_X: /* (dst == src) */
1203 mask = 0x8000; /* je */
1205 case BPF_JMP | BPF_JSET | BPF_X: /* (dst & src) */
1206 mask = 0x7000; /* jnz */
1207 /* ngrk %w1,%dst,%src */
1208 EMIT4_RRF(0xb9e40000, REG_W1, dst_reg, src_reg);
1211 /* lgfi %w1,imm (load sign extend imm) */
1212 EMIT6_IMM(0xc0010000, REG_W1, imm);
1213 /* cgrj %dst,%w1,mask,off */
1214 EMIT6_PCREL(0xec000000, 0x0064, dst_reg, REG_W1, i, off, mask);
1217 /* lgfi %w1,imm (load sign extend imm) */
1218 EMIT6_IMM(0xc0010000, REG_W1, imm);
1219 /* clgrj %dst,%w1,mask,off */
1220 EMIT6_PCREL(0xec000000, 0x0065, dst_reg, REG_W1, i, off, mask);
1223 /* cgrj %dst,%src,mask,off */
1224 EMIT6_PCREL(0xec000000, 0x0064, dst_reg, src_reg, i, off, mask);
1227 /* clgrj %dst,%src,mask,off */
1228 EMIT6_PCREL(0xec000000, 0x0065, dst_reg, src_reg, i, off, mask);
1231 /* brc mask,jmp_off (branch instruction needs 4 bytes) */
1232 jmp_off = addrs[i + off + 1] - (addrs[i + 1] - 4);
1233 EMIT4_PCREL(0xa7040000 | mask << 8, jmp_off);
1238 case BPF_LD | BPF_ABS | BPF_B: /* b0 = *(u8 *) (skb->data+imm) */
1239 case BPF_LD | BPF_IND | BPF_B: /* b0 = *(u8 *) (skb->data+imm+src) */
1240 if ((BPF_MODE(insn->code) == BPF_ABS) && (imm >= 0))
1241 func_addr = __pa(sk_load_byte_pos);
1243 func_addr = __pa(sk_load_byte);
1245 case BPF_LD | BPF_ABS | BPF_H: /* b0 = *(u16 *) (skb->data+imm) */
1246 case BPF_LD | BPF_IND | BPF_H: /* b0 = *(u16 *) (skb->data+imm+src) */
1247 if ((BPF_MODE(insn->code) == BPF_ABS) && (imm >= 0))
1248 func_addr = __pa(sk_load_half_pos);
1250 func_addr = __pa(sk_load_half);
1252 case BPF_LD | BPF_ABS | BPF_W: /* b0 = *(u32 *) (skb->data+imm) */
1253 case BPF_LD | BPF_IND | BPF_W: /* b0 = *(u32 *) (skb->data+imm+src) */
1254 if ((BPF_MODE(insn->code) == BPF_ABS) && (imm >= 0))
1255 func_addr = __pa(sk_load_word_pos);
1257 func_addr = __pa(sk_load_word);
1260 jit->seen |= SEEN_SKB | SEEN_RET0 | SEEN_FUNC;
1261 REG_SET_SEEN(REG_14); /* Return address of possible func call */
1265 * BPF_REG_6 (R7) : skb pointer
1266 * REG_SKB_DATA (R12): skb data pointer
1269 * BPF_REG_2 (R3) : offset of byte(s) to fetch in skb
1270 * BPF_REG_5 (R6) : return address
1273 * BPF_REG_0 (R14): data read from skb
1275 * Scratch registers (BPF_REG_1-5)
1278 /* Call function: llilf %w1,func_addr */
1279 EMIT6_IMM(0xc00f0000, REG_W1, func_addr);
1281 /* Offset: lgfi %b2,imm */
1282 EMIT6_IMM(0xc0010000, BPF_REG_2, imm);
1283 if (BPF_MODE(insn->code) == BPF_IND)
1284 /* agfr %b2,%src (%src is s32 here) */
1285 EMIT4(0xb9180000, BPF_REG_2, src_reg);
1287 /* basr %b5,%w1 (%b5 is call saved) */
1288 EMIT2(0x0d00, BPF_REG_5, REG_W1);
1291 * Note: For fast access we jump directly after the
1292 * jnz instruction from bpf_jit.S
1295 EMIT4_PCREL(0xa7740000, jit->ret0_ip - jit->prg);
1297 default: /* too complex, give up */
1298 pr_err("Unknown opcode %02x\n", insn->code);
1305 * Compile eBPF program into s390x code
1307 static int bpf_jit_prog(struct bpf_jit *jit, struct bpf_prog *fp)
1311 jit->lit = jit->lit_start;
1314 bpf_jit_prologue(jit, bpf_prog_was_classic(fp));
1315 for (i = 0; i < fp->len; i += insn_count) {
1316 insn_count = bpf_jit_insn(jit, fp, i);
1319 /* Next instruction address */
1320 jit->addrs[i + insn_count] = jit->prg;
1322 bpf_jit_epilogue(jit);
1324 jit->lit_start = jit->prg;
1325 jit->size = jit->lit;
1326 jit->size_prg = jit->prg;
1331 * Classic BPF function stub. BPF programs will be converted into
1332 * eBPF and then bpf_int_jit_compile() will be called.
1334 void bpf_jit_compile(struct bpf_prog *fp)
1339 * Compile eBPF program "fp"
1341 void bpf_int_jit_compile(struct bpf_prog *fp)
1343 struct bpf_binary_header *header;
1347 if (!bpf_jit_enable)
1349 memset(&jit, 0, sizeof(jit));
1350 jit.addrs = kcalloc(fp->len + 1, sizeof(*jit.addrs), GFP_KERNEL);
1351 if (jit.addrs == NULL)
1354 * Three initial passes:
1355 * - 1/2: Determine clobbered registers
1356 * - 3: Calculate program size and addrs arrray
1358 for (pass = 1; pass <= 3; pass++) {
1359 if (bpf_jit_prog(&jit, fp))
1363 * Final pass: Allocate and generate program
1365 if (jit.size >= BPF_SIZE_MAX)
1367 header = bpf_jit_binary_alloc(jit.size, &jit.prg_buf, 2, jit_fill_hole);
1370 if (bpf_jit_prog(&jit, fp))
1372 if (bpf_jit_enable > 1) {
1373 bpf_jit_dump(fp->len, jit.size, pass, jit.prg_buf);
1375 print_fn_code(jit.prg_buf, jit.size_prg);
1378 set_memory_ro((unsigned long)header, header->pages);
1379 fp->bpf_func = (void *) jit.prg_buf;
1389 void bpf_jit_free(struct bpf_prog *fp)
1391 unsigned long addr = (unsigned long)fp->bpf_func & PAGE_MASK;
1392 struct bpf_binary_header *header = (void *)addr;
1397 set_memory_rw(addr, header->pages);
1398 bpf_jit_binary_free(header);
1401 bpf_prog_unlock_free(fp);