2 * Copyright IBM Corp 2000, 2011
3 * Author(s): Holger Smolinski <Holger.Smolinski@de.ibm.com>,
7 #include <linux/linkage.h>
8 #include <asm/asm-offsets.h>
9 #include <asm/nospec-insn.h>
15 # Issue "store status" for the current CPU to its prefix page
16 # and call passed function afterwards
18 # r2 = Function to be called after store status
19 # r3 = Parameter for function
22 /* Save register one and load save area base */
23 stg %r1,__LC_SAVE_AREA_RESTART
24 /* General purpose registers */
25 lghi %r1,__LC_GPREGS_SAVE_AREA
27 mvc 8(8,%r1),__LC_SAVE_AREA_RESTART
28 /* Control registers */
29 lghi %r1,__LC_CREGS_SAVE_AREA
31 /* Access registers */
32 lghi %r1,__LC_AREGS_SAVE_AREA
34 /* Floating point registers */
35 lghi %r1,__LC_FPREGS_SAVE_AREA
52 /* Floating point control register */
53 lghi %r1,__LC_FP_CREG_SAVE_AREA
56 lghi %r1,__LC_CPU_TIMER_SAVE_AREA
58 /* Store prefix register */
59 lghi %r1,__LC_PREFIX_SAVE_AREA
61 /* Clock comparator - seven bytes */
62 lghi %r1,__LC_CLOCK_COMP_SAVE_AREA
66 /* Program status word */
67 lghi %r1,__LC_PSW_SAVE_AREA
78 .Lclkcmp: .quad 0x0000000000000000
83 # Parameter: r2 = schid of reipl device
88 .Lpg0: lpswe .Lnewpsw-.Lpg0(%r13)
91 brasl %r14,store_status
93 .Lstatus: lctlg %c6,%c6,.Lall-.Lpg0(%r13)
95 mvc __LC_PGM_NEW_PSW(16),.Lpcnew-.Lpg0(%r13)
96 stsch .Lschib-.Lpg0(%r13)
97 oi .Lschib+5-.Lpg0(%r13),0x84
98 .Lecs: xi .Lschib+27-.Lpg0(%r13),0x01
99 msch .Lschib-.Lpg0(%r13)
101 .Lssch: ssch .Liplorb-.Lpg0(%r13)
104 bas %r14,.Ldisab-.Lpg0(%r13)
105 .L001: mvc __LC_IO_NEW_PSW(16),.Lionew-.Lpg0(%r13)
106 .Ltpi: lpswe .Lwaitpsw-.Lpg0(%r13)
107 .Lcont: c %r1,__LC_SUBCHANNEL_ID
109 clc __LC_IO_INT_PARM(4),.Liplorb-.Lpg0(%r13)
111 tsch .Liplirb-.Lpg0(%r13)
112 tm .Liplirb+9-.Lpg0(%r13),0xbf
114 bas %r14,.Ldisab-.Lpg0(%r13)
115 .L002: tm .Liplirb+8-.Lpg0(%r13),0xf3
117 bas %r14,.Ldisab-.Lpg0(%r13)
118 .L003: st %r1,__LC_SUBCHANNEL_ID
119 lhi %r1,0 # mode 0 = esa
120 slr %r0,%r0 # set cpuid to zero
121 sigp %r1,%r0,SIGP_SET_ARCHITECTURE # switch to esa mode
124 srl %r14,1 # need to kill hi bit to avoid specification exceptions.
125 st %r14,.Ldispsw+12-.Lpg0(%r13)
126 lpswe .Ldispsw-.Lpg0(%r13)
128 .Lall: .quad 0x00000000ff000000
131 * These addresses have to be 31 bit otherwise
132 * the sigp will throw a specifcation exception
133 * when switching to ESA mode as bit 31 be set
135 * Bit 31 of the addresses has to be 0 for the
136 * 31bit lpswe instruction a fact they appear to have
137 * omitted from the pop.
139 .Lnewpsw: .quad 0x0000000080000000
141 .Lpcnew: .quad 0x0000000080000000
143 .Lionew: .quad 0x0000000080000000
145 .Lwaitpsw: .quad 0x0202000080000000
147 .Ldispsw: .quad 0x0002000080000000
148 .quad 0x0000000000000000
149 .Liplccws: .long 0x02000000,0x60000018
150 .long 0x08000008,0x20000001
151 .Liplorb: .long 0x0049504c,0x0040ff80
152 .long 0x00000000+.Liplccws
153 .Lschib: .long 0x00000000,0x00000000
154 .long 0x00000000,0x00000000
155 .long 0x00000000,0x00000000
156 .long 0x00000000,0x00000000
157 .long 0x00000000,0x00000000
158 .long 0x00000000,0x00000000
159 .Liplirb: .long 0x00000000,0x00000000
160 .long 0x00000000,0x00000000
161 .long 0x00000000,0x00000000
162 .long 0x00000000,0x00000000
163 .long 0x00000000,0x00000000
164 .long 0x00000000,0x00000000
165 .long 0x00000000,0x00000000
166 .long 0x00000000,0x00000000