2 * Support for Vector Instructions
4 * Assembler macros to generate .byte/.word code for particular
5 * vector instructions that are supported by recent binutils (>= 2.26) only.
7 * Copyright IBM Corp. 2015
8 * Author(s): Hendrik Brueckner <brueckner@linux.vnet.ibm.com>
11 #ifndef __ASM_S390_VX_INSN_H
12 #define __ASM_S390_VX_INSN_H
17 /* Macros to generate vector instruction byte code */
19 /* GR_NUM - Retrieve general-purpose register number
21 * @opd: Operand to store register number
22 * @r64: String designation register in the format "%rN"
79 /* VX_NUM - Retrieve vector register number
81 * @opd: Operand to store register number
82 * @vxr: String designation register in the format "%vN"
84 * The vector register number is used for as input number to the
85 * instruction and, as well as, to compute the RXB field of the
191 /* RXB - Compute most significant bit used vector registers
193 * @rxb: Operand to store computed RXB value
194 * @v1: First vector register designated operand
195 * @v2: Second vector register designated operand
196 * @v3: Third vector register designated operand
197 * @v4: Fourth vector register designated operand
199 .macro RXB rxb v1 v2=0 v3=0 v4=0
215 /* MRXB - Generate Element Size Control and RXB value
217 * @m: Element size control
218 * @v1: First vector register designated operand (for RXB)
219 * @v2: Second vector register designated operand (for RXB)
220 * @v3: Third vector register designated operand (for RXB)
221 * @v4: Fourth vector register designated operand (for RXB)
223 .macro MRXB m v1 v2=0 v3=0 v4=0
225 RXB rxb, \v1, \v2, \v3, \v4
226 .byte (\m << 4) | rxb
229 /* MRXBOPC - Generate Element Size Control, RXB, and final Opcode fields
231 * @m: Element size control
233 * @v1: First vector register designated operand (for RXB)
234 * @v2: Second vector register designated operand (for RXB)
235 * @v3: Third vector register designated operand (for RXB)
236 * @v4: Fourth vector register designated operand (for RXB)
238 .macro MRXBOPC m opc v1 v2=0 v3=0 v4=0
239 MRXB \m, \v1, \v2, \v3, \v4
243 /* Vector support instructions */
245 /* VECTOR GENERATE BYTE MASK */
248 .word (0xE700 | ((v1&15) << 4))
259 /* VECTOR LOAD VR ELEMENT FROM GR */
260 .macro VLVG v, gr, disp, m
264 .word 0xE700 | ((v1&15) << 4) | r3
265 .word (b2 << 12) | (\disp)
268 .macro VLVGB v, gr, index, base
269 VLVG \v, \gr, \index, \base, 0
271 .macro VLVGH v, gr, index
272 VLVG \v, \gr, \index, 1
274 .macro VLVGF v, gr, index
275 VLVG \v, \gr, \index, 2
277 .macro VLVGG v, gr, index
278 VLVG \v, \gr, \index, 3
281 /* VECTOR LOAD REGISTER */
285 .word 0xE700 | ((v1&15) << 4) | (v2&15)
287 MRXBOPC 0, 0x56, v1, v2
291 .macro VL v, disp, index="%r0", base
295 .word 0xE700 | ((v1&15) << 4) | x2
296 .word (b2 << 12) | (\disp)
300 /* VECTOR LOAD ELEMENT */
301 .macro VLEx vr1, disp, index="%r0", base, m3, opc
305 .word 0xE700 | ((v1&15) << 4) | x2
306 .word (b2 << 12) | (\disp)
307 MRXBOPC \m3, \opc, v1
309 .macro VLEB vr1, disp, index="%r0", base, m3
310 VLEx \vr1, \disp, \index, \base, \m3, 0x00
312 .macro VLEH vr1, disp, index="%r0", base, m3
313 VLEx \vr1, \disp, \index, \base, \m3, 0x01
315 .macro VLEF vr1, disp, index="%r0", base, m3
316 VLEx \vr1, \disp, \index, \base, \m3, 0x03
318 .macro VLEG vr1, disp, index="%r0", base, m3
319 VLEx \vr1, \disp, \index, \base, \m3, 0x02
322 /* VECTOR LOAD ELEMENT IMMEDIATE */
323 .macro VLEIx vr1, imm2, m3, opc
325 .word 0xE700 | ((v1&15) << 4)
327 MRXBOPC \m3, \opc, v1
329 .macro VLEIB vr1, imm2, index
330 VLEIx \vr1, \imm2, \index, 0x40
332 .macro VLEIH vr1, imm2, index
333 VLEIx \vr1, \imm2, \index, 0x41
335 .macro VLEIF vr1, imm2, index
336 VLEIx \vr1, \imm2, \index, 0x43
338 .macro VLEIG vr1, imm2, index
339 VLEIx \vr1, \imm2, \index, 0x42
342 /* VECTOR LOAD GR FROM VR ELEMENT */
343 .macro VLGV gr, vr, disp, base="%r0", m
347 .word 0xE700 | (r1 << 4) | (v3&15)
348 .word (b2 << 12) | (\disp)
351 .macro VLGVB gr, vr, disp, base="%r0"
352 VLGV \gr, \vr, \disp, \base, 0
354 .macro VLGVH gr, vr, disp, base="%r0"
355 VLGV \gr, \vr, \disp, \base, 1
357 .macro VLGVF gr, vr, disp, base="%r0"
358 VLGV \gr, \vr, \disp, \base, 2
360 .macro VLGVG gr, vr, disp, base="%r0"
361 VLGV \gr, \vr, \disp, \base, 3
364 /* VECTOR LOAD MULTIPLE */
365 .macro VLM vfrom, vto, disp, base
368 GR_NUM b2, \base /* Base register */
369 .word 0xE700 | ((v1&15) << 4) | (v3&15)
370 .word (b2 << 12) | (\disp)
371 MRXBOPC 0, 0x36, v1, v3
374 /* VECTOR STORE MULTIPLE */
375 .macro VSTM vfrom, vto, disp, base
378 GR_NUM b2, \base /* Base register */
379 .word 0xE700 | ((v1&15) << 4) | (v3&15)
380 .word (b2 << 12) | (\disp)
381 MRXBOPC 0, 0x3E, v1, v3
385 .macro VPERM vr1, vr2, vr3, vr4
390 .word 0xE700 | ((v1&15) << 4) | (v2&15)
391 .word ((v3&15) << 12)
392 MRXBOPC (v4&15), 0x8C, v1, v2, v3, v4
395 /* VECTOR UNPACK LOGICAL LOW */
396 .macro VUPLL vr1, vr2, m3
399 .word 0xE700 | ((v1&15) << 4) | (v2&15)
401 MRXBOPC \m3, 0xD4, v1, v2
403 .macro VUPLLB vr1, vr2
406 .macro VUPLLH vr1, vr2
409 .macro VUPLLF vr1, vr2
414 /* Vector integer instructions */
417 .macro VN vr1, vr2, vr3
421 .word 0xE700 | ((v1&15) << 4) | (v2&15)
422 .word ((v3&15) << 12)
423 MRXBOPC 0, 0x68, v1, v2, v3
426 /* VECTOR EXCLUSIVE OR */
427 .macro VX vr1, vr2, vr3
431 .word 0xE700 | ((v1&15) << 4) | (v2&15)
432 .word ((v3&15) << 12)
433 MRXBOPC 0, 0x6D, v1, v2, v3
436 /* VECTOR GALOIS FIELD MULTIPLY SUM */
437 .macro VGFM vr1, vr2, vr3, m4
441 .word 0xE700 | ((v1&15) << 4) | (v2&15)
442 .word ((v3&15) << 12)
443 MRXBOPC \m4, 0xB4, v1, v2, v3
445 .macro VGFMB vr1, vr2, vr3
446 VGFM \vr1, \vr2, \vr3, 0
448 .macro VGFMH vr1, vr2, vr3
449 VGFM \vr1, \vr2, \vr3, 1
451 .macro VGFMF vr1, vr2, vr3
452 VGFM \vr1, \vr2, \vr3, 2
454 .macro VGFMG vr1, vr2, vr3
455 VGFM \vr1, \vr2, \vr3, 3
458 /* VECTOR GALOIS FIELD MULTIPLY SUM AND ACCUMULATE */
459 .macro VGFMA vr1, vr2, vr3, vr4, m5
464 .word 0xE700 | ((v1&15) << 4) | (v2&15)
465 .word ((v3&15) << 12) | (\m5 << 8)
466 MRXBOPC (v4&15), 0xBC, v1, v2, v3, v4
468 .macro VGFMAB vr1, vr2, vr3, vr4
469 VGFMA \vr1, \vr2, \vr3, \vr4, 0
471 .macro VGFMAH vr1, vr2, vr3, vr4
472 VGFMA \vr1, \vr2, \vr3, \vr4, 1
474 .macro VGFMAF vr1, vr2, vr3, vr4
475 VGFMA \vr1, \vr2, \vr3, \vr4, 2
477 .macro VGFMAG vr1, vr2, vr3, vr4
478 VGFMA \vr1, \vr2, \vr3, \vr4, 3
481 /* VECTOR SHIFT RIGHT LOGICAL BY BYTE */
482 .macro VSRLB vr1, vr2, vr3
486 .word 0xE700 | ((v1&15) << 4) | (v2&15)
487 .word ((v3&15) << 12)
488 MRXBOPC 0, 0x7D, v1, v2, v3
491 /* VECTOR REPLICATE IMMEDIATE */
492 .macro VREPI vr1, imm2, m3
494 .word 0xE700 | ((v1&15) << 4)
496 MRXBOPC \m3, 0x45, v1
498 .macro VREPIB vr1, imm2
501 .macro VREPIH vr1, imm2
504 .macro VREPIF vr1, imm2
507 .macro VREPIG vr1, imm2
512 .macro VA vr1, vr2, vr3, m4
516 .word 0xE700 | ((v1&15) << 4) | (v2&15)
517 .word ((v3&15) << 12)
518 MRXBOPC \m4, 0xF3, v1, v2, v3
520 .macro VAB vr1, vr2, vr3
521 VA \vr1, \vr2, \vr3, 0
523 .macro VAH vr1, vr2, vr3
524 VA \vr1, \vr2, \vr3, 1
526 .macro VAF vr1, vr2, vr3
527 VA \vr1, \vr2, \vr3, 2
529 .macro VAG vr1, vr2, vr3
530 VA \vr1, \vr2, \vr3, 3
532 .macro VAQ vr1, vr2, vr3
533 VA \vr1, \vr2, \vr3, 4
536 /* VECTOR ELEMENT SHIFT RIGHT ARITHMETIC */
537 .macro VESRAV vr1, vr2, vr3, m4
541 .word 0xE700 | ((v1&15) << 4) | (v2&15)
542 .word ((v3&15) << 12)
543 MRXBOPC \m4, 0x7A, v1, v2, v3
546 .macro VESRAVB vr1, vr2, vr3
547 VESRAV \vr1, \vr2, \vr3, 0
549 .macro VESRAVH vr1, vr2, vr3
550 VESRAV \vr1, \vr2, \vr3, 1
552 .macro VESRAVF vr1, vr2, vr3
553 VESRAV \vr1, \vr2, \vr3, 2
555 .macro VESRAVG vr1, vr2, vr3
556 VESRAV \vr1, \vr2, \vr3, 3
559 #endif /* __ASSEMBLY__ */
560 #endif /* __ASM_S390_VX_INSN_H */