1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Common functionality for RV32 and RV64 BPF JIT compilers
5 * Copyright (c) 2019 Björn Töpel <bjorn.topel@gmail.com>
12 #include <linux/bpf.h>
13 #include <linux/filter.h>
14 #include <asm/cacheflush.h>
16 static inline bool rvc_enabled(void)
18 return IS_ENABLED(CONFIG_RISCV_ISA_C);
22 RV_REG_ZERO = 0, /* The constant value 0 */
23 RV_REG_RA = 1, /* Return address */
24 RV_REG_SP = 2, /* Stack pointer */
25 RV_REG_GP = 3, /* Global pointer */
26 RV_REG_TP = 4, /* Thread pointer */
27 RV_REG_T0 = 5, /* Temporaries */
30 RV_REG_FP = 8, /* Saved register/frame pointer */
31 RV_REG_S1 = 9, /* Saved register */
32 RV_REG_A0 = 10, /* Function argument/return values */
33 RV_REG_A1 = 11, /* Function arguments */
40 RV_REG_S2 = 18, /* Saved registers */
50 RV_REG_T3 = 28, /* Temporaries */
56 static inline bool is_creg(u8 reg)
58 return (1 << reg) & (BIT(RV_REG_FP) |
68 struct rv_jit_context {
69 struct bpf_prog *prog;
70 u16 *insns; /* RV insns */
74 int *offset; /* BPF to RV */
80 /* Convert from ninsns to bytes. */
81 static inline int ninsns_rvoff(int ninsns)
87 struct bpf_binary_header *header;
89 struct rv_jit_context ctx;
92 static inline void bpf_fill_ill_insns(void *area, unsigned int size)
94 memset(area, 0, size);
97 static inline void bpf_flush_icache(void *start, void *end)
99 flush_icache_range((unsigned long)start, (unsigned long)end);
102 /* Emit a 4-byte riscv instruction. */
103 static inline void emit(const u32 insn, struct rv_jit_context *ctx)
106 ctx->insns[ctx->ninsns] = insn;
107 ctx->insns[ctx->ninsns + 1] = (insn >> 16);
113 /* Emit a 2-byte riscv compressed instruction. */
114 static inline void emitc(const u16 insn, struct rv_jit_context *ctx)
116 BUILD_BUG_ON(!rvc_enabled());
119 ctx->insns[ctx->ninsns] = insn;
124 static inline int epilogue_offset(struct rv_jit_context *ctx)
126 int to = ctx->epilogue_offset, from = ctx->ninsns;
128 return ninsns_rvoff(to - from);
131 /* Return -1 or inverted cond. */
132 static inline int invert_bpf_cond(u8 cond)
159 static inline bool is_6b_int(long val)
161 return -(1L << 5) <= val && val < (1L << 5);
164 static inline bool is_7b_uint(unsigned long val)
166 return val < (1UL << 7);
169 static inline bool is_8b_uint(unsigned long val)
171 return val < (1UL << 8);
174 static inline bool is_9b_uint(unsigned long val)
176 return val < (1UL << 9);
179 static inline bool is_10b_int(long val)
181 return -(1L << 9) <= val && val < (1L << 9);
184 static inline bool is_10b_uint(unsigned long val)
186 return val < (1UL << 10);
189 static inline bool is_12b_int(long val)
191 return -(1L << 11) <= val && val < (1L << 11);
194 static inline int is_12b_check(int off, int insn)
196 if (!is_12b_int(off)) {
197 pr_err("bpf-jit: insn=%d 12b < offset=%d not supported yet!\n",
204 static inline bool is_13b_int(long val)
206 return -(1L << 12) <= val && val < (1L << 12);
209 static inline bool is_21b_int(long val)
211 return -(1L << 20) <= val && val < (1L << 20);
214 static inline int rv_offset(int insn, int off, struct rv_jit_context *ctx)
218 off++; /* BPF branch is from PC+1, RV is from PC */
219 from = (insn > 0) ? ctx->offset[insn - 1] : ctx->prologue_len;
220 to = (insn + off > 0) ? ctx->offset[insn + off - 1] : ctx->prologue_len;
221 return ninsns_rvoff(to - from);
224 /* Instruction formats. */
226 static inline u32 rv_r_insn(u8 funct7, u8 rs2, u8 rs1, u8 funct3, u8 rd,
229 return (funct7 << 25) | (rs2 << 20) | (rs1 << 15) | (funct3 << 12) |
233 static inline u32 rv_i_insn(u16 imm11_0, u8 rs1, u8 funct3, u8 rd, u8 opcode)
235 return (imm11_0 << 20) | (rs1 << 15) | (funct3 << 12) | (rd << 7) |
239 static inline u32 rv_s_insn(u16 imm11_0, u8 rs2, u8 rs1, u8 funct3, u8 opcode)
241 u8 imm11_5 = imm11_0 >> 5, imm4_0 = imm11_0 & 0x1f;
243 return (imm11_5 << 25) | (rs2 << 20) | (rs1 << 15) | (funct3 << 12) |
244 (imm4_0 << 7) | opcode;
247 static inline u32 rv_b_insn(u16 imm12_1, u8 rs2, u8 rs1, u8 funct3, u8 opcode)
249 u8 imm12 = ((imm12_1 & 0x800) >> 5) | ((imm12_1 & 0x3f0) >> 4);
250 u8 imm4_1 = ((imm12_1 & 0xf) << 1) | ((imm12_1 & 0x400) >> 10);
252 return (imm12 << 25) | (rs2 << 20) | (rs1 << 15) | (funct3 << 12) |
253 (imm4_1 << 7) | opcode;
256 static inline u32 rv_u_insn(u32 imm31_12, u8 rd, u8 opcode)
258 return (imm31_12 << 12) | (rd << 7) | opcode;
261 static inline u32 rv_j_insn(u32 imm20_1, u8 rd, u8 opcode)
265 imm = (imm20_1 & 0x80000) | ((imm20_1 & 0x3ff) << 9) |
266 ((imm20_1 & 0x400) >> 2) | ((imm20_1 & 0x7f800) >> 11);
268 return (imm << 12) | (rd << 7) | opcode;
271 static inline u32 rv_amo_insn(u8 funct5, u8 aq, u8 rl, u8 rs2, u8 rs1,
272 u8 funct3, u8 rd, u8 opcode)
274 u8 funct7 = (funct5 << 2) | (aq << 1) | rl;
276 return rv_r_insn(funct7, rs2, rs1, funct3, rd, opcode);
279 /* RISC-V compressed instruction formats. */
281 static inline u16 rv_cr_insn(u8 funct4, u8 rd, u8 rs2, u8 op)
283 return (funct4 << 12) | (rd << 7) | (rs2 << 2) | op;
286 static inline u16 rv_ci_insn(u8 funct3, u32 imm6, u8 rd, u8 op)
290 imm = ((imm6 & 0x20) << 7) | ((imm6 & 0x1f) << 2);
291 return (funct3 << 13) | (rd << 7) | op | imm;
294 static inline u16 rv_css_insn(u8 funct3, u32 uimm, u8 rs2, u8 op)
296 return (funct3 << 13) | (uimm << 7) | (rs2 << 2) | op;
299 static inline u16 rv_ciw_insn(u8 funct3, u32 uimm, u8 rd, u8 op)
301 return (funct3 << 13) | (uimm << 5) | ((rd & 0x7) << 2) | op;
304 static inline u16 rv_cl_insn(u8 funct3, u32 imm_hi, u8 rs1, u32 imm_lo, u8 rd,
307 return (funct3 << 13) | (imm_hi << 10) | ((rs1 & 0x7) << 7) |
308 (imm_lo << 5) | ((rd & 0x7) << 2) | op;
311 static inline u16 rv_cs_insn(u8 funct3, u32 imm_hi, u8 rs1, u32 imm_lo, u8 rs2,
314 return (funct3 << 13) | (imm_hi << 10) | ((rs1 & 0x7) << 7) |
315 (imm_lo << 5) | ((rs2 & 0x7) << 2) | op;
318 static inline u16 rv_ca_insn(u8 funct6, u8 rd, u8 funct2, u8 rs2, u8 op)
320 return (funct6 << 10) | ((rd & 0x7) << 7) | (funct2 << 5) |
321 ((rs2 & 0x7) << 2) | op;
324 static inline u16 rv_cb_insn(u8 funct3, u32 imm6, u8 funct2, u8 rd, u8 op)
328 imm = ((imm6 & 0x20) << 7) | ((imm6 & 0x1f) << 2);
329 return (funct3 << 13) | (funct2 << 10) | ((rd & 0x7) << 7) | op | imm;
332 /* Instructions shared by both RV32 and RV64. */
334 static inline u32 rv_addi(u8 rd, u8 rs1, u16 imm11_0)
336 return rv_i_insn(imm11_0, rs1, 0, rd, 0x13);
339 static inline u32 rv_andi(u8 rd, u8 rs1, u16 imm11_0)
341 return rv_i_insn(imm11_0, rs1, 7, rd, 0x13);
344 static inline u32 rv_ori(u8 rd, u8 rs1, u16 imm11_0)
346 return rv_i_insn(imm11_0, rs1, 6, rd, 0x13);
349 static inline u32 rv_xori(u8 rd, u8 rs1, u16 imm11_0)
351 return rv_i_insn(imm11_0, rs1, 4, rd, 0x13);
354 static inline u32 rv_slli(u8 rd, u8 rs1, u16 imm11_0)
356 return rv_i_insn(imm11_0, rs1, 1, rd, 0x13);
359 static inline u32 rv_srli(u8 rd, u8 rs1, u16 imm11_0)
361 return rv_i_insn(imm11_0, rs1, 5, rd, 0x13);
364 static inline u32 rv_srai(u8 rd, u8 rs1, u16 imm11_0)
366 return rv_i_insn(0x400 | imm11_0, rs1, 5, rd, 0x13);
369 static inline u32 rv_lui(u8 rd, u32 imm31_12)
371 return rv_u_insn(imm31_12, rd, 0x37);
374 static inline u32 rv_auipc(u8 rd, u32 imm31_12)
376 return rv_u_insn(imm31_12, rd, 0x17);
379 static inline u32 rv_add(u8 rd, u8 rs1, u8 rs2)
381 return rv_r_insn(0, rs2, rs1, 0, rd, 0x33);
384 static inline u32 rv_sub(u8 rd, u8 rs1, u8 rs2)
386 return rv_r_insn(0x20, rs2, rs1, 0, rd, 0x33);
389 static inline u32 rv_sltu(u8 rd, u8 rs1, u8 rs2)
391 return rv_r_insn(0, rs2, rs1, 3, rd, 0x33);
394 static inline u32 rv_and(u8 rd, u8 rs1, u8 rs2)
396 return rv_r_insn(0, rs2, rs1, 7, rd, 0x33);
399 static inline u32 rv_or(u8 rd, u8 rs1, u8 rs2)
401 return rv_r_insn(0, rs2, rs1, 6, rd, 0x33);
404 static inline u32 rv_xor(u8 rd, u8 rs1, u8 rs2)
406 return rv_r_insn(0, rs2, rs1, 4, rd, 0x33);
409 static inline u32 rv_sll(u8 rd, u8 rs1, u8 rs2)
411 return rv_r_insn(0, rs2, rs1, 1, rd, 0x33);
414 static inline u32 rv_srl(u8 rd, u8 rs1, u8 rs2)
416 return rv_r_insn(0, rs2, rs1, 5, rd, 0x33);
419 static inline u32 rv_sra(u8 rd, u8 rs1, u8 rs2)
421 return rv_r_insn(0x20, rs2, rs1, 5, rd, 0x33);
424 static inline u32 rv_mul(u8 rd, u8 rs1, u8 rs2)
426 return rv_r_insn(1, rs2, rs1, 0, rd, 0x33);
429 static inline u32 rv_mulhu(u8 rd, u8 rs1, u8 rs2)
431 return rv_r_insn(1, rs2, rs1, 3, rd, 0x33);
434 static inline u32 rv_divu(u8 rd, u8 rs1, u8 rs2)
436 return rv_r_insn(1, rs2, rs1, 5, rd, 0x33);
439 static inline u32 rv_remu(u8 rd, u8 rs1, u8 rs2)
441 return rv_r_insn(1, rs2, rs1, 7, rd, 0x33);
444 static inline u32 rv_jal(u8 rd, u32 imm20_1)
446 return rv_j_insn(imm20_1, rd, 0x6f);
449 static inline u32 rv_jalr(u8 rd, u8 rs1, u16 imm11_0)
451 return rv_i_insn(imm11_0, rs1, 0, rd, 0x67);
454 static inline u32 rv_beq(u8 rs1, u8 rs2, u16 imm12_1)
456 return rv_b_insn(imm12_1, rs2, rs1, 0, 0x63);
459 static inline u32 rv_bne(u8 rs1, u8 rs2, u16 imm12_1)
461 return rv_b_insn(imm12_1, rs2, rs1, 1, 0x63);
464 static inline u32 rv_bltu(u8 rs1, u8 rs2, u16 imm12_1)
466 return rv_b_insn(imm12_1, rs2, rs1, 6, 0x63);
469 static inline u32 rv_bgtu(u8 rs1, u8 rs2, u16 imm12_1)
471 return rv_bltu(rs2, rs1, imm12_1);
474 static inline u32 rv_bgeu(u8 rs1, u8 rs2, u16 imm12_1)
476 return rv_b_insn(imm12_1, rs2, rs1, 7, 0x63);
479 static inline u32 rv_bleu(u8 rs1, u8 rs2, u16 imm12_1)
481 return rv_bgeu(rs2, rs1, imm12_1);
484 static inline u32 rv_blt(u8 rs1, u8 rs2, u16 imm12_1)
486 return rv_b_insn(imm12_1, rs2, rs1, 4, 0x63);
489 static inline u32 rv_bgt(u8 rs1, u8 rs2, u16 imm12_1)
491 return rv_blt(rs2, rs1, imm12_1);
494 static inline u32 rv_bge(u8 rs1, u8 rs2, u16 imm12_1)
496 return rv_b_insn(imm12_1, rs2, rs1, 5, 0x63);
499 static inline u32 rv_ble(u8 rs1, u8 rs2, u16 imm12_1)
501 return rv_bge(rs2, rs1, imm12_1);
504 static inline u32 rv_lw(u8 rd, u16 imm11_0, u8 rs1)
506 return rv_i_insn(imm11_0, rs1, 2, rd, 0x03);
509 static inline u32 rv_lbu(u8 rd, u16 imm11_0, u8 rs1)
511 return rv_i_insn(imm11_0, rs1, 4, rd, 0x03);
514 static inline u32 rv_lhu(u8 rd, u16 imm11_0, u8 rs1)
516 return rv_i_insn(imm11_0, rs1, 5, rd, 0x03);
519 static inline u32 rv_sb(u8 rs1, u16 imm11_0, u8 rs2)
521 return rv_s_insn(imm11_0, rs2, rs1, 0, 0x23);
524 static inline u32 rv_sh(u8 rs1, u16 imm11_0, u8 rs2)
526 return rv_s_insn(imm11_0, rs2, rs1, 1, 0x23);
529 static inline u32 rv_sw(u8 rs1, u16 imm11_0, u8 rs2)
531 return rv_s_insn(imm11_0, rs2, rs1, 2, 0x23);
534 static inline u32 rv_amoadd_w(u8 rd, u8 rs2, u8 rs1, u8 aq, u8 rl)
536 return rv_amo_insn(0, aq, rl, rs2, rs1, 2, rd, 0x2f);
539 static inline u32 rv_amoand_w(u8 rd, u8 rs2, u8 rs1, u8 aq, u8 rl)
541 return rv_amo_insn(0xc, aq, rl, rs2, rs1, 2, rd, 0x2f);
544 static inline u32 rv_amoor_w(u8 rd, u8 rs2, u8 rs1, u8 aq, u8 rl)
546 return rv_amo_insn(0x8, aq, rl, rs2, rs1, 2, rd, 0x2f);
549 static inline u32 rv_amoxor_w(u8 rd, u8 rs2, u8 rs1, u8 aq, u8 rl)
551 return rv_amo_insn(0x4, aq, rl, rs2, rs1, 2, rd, 0x2f);
554 static inline u32 rv_amoswap_w(u8 rd, u8 rs2, u8 rs1, u8 aq, u8 rl)
556 return rv_amo_insn(0x1, aq, rl, rs2, rs1, 2, rd, 0x2f);
559 static inline u32 rv_lr_w(u8 rd, u8 rs2, u8 rs1, u8 aq, u8 rl)
561 return rv_amo_insn(0x2, aq, rl, rs2, rs1, 2, rd, 0x2f);
564 static inline u32 rv_sc_w(u8 rd, u8 rs2, u8 rs1, u8 aq, u8 rl)
566 return rv_amo_insn(0x3, aq, rl, rs2, rs1, 2, rd, 0x2f);
569 static inline u32 rv_fence(u8 pred, u8 succ)
571 u16 imm11_0 = pred << 4 | succ;
573 return rv_i_insn(imm11_0, 0, 0, 0, 0xf);
576 /* RVC instrutions. */
578 static inline u16 rvc_addi4spn(u8 rd, u32 imm10)
582 imm = ((imm10 & 0x30) << 2) | ((imm10 & 0x3c0) >> 4) |
583 ((imm10 & 0x4) >> 1) | ((imm10 & 0x8) >> 3);
584 return rv_ciw_insn(0x0, imm, rd, 0x0);
587 static inline u16 rvc_lw(u8 rd, u32 imm7, u8 rs1)
591 imm_hi = (imm7 & 0x38) >> 3;
592 imm_lo = ((imm7 & 0x4) >> 1) | ((imm7 & 0x40) >> 6);
593 return rv_cl_insn(0x2, imm_hi, rs1, imm_lo, rd, 0x0);
596 static inline u16 rvc_sw(u8 rs1, u32 imm7, u8 rs2)
600 imm_hi = (imm7 & 0x38) >> 3;
601 imm_lo = ((imm7 & 0x4) >> 1) | ((imm7 & 0x40) >> 6);
602 return rv_cs_insn(0x6, imm_hi, rs1, imm_lo, rs2, 0x0);
605 static inline u16 rvc_addi(u8 rd, u32 imm6)
607 return rv_ci_insn(0, imm6, rd, 0x1);
610 static inline u16 rvc_li(u8 rd, u32 imm6)
612 return rv_ci_insn(0x2, imm6, rd, 0x1);
615 static inline u16 rvc_addi16sp(u32 imm10)
619 imm = ((imm10 & 0x200) >> 4) | (imm10 & 0x10) | ((imm10 & 0x40) >> 3) |
620 ((imm10 & 0x180) >> 6) | ((imm10 & 0x20) >> 5);
621 return rv_ci_insn(0x3, imm, RV_REG_SP, 0x1);
624 static inline u16 rvc_lui(u8 rd, u32 imm6)
626 return rv_ci_insn(0x3, imm6, rd, 0x1);
629 static inline u16 rvc_srli(u8 rd, u32 imm6)
631 return rv_cb_insn(0x4, imm6, 0, rd, 0x1);
634 static inline u16 rvc_srai(u8 rd, u32 imm6)
636 return rv_cb_insn(0x4, imm6, 0x1, rd, 0x1);
639 static inline u16 rvc_andi(u8 rd, u32 imm6)
641 return rv_cb_insn(0x4, imm6, 0x2, rd, 0x1);
644 static inline u16 rvc_sub(u8 rd, u8 rs)
646 return rv_ca_insn(0x23, rd, 0, rs, 0x1);
649 static inline u16 rvc_xor(u8 rd, u8 rs)
651 return rv_ca_insn(0x23, rd, 0x1, rs, 0x1);
654 static inline u16 rvc_or(u8 rd, u8 rs)
656 return rv_ca_insn(0x23, rd, 0x2, rs, 0x1);
659 static inline u16 rvc_and(u8 rd, u8 rs)
661 return rv_ca_insn(0x23, rd, 0x3, rs, 0x1);
664 static inline u16 rvc_slli(u8 rd, u32 imm6)
666 return rv_ci_insn(0, imm6, rd, 0x2);
669 static inline u16 rvc_lwsp(u8 rd, u32 imm8)
673 imm = ((imm8 & 0xc0) >> 6) | (imm8 & 0x3c);
674 return rv_ci_insn(0x2, imm, rd, 0x2);
677 static inline u16 rvc_jr(u8 rs1)
679 return rv_cr_insn(0x8, rs1, RV_REG_ZERO, 0x2);
682 static inline u16 rvc_mv(u8 rd, u8 rs)
684 return rv_cr_insn(0x8, rd, rs, 0x2);
687 static inline u16 rvc_jalr(u8 rs1)
689 return rv_cr_insn(0x9, rs1, RV_REG_ZERO, 0x2);
692 static inline u16 rvc_add(u8 rd, u8 rs)
694 return rv_cr_insn(0x9, rd, rs, 0x2);
697 static inline u16 rvc_swsp(u32 imm8, u8 rs2)
701 imm = (imm8 & 0x3c) | ((imm8 & 0xc0) >> 6);
702 return rv_css_insn(0x6, imm, rs2, 0x2);
706 * RV64-only instructions.
708 * These instructions are not available on RV32. Wrap them below a #if to
709 * ensure that the RV32 JIT doesn't emit any of these instructions.
712 #if __riscv_xlen == 64
714 static inline u32 rv_addiw(u8 rd, u8 rs1, u16 imm11_0)
716 return rv_i_insn(imm11_0, rs1, 0, rd, 0x1b);
719 static inline u32 rv_slliw(u8 rd, u8 rs1, u16 imm11_0)
721 return rv_i_insn(imm11_0, rs1, 1, rd, 0x1b);
724 static inline u32 rv_srliw(u8 rd, u8 rs1, u16 imm11_0)
726 return rv_i_insn(imm11_0, rs1, 5, rd, 0x1b);
729 static inline u32 rv_sraiw(u8 rd, u8 rs1, u16 imm11_0)
731 return rv_i_insn(0x400 | imm11_0, rs1, 5, rd, 0x1b);
734 static inline u32 rv_addw(u8 rd, u8 rs1, u8 rs2)
736 return rv_r_insn(0, rs2, rs1, 0, rd, 0x3b);
739 static inline u32 rv_subw(u8 rd, u8 rs1, u8 rs2)
741 return rv_r_insn(0x20, rs2, rs1, 0, rd, 0x3b);
744 static inline u32 rv_sllw(u8 rd, u8 rs1, u8 rs2)
746 return rv_r_insn(0, rs2, rs1, 1, rd, 0x3b);
749 static inline u32 rv_srlw(u8 rd, u8 rs1, u8 rs2)
751 return rv_r_insn(0, rs2, rs1, 5, rd, 0x3b);
754 static inline u32 rv_sraw(u8 rd, u8 rs1, u8 rs2)
756 return rv_r_insn(0x20, rs2, rs1, 5, rd, 0x3b);
759 static inline u32 rv_mulw(u8 rd, u8 rs1, u8 rs2)
761 return rv_r_insn(1, rs2, rs1, 0, rd, 0x3b);
764 static inline u32 rv_divuw(u8 rd, u8 rs1, u8 rs2)
766 return rv_r_insn(1, rs2, rs1, 5, rd, 0x3b);
769 static inline u32 rv_remuw(u8 rd, u8 rs1, u8 rs2)
771 return rv_r_insn(1, rs2, rs1, 7, rd, 0x3b);
774 static inline u32 rv_ld(u8 rd, u16 imm11_0, u8 rs1)
776 return rv_i_insn(imm11_0, rs1, 3, rd, 0x03);
779 static inline u32 rv_lwu(u8 rd, u16 imm11_0, u8 rs1)
781 return rv_i_insn(imm11_0, rs1, 6, rd, 0x03);
784 static inline u32 rv_sd(u8 rs1, u16 imm11_0, u8 rs2)
786 return rv_s_insn(imm11_0, rs2, rs1, 3, 0x23);
789 static inline u32 rv_amoadd_d(u8 rd, u8 rs2, u8 rs1, u8 aq, u8 rl)
791 return rv_amo_insn(0, aq, rl, rs2, rs1, 3, rd, 0x2f);
794 static inline u32 rv_amoand_d(u8 rd, u8 rs2, u8 rs1, u8 aq, u8 rl)
796 return rv_amo_insn(0xc, aq, rl, rs2, rs1, 3, rd, 0x2f);
799 static inline u32 rv_amoor_d(u8 rd, u8 rs2, u8 rs1, u8 aq, u8 rl)
801 return rv_amo_insn(0x8, aq, rl, rs2, rs1, 3, rd, 0x2f);
804 static inline u32 rv_amoxor_d(u8 rd, u8 rs2, u8 rs1, u8 aq, u8 rl)
806 return rv_amo_insn(0x4, aq, rl, rs2, rs1, 3, rd, 0x2f);
809 static inline u32 rv_amoswap_d(u8 rd, u8 rs2, u8 rs1, u8 aq, u8 rl)
811 return rv_amo_insn(0x1, aq, rl, rs2, rs1, 3, rd, 0x2f);
814 static inline u32 rv_lr_d(u8 rd, u8 rs2, u8 rs1, u8 aq, u8 rl)
816 return rv_amo_insn(0x2, aq, rl, rs2, rs1, 3, rd, 0x2f);
819 static inline u32 rv_sc_d(u8 rd, u8 rs2, u8 rs1, u8 aq, u8 rl)
821 return rv_amo_insn(0x3, aq, rl, rs2, rs1, 3, rd, 0x2f);
824 /* RV64-only RVC instructions. */
826 static inline u16 rvc_ld(u8 rd, u32 imm8, u8 rs1)
830 imm_hi = (imm8 & 0x38) >> 3;
831 imm_lo = (imm8 & 0xc0) >> 6;
832 return rv_cl_insn(0x3, imm_hi, rs1, imm_lo, rd, 0x0);
835 static inline u16 rvc_sd(u8 rs1, u32 imm8, u8 rs2)
839 imm_hi = (imm8 & 0x38) >> 3;
840 imm_lo = (imm8 & 0xc0) >> 6;
841 return rv_cs_insn(0x7, imm_hi, rs1, imm_lo, rs2, 0x0);
844 static inline u16 rvc_subw(u8 rd, u8 rs)
846 return rv_ca_insn(0x27, rd, 0, rs, 0x1);
849 static inline u16 rvc_addiw(u8 rd, u32 imm6)
851 return rv_ci_insn(0x1, imm6, rd, 0x1);
854 static inline u16 rvc_ldsp(u8 rd, u32 imm9)
858 imm = ((imm9 & 0x1c0) >> 6) | (imm9 & 0x38);
859 return rv_ci_insn(0x3, imm, rd, 0x2);
862 static inline u16 rvc_sdsp(u32 imm9, u8 rs2)
866 imm = (imm9 & 0x38) | ((imm9 & 0x1c0) >> 6);
867 return rv_css_insn(0x7, imm, rs2, 0x2);
870 #endif /* __riscv_xlen == 64 */
872 /* Helper functions that emit RVC instructions when possible. */
874 static inline void emit_jalr(u8 rd, u8 rs, s32 imm, struct rv_jit_context *ctx)
876 if (rvc_enabled() && rd == RV_REG_RA && rs && !imm)
877 emitc(rvc_jalr(rs), ctx);
878 else if (rvc_enabled() && !rd && rs && !imm)
879 emitc(rvc_jr(rs), ctx);
881 emit(rv_jalr(rd, rs, imm), ctx);
884 static inline void emit_mv(u8 rd, u8 rs, struct rv_jit_context *ctx)
886 if (rvc_enabled() && rd && rs)
887 emitc(rvc_mv(rd, rs), ctx);
889 emit(rv_addi(rd, rs, 0), ctx);
892 static inline void emit_add(u8 rd, u8 rs1, u8 rs2, struct rv_jit_context *ctx)
894 if (rvc_enabled() && rd && rd == rs1 && rs2)
895 emitc(rvc_add(rd, rs2), ctx);
897 emit(rv_add(rd, rs1, rs2), ctx);
900 static inline void emit_addi(u8 rd, u8 rs, s32 imm, struct rv_jit_context *ctx)
902 if (rvc_enabled() && rd == RV_REG_SP && rd == rs && is_10b_int(imm) && imm && !(imm & 0xf))
903 emitc(rvc_addi16sp(imm), ctx);
904 else if (rvc_enabled() && is_creg(rd) && rs == RV_REG_SP && is_10b_uint(imm) &&
906 emitc(rvc_addi4spn(rd, imm), ctx);
907 else if (rvc_enabled() && rd && rd == rs && imm && is_6b_int(imm))
908 emitc(rvc_addi(rd, imm), ctx);
910 emit(rv_addi(rd, rs, imm), ctx);
913 static inline void emit_li(u8 rd, s32 imm, struct rv_jit_context *ctx)
915 if (rvc_enabled() && rd && is_6b_int(imm))
916 emitc(rvc_li(rd, imm), ctx);
918 emit(rv_addi(rd, RV_REG_ZERO, imm), ctx);
921 static inline void emit_lui(u8 rd, s32 imm, struct rv_jit_context *ctx)
923 if (rvc_enabled() && rd && rd != RV_REG_SP && is_6b_int(imm) && imm)
924 emitc(rvc_lui(rd, imm), ctx);
926 emit(rv_lui(rd, imm), ctx);
929 static inline void emit_slli(u8 rd, u8 rs, s32 imm, struct rv_jit_context *ctx)
931 if (rvc_enabled() && rd && rd == rs && imm && (u32)imm < __riscv_xlen)
932 emitc(rvc_slli(rd, imm), ctx);
934 emit(rv_slli(rd, rs, imm), ctx);
937 static inline void emit_andi(u8 rd, u8 rs, s32 imm, struct rv_jit_context *ctx)
939 if (rvc_enabled() && is_creg(rd) && rd == rs && is_6b_int(imm))
940 emitc(rvc_andi(rd, imm), ctx);
942 emit(rv_andi(rd, rs, imm), ctx);
945 static inline void emit_srli(u8 rd, u8 rs, s32 imm, struct rv_jit_context *ctx)
947 if (rvc_enabled() && is_creg(rd) && rd == rs && imm && (u32)imm < __riscv_xlen)
948 emitc(rvc_srli(rd, imm), ctx);
950 emit(rv_srli(rd, rs, imm), ctx);
953 static inline void emit_srai(u8 rd, u8 rs, s32 imm, struct rv_jit_context *ctx)
955 if (rvc_enabled() && is_creg(rd) && rd == rs && imm && (u32)imm < __riscv_xlen)
956 emitc(rvc_srai(rd, imm), ctx);
958 emit(rv_srai(rd, rs, imm), ctx);
961 static inline void emit_sub(u8 rd, u8 rs1, u8 rs2, struct rv_jit_context *ctx)
963 if (rvc_enabled() && is_creg(rd) && rd == rs1 && is_creg(rs2))
964 emitc(rvc_sub(rd, rs2), ctx);
966 emit(rv_sub(rd, rs1, rs2), ctx);
969 static inline void emit_or(u8 rd, u8 rs1, u8 rs2, struct rv_jit_context *ctx)
971 if (rvc_enabled() && is_creg(rd) && rd == rs1 && is_creg(rs2))
972 emitc(rvc_or(rd, rs2), ctx);
974 emit(rv_or(rd, rs1, rs2), ctx);
977 static inline void emit_and(u8 rd, u8 rs1, u8 rs2, struct rv_jit_context *ctx)
979 if (rvc_enabled() && is_creg(rd) && rd == rs1 && is_creg(rs2))
980 emitc(rvc_and(rd, rs2), ctx);
982 emit(rv_and(rd, rs1, rs2), ctx);
985 static inline void emit_xor(u8 rd, u8 rs1, u8 rs2, struct rv_jit_context *ctx)
987 if (rvc_enabled() && is_creg(rd) && rd == rs1 && is_creg(rs2))
988 emitc(rvc_xor(rd, rs2), ctx);
990 emit(rv_xor(rd, rs1, rs2), ctx);
993 static inline void emit_lw(u8 rd, s32 off, u8 rs1, struct rv_jit_context *ctx)
995 if (rvc_enabled() && rs1 == RV_REG_SP && rd && is_8b_uint(off) && !(off & 0x3))
996 emitc(rvc_lwsp(rd, off), ctx);
997 else if (rvc_enabled() && is_creg(rd) && is_creg(rs1) && is_7b_uint(off) && !(off & 0x3))
998 emitc(rvc_lw(rd, off, rs1), ctx);
1000 emit(rv_lw(rd, off, rs1), ctx);
1003 static inline void emit_sw(u8 rs1, s32 off, u8 rs2, struct rv_jit_context *ctx)
1005 if (rvc_enabled() && rs1 == RV_REG_SP && is_8b_uint(off) && !(off & 0x3))
1006 emitc(rvc_swsp(off, rs2), ctx);
1007 else if (rvc_enabled() && is_creg(rs1) && is_creg(rs2) && is_7b_uint(off) && !(off & 0x3))
1008 emitc(rvc_sw(rs1, off, rs2), ctx);
1010 emit(rv_sw(rs1, off, rs2), ctx);
1013 /* RV64-only helper functions. */
1014 #if __riscv_xlen == 64
1016 static inline void emit_addiw(u8 rd, u8 rs, s32 imm, struct rv_jit_context *ctx)
1018 if (rvc_enabled() && rd && rd == rs && is_6b_int(imm))
1019 emitc(rvc_addiw(rd, imm), ctx);
1021 emit(rv_addiw(rd, rs, imm), ctx);
1024 static inline void emit_ld(u8 rd, s32 off, u8 rs1, struct rv_jit_context *ctx)
1026 if (rvc_enabled() && rs1 == RV_REG_SP && rd && is_9b_uint(off) && !(off & 0x7))
1027 emitc(rvc_ldsp(rd, off), ctx);
1028 else if (rvc_enabled() && is_creg(rd) && is_creg(rs1) && is_8b_uint(off) && !(off & 0x7))
1029 emitc(rvc_ld(rd, off, rs1), ctx);
1031 emit(rv_ld(rd, off, rs1), ctx);
1034 static inline void emit_sd(u8 rs1, s32 off, u8 rs2, struct rv_jit_context *ctx)
1036 if (rvc_enabled() && rs1 == RV_REG_SP && is_9b_uint(off) && !(off & 0x7))
1037 emitc(rvc_sdsp(off, rs2), ctx);
1038 else if (rvc_enabled() && is_creg(rs1) && is_creg(rs2) && is_8b_uint(off) && !(off & 0x7))
1039 emitc(rvc_sd(rs1, off, rs2), ctx);
1041 emit(rv_sd(rs1, off, rs2), ctx);
1044 static inline void emit_subw(u8 rd, u8 rs1, u8 rs2, struct rv_jit_context *ctx)
1046 if (rvc_enabled() && is_creg(rd) && rd == rs1 && is_creg(rs2))
1047 emitc(rvc_subw(rd, rs2), ctx);
1049 emit(rv_subw(rd, rs1, rs2), ctx);
1052 #endif /* __riscv_xlen == 64 */
1054 void bpf_jit_build_prologue(struct rv_jit_context *ctx);
1055 void bpf_jit_build_epilogue(struct rv_jit_context *ctx);
1057 int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx,
1060 #endif /* _BPF_JIT_H */