arch/riscv/kernel/probes/simulate-insn.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2
   3 #ifndef _RISCV_KERNEL_PROBES_SIMULATE_INSN_H
   4 #define _RISCV_KERNEL_PROBES_SIMULATE_INSN_H
   5
   6 #include <asm/insn.h>
   7
   8 #define RISCV_INSN_REJECTED(name, code)                                 \
   9         do {                                                            \
  10                 if (riscv_insn_is_##name(code)) {                       \
  11                         return INSN_REJECTED;                           \
  12                 }                                                       \
  13         } while (0)
  14
  15 #define RISCV_INSN_SET_SIMULATE(name, code)                             \
  16         do {                                                            \
  17                 if (riscv_insn_is_##name(code)) {                       \
  18                         api->handler = simulate_##name;                 \
  19                         return INSN_GOOD_NO_SLOT;                       \
  20                 }                                                       \
  21         } while (0)
  22
  23 bool simulate_auipc(u32 opcode, unsigned long addr, struct pt_regs *regs);
  24 bool simulate_branch(u32 opcode, unsigned long addr, struct pt_regs *regs);
  25 bool simulate_jal(u32 opcode, unsigned long addr, struct pt_regs *regs);
  26 bool simulate_jalr(u32 opcode, unsigned long addr, struct pt_regs *regs);
  27 bool simulate_c_j(u32 opcode, unsigned long addr, struct pt_regs *regs);
  28 bool simulate_c_jr(u32 opcode, unsigned long addr, struct pt_regs *regs);
  29 bool simulate_c_jalr(u32 opcode, unsigned long addr, struct pt_regs *regs);
  30 bool simulate_c_bnez(u32 opcode, unsigned long addr, struct pt_regs *regs);
  31 bool simulate_c_beqz(u32 opcode, unsigned long addr, struct pt_regs *regs);
  32
  33 #endif /* _RISCV_KERNEL_PROBES_SIMULATE_INSN_H */