1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012 Regents of the University of California
6 #include <linux/acpi.h>
8 #include <linux/ctype.h>
9 #include <linux/init.h>
10 #include <linux/seq_file.h>
13 #include <asm/cpufeature.h>
15 #include <asm/hwcap.h>
18 #include <asm/pgtable.h>
20 bool arch_match_cpu_phys_id(int cpu, u64 phys_id)
22 return phys_id == cpuid_to_hartid_map(cpu);
26 * Returns the hart ID of the given device tree node, or -ENODEV if the node
27 * isn't an enabled and valid RISC-V hart node.
29 int riscv_of_processor_hartid(struct device_node *node, unsigned long *hart)
33 *hart = (unsigned long)of_get_cpu_hwid(node, 0);
35 pr_warn("Found CPU without hart ID\n");
39 cpu = riscv_hartid_to_cpuid(*hart);
43 if (!cpu_possible(cpu))
49 int __init riscv_early_of_processor_hartid(struct device_node *node, unsigned long *hart)
53 if (!of_device_is_compatible(node, "riscv")) {
54 pr_warn("Found incompatible CPU\n");
58 *hart = (unsigned long)of_get_cpu_hwid(node, 0);
60 pr_warn("Found CPU without hart ID\n");
64 if (!of_device_is_available(node)) {
65 pr_info("CPU with hartid=%lu is not available\n", *hart);
69 if (of_property_read_string(node, "riscv,isa-base", &isa))
72 if (IS_ENABLED(CONFIG_32BIT) && strncasecmp(isa, "rv32i", 5)) {
73 pr_warn("CPU with hartid=%lu does not support rv32i", *hart);
77 if (IS_ENABLED(CONFIG_64BIT) && strncasecmp(isa, "rv64i", 5)) {
78 pr_warn("CPU with hartid=%lu does not support rv64i", *hart);
82 if (!of_property_present(node, "riscv,isa-extensions"))
85 if (of_property_match_string(node, "riscv,isa-extensions", "i") < 0 ||
86 of_property_match_string(node, "riscv,isa-extensions", "m") < 0 ||
87 of_property_match_string(node, "riscv,isa-extensions", "a") < 0) {
88 pr_warn("CPU with hartid=%lu does not support ima", *hart);
95 if (!riscv_isa_fallback) {
96 pr_warn("CPU with hartid=%lu is invalid: this kernel does not parse \"riscv,isa\"",
101 if (of_property_read_string(node, "riscv,isa", &isa)) {
102 pr_warn("CPU with hartid=%lu has no \"riscv,isa-base\" or \"riscv,isa\" property\n",
107 if (IS_ENABLED(CONFIG_32BIT) && strncasecmp(isa, "rv32ima", 7)) {
108 pr_warn("CPU with hartid=%lu does not support rv32ima", *hart);
112 if (IS_ENABLED(CONFIG_64BIT) && strncasecmp(isa, "rv64ima", 7)) {
113 pr_warn("CPU with hartid=%lu does not support rv64ima", *hart);
121 * Find hart ID of the CPU DT node under which given DT node falls.
123 * To achieve this, we walk up the DT tree until we find an active
124 * RISC-V core (HART) node and extract the cpuid from it.
126 int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid)
128 for (; node; node = node->parent) {
129 if (of_device_is_compatible(node, "riscv")) {
130 *hartid = (unsigned long)of_get_cpu_hwid(node, 0);
131 if (*hartid == ~0UL) {
132 pr_warn("Found CPU without hart ID\n");
142 DEFINE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo);
144 unsigned long riscv_cached_mvendorid(unsigned int cpu_id)
146 struct riscv_cpuinfo *ci = per_cpu_ptr(&riscv_cpuinfo, cpu_id);
148 return ci->mvendorid;
150 EXPORT_SYMBOL(riscv_cached_mvendorid);
152 unsigned long riscv_cached_marchid(unsigned int cpu_id)
154 struct riscv_cpuinfo *ci = per_cpu_ptr(&riscv_cpuinfo, cpu_id);
158 EXPORT_SYMBOL(riscv_cached_marchid);
160 unsigned long riscv_cached_mimpid(unsigned int cpu_id)
162 struct riscv_cpuinfo *ci = per_cpu_ptr(&riscv_cpuinfo, cpu_id);
166 EXPORT_SYMBOL(riscv_cached_mimpid);
168 static int riscv_cpuinfo_starting(unsigned int cpu)
170 struct riscv_cpuinfo *ci = this_cpu_ptr(&riscv_cpuinfo);
172 #if IS_ENABLED(CONFIG_RISCV_SBI)
173 ci->mvendorid = sbi_spec_is_0_1() ? 0 : sbi_get_mvendorid();
174 ci->marchid = sbi_spec_is_0_1() ? 0 : sbi_get_marchid();
175 ci->mimpid = sbi_spec_is_0_1() ? 0 : sbi_get_mimpid();
176 #elif IS_ENABLED(CONFIG_RISCV_M_MODE)
177 ci->mvendorid = csr_read(CSR_MVENDORID);
178 ci->marchid = csr_read(CSR_MARCHID);
179 ci->mimpid = csr_read(CSR_MIMPID);
189 static int __init riscv_cpuinfo_init(void)
193 ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "riscv/cpuinfo:starting",
194 riscv_cpuinfo_starting, NULL);
196 pr_err("cpuinfo: failed to register hotplug callbacks.\n");
202 arch_initcall(riscv_cpuinfo_init);
204 #ifdef CONFIG_PROC_FS
206 static void print_isa(struct seq_file *f, const unsigned long *isa_bitmap)
209 if (IS_ENABLED(CONFIG_32BIT))
210 seq_write(f, "rv32", 4);
212 seq_write(f, "rv64", 4);
214 for (int i = 0; i < riscv_isa_ext_count; i++) {
215 if (!__riscv_isa_extension_available(isa_bitmap, riscv_isa_ext[i].id))
218 /* Only multi-letter extensions are split by underscores */
219 if (strnlen(riscv_isa_ext[i].name, 2) != 1)
222 seq_printf(f, "%s", riscv_isa_ext[i].name);
228 static void print_mmu(struct seq_file *f)
233 #if defined(CONFIG_32BIT)
235 #elif defined(CONFIG_64BIT)
236 if (pgtable_l5_enabled)
238 else if (pgtable_l4_enabled)
245 #endif /* CONFIG_MMU */
246 seq_printf(f, "mmu\t\t: %s\n", sv_type);
249 static void *c_start(struct seq_file *m, loff_t *pos)
251 if (*pos == nr_cpu_ids)
254 *pos = cpumask_next(*pos - 1, cpu_online_mask);
255 if ((*pos) < nr_cpu_ids)
256 return (void *)(uintptr_t)(1 + *pos);
260 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
263 return c_start(m, pos);
266 static void c_stop(struct seq_file *m, void *v)
270 static int c_show(struct seq_file *m, void *v)
272 unsigned long cpu_id = (unsigned long)v - 1;
273 struct riscv_cpuinfo *ci = per_cpu_ptr(&riscv_cpuinfo, cpu_id);
274 struct device_node *node;
277 seq_printf(m, "processor\t: %lu\n", cpu_id);
278 seq_printf(m, "hart\t\t: %lu\n", cpuid_to_hartid_map(cpu_id));
281 * For historical raisins, the isa: line is limited to the lowest common
282 * denominator of extensions supported across all harts. A true list of
283 * extensions supported on this hart is printed later in the hart isa:
286 seq_puts(m, "isa\t\t: ");
291 node = of_get_cpu_node(cpu_id, NULL);
293 if (!of_property_read_string(node, "compatible", &compat) &&
294 strcmp(compat, "riscv"))
295 seq_printf(m, "uarch\t\t: %s\n", compat);
300 seq_printf(m, "mvendorid\t: 0x%lx\n", ci->mvendorid);
301 seq_printf(m, "marchid\t\t: 0x%lx\n", ci->marchid);
302 seq_printf(m, "mimpid\t\t: 0x%lx\n", ci->mimpid);
305 * Print the ISA extensions specific to this hart, which may show
306 * additional extensions not present across all harts.
308 seq_puts(m, "hart isa\t: ");
309 print_isa(m, hart_isa[cpu_id].isa);
315 const struct seq_operations cpuinfo_op = {
322 #endif /* CONFIG_PROC_FS */