1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012 Regents of the University of California
6 #include <linux/init.h>
7 #include <linux/seq_file.h>
11 #include <asm/pgtable.h>
14 * Returns the hart ID of the given device tree node, or -ENODEV if the node
15 * isn't an enabled and valid RISC-V hart node.
17 int riscv_of_processor_hartid(struct device_node *node)
22 if (!of_device_is_compatible(node, "riscv")) {
23 pr_warn("Found incompatible CPU\n");
27 hart = of_get_cpu_hwid(node, 0);
29 pr_warn("Found CPU without hart ID\n");
33 if (!of_device_is_available(node)) {
34 pr_info("CPU with hartid=%d is not available\n", hart);
38 if (of_property_read_string(node, "riscv,isa", &isa)) {
39 pr_warn("CPU with hartid=%d has no \"riscv,isa\" property\n", hart);
42 if (isa[0] != 'r' || isa[1] != 'v') {
43 pr_warn("CPU with hartid=%d has an invalid ISA of \"%s\"\n", hart, isa);
51 * Find hart ID of the CPU DT node under which given DT node falls.
53 * To achieve this, we walk up the DT tree until we find an active
54 * RISC-V core (HART) node and extract the cpuid from it.
56 int riscv_of_parent_hartid(struct device_node *node)
58 for (; node; node = node->parent) {
59 if (of_device_is_compatible(node, "riscv"))
60 return riscv_of_processor_hartid(node);
67 #define __RISCV_ISA_EXT_DATA(UPROP, EXTID) \
70 .isa_ext_id = EXTID, \
73 * Here are the ordering rules of extension naming defined by RISC-V
75 * 1. All extensions should be separated from other multi-letter extensions
77 * 2. The first letter following the 'Z' conventionally indicates the most
78 * closely related alphabetical extension category, IMAFDQLCBKJTPVH.
79 * If multiple 'Z' extensions are named, they should be ordered first
80 * by category, then alphabetically within a category.
81 * 3. Standard supervisor-level extensions (starts with 'S') should be
82 * listed after standard unprivileged extensions. If multiple
83 * supervisor-level extensions are listed, they should be ordered
85 * 4. Non-standard extensions (starts with 'X') must be listed after all
86 * standard extensions. They must be separated from other multi-letter
87 * extensions by an underscore.
89 static struct riscv_isa_ext_data isa_ext_arr[] = {
90 __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
91 __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT),
92 __RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX),
95 static void print_isa_ext(struct seq_file *f)
97 struct riscv_isa_ext_data *edata;
100 arr_sz = ARRAY_SIZE(isa_ext_arr) - 1;
102 /* No extension support available */
106 for (i = 0; i <= arr_sz; i++) {
107 edata = &isa_ext_arr[i];
108 if (!__riscv_isa_extension_available(NULL, edata->isa_ext_id))
110 seq_printf(f, "_%s", edata->uprop);
115 * These are the only valid base (single letter) ISA extensions as per the spec.
116 * It also specifies the canonical order in which it appears in the spec.
117 * Some of the extension may just be a place holder for now (B, K, P, J).
118 * This should be updated once corresponding extensions are ratified.
120 static const char base_riscv_exts[13] = "imafdqcbkjpvh";
122 static void print_isa(struct seq_file *f, const char *isa)
126 seq_puts(f, "isa\t\t: ");
127 /* Print the rv[64/32] part */
128 seq_write(f, isa, 4);
129 for (i = 0; i < sizeof(base_riscv_exts); i++) {
130 if (__riscv_isa_extension_available(NULL, base_riscv_exts[i] - 'a'))
131 /* Print only enabled the base ISA extensions */
132 seq_write(f, &base_riscv_exts[i], 1);
138 static void print_mmu(struct seq_file *f)
143 #if defined(CONFIG_32BIT)
144 strncpy(sv_type, "sv32", 5);
145 #elif defined(CONFIG_64BIT)
146 if (pgtable_l5_enabled)
147 strncpy(sv_type, "sv57", 5);
148 else if (pgtable_l4_enabled)
149 strncpy(sv_type, "sv48", 5);
151 strncpy(sv_type, "sv39", 5);
154 strncpy(sv_type, "none", 5);
155 #endif /* CONFIG_MMU */
156 seq_printf(f, "mmu\t\t: %s\n", sv_type);
159 static void *c_start(struct seq_file *m, loff_t *pos)
161 *pos = cpumask_next(*pos - 1, cpu_online_mask);
162 if ((*pos) < nr_cpu_ids)
163 return (void *)(uintptr_t)(1 + *pos);
167 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
170 return c_start(m, pos);
173 static void c_stop(struct seq_file *m, void *v)
177 static int c_show(struct seq_file *m, void *v)
179 unsigned long cpu_id = (unsigned long)v - 1;
180 struct device_node *node = of_get_cpu_node(cpu_id, NULL);
181 const char *compat, *isa;
183 seq_printf(m, "processor\t: %lu\n", cpu_id);
184 seq_printf(m, "hart\t\t: %lu\n", cpuid_to_hartid_map(cpu_id));
185 if (!of_property_read_string(node, "riscv,isa", &isa))
188 if (!of_property_read_string(node, "compatible", &compat)
189 && strcmp(compat, "riscv"))
190 seq_printf(m, "uarch\t\t: %s\n", compat);
197 const struct seq_operations cpuinfo_op = {
204 #endif /* CONFIG_PROC_FS */