1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012 Regents of the University of California
7 #include <linux/init.h>
8 #include <linux/seq_file.h>
11 #include <asm/hwcap.h>
14 #include <asm/pgtable.h>
17 * Returns the hart ID of the given device tree node, or -ENODEV if the node
18 * isn't an enabled and valid RISC-V hart node.
20 int riscv_of_processor_hartid(struct device_node *node, unsigned long *hart)
24 if (!of_device_is_compatible(node, "riscv")) {
25 pr_warn("Found incompatible CPU\n");
29 *hart = (unsigned long) of_get_cpu_hwid(node, 0);
31 pr_warn("Found CPU without hart ID\n");
35 if (!of_device_is_available(node)) {
36 pr_info("CPU with hartid=%lu is not available\n", *hart);
40 if (of_property_read_string(node, "riscv,isa", &isa)) {
41 pr_warn("CPU with hartid=%lu has no \"riscv,isa\" property\n", *hart);
44 if (isa[0] != 'r' || isa[1] != 'v') {
45 pr_warn("CPU with hartid=%lu has an invalid ISA of \"%s\"\n", *hart, isa);
53 * Find hart ID of the CPU DT node under which given DT node falls.
55 * To achieve this, we walk up the DT tree until we find an active
56 * RISC-V core (HART) node and extract the cpuid from it.
58 int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid)
60 for (; node; node = node->parent) {
61 if (of_device_is_compatible(node, "riscv")) {
62 *hartid = (unsigned long)of_get_cpu_hwid(node, 0);
63 if (*hartid == ~0UL) {
64 pr_warn("Found CPU without hart ID\n");
76 struct riscv_cpuinfo {
77 unsigned long mvendorid;
78 unsigned long marchid;
81 static DEFINE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo);
83 static int riscv_cpuinfo_starting(unsigned int cpu)
85 struct riscv_cpuinfo *ci = this_cpu_ptr(&riscv_cpuinfo);
87 #if IS_ENABLED(CONFIG_RISCV_SBI)
88 ci->mvendorid = sbi_spec_is_0_1() ? 0 : sbi_get_mvendorid();
89 ci->marchid = sbi_spec_is_0_1() ? 0 : sbi_get_marchid();
90 ci->mimpid = sbi_spec_is_0_1() ? 0 : sbi_get_mimpid();
91 #elif IS_ENABLED(CONFIG_RISCV_M_MODE)
92 ci->mvendorid = csr_read(CSR_MVENDORID);
93 ci->marchid = csr_read(CSR_MARCHID);
94 ci->mimpid = csr_read(CSR_MIMPID);
104 static int __init riscv_cpuinfo_init(void)
108 ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "riscv/cpuinfo:starting",
109 riscv_cpuinfo_starting, NULL);
111 pr_err("cpuinfo: failed to register hotplug callbacks.\n");
117 device_initcall(riscv_cpuinfo_init);
119 #define __RISCV_ISA_EXT_DATA(UPROP, EXTID) \
122 .isa_ext_id = EXTID, \
125 * Here are the ordering rules of extension naming defined by RISC-V
127 * 1. All extensions should be separated from other multi-letter extensions
129 * 2. The first letter following the 'Z' conventionally indicates the most
130 * closely related alphabetical extension category, IMAFDQLCBKJTPVH.
131 * If multiple 'Z' extensions are named, they should be ordered first
132 * by category, then alphabetically within a category.
133 * 3. Standard supervisor-level extensions (starts with 'S') should be
134 * listed after standard unprivileged extensions. If multiple
135 * supervisor-level extensions are listed, they should be ordered
137 * 4. Non-standard extensions (starts with 'X') must be listed after all
138 * standard extensions. They must be separated from other multi-letter
139 * extensions by an underscore.
141 static struct riscv_isa_ext_data isa_ext_arr[] = {
142 __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
143 __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC),
144 __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL),
145 __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT),
146 __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM),
147 __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),
148 __RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX),
151 static void print_isa_ext(struct seq_file *f)
153 struct riscv_isa_ext_data *edata;
156 arr_sz = ARRAY_SIZE(isa_ext_arr) - 1;
158 /* No extension support available */
162 for (i = 0; i <= arr_sz; i++) {
163 edata = &isa_ext_arr[i];
164 if (!__riscv_isa_extension_available(NULL, edata->isa_ext_id))
166 seq_printf(f, "_%s", edata->uprop);
171 * These are the only valid base (single letter) ISA extensions as per the spec.
172 * It also specifies the canonical order in which it appears in the spec.
173 * Some of the extension may just be a place holder for now (B, K, P, J).
174 * This should be updated once corresponding extensions are ratified.
176 static const char base_riscv_exts[13] = "imafdqcbkjpvh";
178 static void print_isa(struct seq_file *f, const char *isa)
182 seq_puts(f, "isa\t\t: ");
183 /* Print the rv[64/32] part */
184 seq_write(f, isa, 4);
185 for (i = 0; i < sizeof(base_riscv_exts); i++) {
186 if (__riscv_isa_extension_available(NULL, base_riscv_exts[i] - 'a'))
187 /* Print only enabled the base ISA extensions */
188 seq_write(f, &base_riscv_exts[i], 1);
194 static void print_mmu(struct seq_file *f)
199 #if defined(CONFIG_32BIT)
200 strncpy(sv_type, "sv32", 5);
201 #elif defined(CONFIG_64BIT)
202 if (pgtable_l5_enabled)
203 strncpy(sv_type, "sv57", 5);
204 else if (pgtable_l4_enabled)
205 strncpy(sv_type, "sv48", 5);
207 strncpy(sv_type, "sv39", 5);
210 strncpy(sv_type, "none", 5);
211 #endif /* CONFIG_MMU */
212 seq_printf(f, "mmu\t\t: %s\n", sv_type);
215 static void *c_start(struct seq_file *m, loff_t *pos)
217 if (*pos == nr_cpu_ids)
220 *pos = cpumask_next(*pos - 1, cpu_online_mask);
221 if ((*pos) < nr_cpu_ids)
222 return (void *)(uintptr_t)(1 + *pos);
226 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
229 return c_start(m, pos);
232 static void c_stop(struct seq_file *m, void *v)
236 static int c_show(struct seq_file *m, void *v)
238 unsigned long cpu_id = (unsigned long)v - 1;
239 struct device_node *node = of_get_cpu_node(cpu_id, NULL);
240 struct riscv_cpuinfo *ci = per_cpu_ptr(&riscv_cpuinfo, cpu_id);
241 const char *compat, *isa;
243 seq_printf(m, "processor\t: %lu\n", cpu_id);
244 seq_printf(m, "hart\t\t: %lu\n", cpuid_to_hartid_map(cpu_id));
245 if (!of_property_read_string(node, "riscv,isa", &isa))
248 if (!of_property_read_string(node, "compatible", &compat)
249 && strcmp(compat, "riscv"))
250 seq_printf(m, "uarch\t\t: %s\n", compat);
251 seq_printf(m, "mvendorid\t: 0x%lx\n", ci->mvendorid);
252 seq_printf(m, "marchid\t\t: 0x%lx\n", ci->marchid);
253 seq_printf(m, "mimpid\t\t: 0x%lx\n", ci->mimpid);
260 const struct seq_operations cpuinfo_op = {
267 #endif /* CONFIG_PROC_FS */